Scott Mansell
2e5f59cdc1
Merge pull request #734 from Sonicadvance1/remove_warnings_4
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Removes warnings from OpcodeDispatcher
2021-02-01 16:45:37 +13:00
Scott Mansell
767813eb97
Merge pull request #735 from Sonicadvance1/remove_warnings_5
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Removes warning from X86Tables
2021-02-01 16:44:24 +13:00
Scott Mansell
5f624bec05
Merge pull request #733 from Sonicadvance1/remove_warnings_3
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Removes warnings from x86-64 JIT.cpp
2021-02-01 16:42:10 +13:00
Ryan Houdek
9e55f1b177
Removes warning from X86Tables
2021-01-31 07:58:08 -08:00
Ryan Houdek
6012fcfee6
Removes warnings from OpcodeDispatcher
2021-01-31 07:57:28 -08:00
Ryan Houdek
c2f4ea4646
Removes warnings from x86-64 JIT.cpp
2021-01-31 07:56:19 -08:00
Ryan Houdek
1f6017c37c
Removes warnings from Frontend
2021-01-31 07:55:26 -08:00
Stefanos Kornilios Mitsis Poiitidis
1f7d815f3a
LookupCache: Fix crash on L2 insertion
2021-01-29 22:00:07 +02:00
Stefanos Kornilios Mitsis Poiitidis
9ecde7a0b8
Interpreter: Move execution to IntepreterOps::ExecuteIR, single core refactor
2021-01-29 15:17:37 +02:00
Stefanos Kornilios Mitsis Poiitidis
972219043d
Core: Refactor compilation driver, lifetime of objects
2021-01-29 10:42:55 +02:00
Stefanos Kornilios Mitsis Poiitidis
0e00d3dc15
RA: Optimize RAData
2021-01-29 10:42:48 +02:00
Stefanos Kornilios Mitsis Poiitidis
a45c2c34e9
RA: Use RAData directly
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
513112919b
RA: Move allocation data to RAData
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
791aa4c32c
LookupCache: Add a third level cache that will always resolve all known blocks
2021-01-29 01:53:12 +02:00
Stefanos Kornilios Mitsis Poiitidis
0c9e05ed8f
Rename BlockCache to LookupCache
2021-01-29 01:31:48 +02:00
Stefanos Kornilios Mitsis Poiitidis
f872e178ac
Merge pull request #718 from Sonicadvance1/32bit_sigret_handler
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Forces SIGRET handler to the lower 32bits VA on 32bit processes
2021-01-27 20:16:51 +02:00
Stefanos Kornilios Mitsis Poiitidis
ec31dc0872
Merge pull request #716 from Sonicadvance1/describe_tag
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Puts the FEX describe tag in CPUID
2021-01-27 20:10:46 +02:00
Ryan Houdek
2437b89c7b
Forces SIGRET handler to the lower 32bits VA on 32bit processes
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This is visible to the guest process so for 32bit it needs to be in the
lower 32bits.
2021-01-27 07:54:30 -08:00
Ryan Houdek
5673a0e213
Puts the FEX describe tag in CPUID
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This is what shows up in /proc/cpuinfo
example on tagged release: 'model name : FEX-2101'
example on untagged release: 'model name : FEX-2101-64-g536be23f'
Fixes #661
2021-01-27 07:20:14 -08:00
Ryan Houdek
3df344a78d
Fixes some asserts from vixl and a bug in ExitSpillSRA
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Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.
Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location
2021-01-27 00:53:27 -08:00
Ryan Houdek
6bca290611
Implements VBSL on AArch64
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This isn't quite optimal without RA constraints
2021-01-26 03:01:48 -08:00
Ryan Houdek
513cb27825
Add TSX names to decode tables so we know what they are
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Rather than just stating UND
We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis
b0365871b6
OpDisp: Address most 32-bit rip size issues
2021-01-25 15:04:12 +02:00
Ryan Houdek
d4ffea5c31
Merge pull request #670 from FEX-Emu/skmp/faster-ra
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IR: Optimize runtime of optimization passes
2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis
3bd8731b26
IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner
2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis
13613c6de1
IR: Change ValidateCode to use two uint64_t instead of __uint128_t
2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis
1177c375ff
IR: Further parser cleanups, add fence types
2021-01-21 21:17:27 +02:00
Ryan Houdek
633ea045e5
Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler
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cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.
Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.
Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.
If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis
a9332e604a
JIT/x64: Fix VAddV
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
567e315854
Frontend, OpDisp: Don't assert on invalid instructions
2021-01-18 17:19:11 +02:00
Stefanos Kornilios Mitsis Poiitidis
aa0cd76e06
OpDisp: Remove missed debug printf
2021-01-18 10:03:31 +02:00
Ryan Houdek
fbe67db93b
Merge pull request #657 from FEX-Emu/skmp/block-ordering
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OpDisp: Improved Block Ordering
2021-01-17 23:39:53 -08:00
Ryan Houdek
63f9b62594
Merge pull request #497 from FEX-Emu/skmp/block-linking
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Block linking
2021-01-17 23:35:40 -08:00
Stefanos Kornilios Mitsis Poiitidis
eb430815ad
Jit: Add Block Linking information
2021-01-16 12:30:32 +02:00
Stefanos Kornilios Mitsis Poiitidis
41d0f84710
OpDisp: Improve block ordering interface, optimize branching order and conds
2021-01-15 21:05:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
5fdbb8a9b2
OpDisp: Improve block ordering for multi-block ops
2021-01-15 21:05:29 +02:00
Ryan Houdek
8d81a925ee
Allows JITSymbols to see central dispatcher
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Will let us see in perf how much time is spent there
2021-01-14 13:05:24 -08:00
Stefanos Kornilios Mitsis Poiitidis
3507328232
JIT/x64: Add block linking for x86_64
2021-01-13 22:16:07 +02:00
Stefanos Kornilios Mitsis Poiitidis
c46b932b26
JIT/arm64: Implement block linking
2021-01-13 22:03:46 +02:00
Ryan Houdek
e884525434
Fixes 16bit addr offset calculation
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In the case of 16bit addressing mode, the upper bits 16bits are zext
prior to result.
2021-01-13 12:02:19 -08:00
Ryan Houdek
1084ecf2d3
Fixes more 16bit modrm addressing problems
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In the case of an instruction that used 16bit addressing mode. It would
calculate the amount of displacement needing to be read using a 32bit
modrm mode. It would then read calculate modrm displacement again and
read the correct number of bytes.
Leftover bytes would then be in a mismatched state which means if an
instruction was using 16bit addressing + modrm + literal at /that/ point
the number of literal bytes remaining would be calculated as a negative.
This didn't actually break things since instructions that have modrm +
literal and can safely use 16bit addressing without breaking in a 32bit
environment is impossible on Linux. Due to the inability to map a memory
range in 16bit range.
2021-01-13 12:02:19 -08:00
Ryan Houdek
96b2c6ca8b
Merge pull request #637 from FEX-Emu/skmp/unsyncronized-rip
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Dispatch: ExitFunction InlineConstant & unsynchronized rip
2021-01-13 10:58:58 -08:00
Stefanos Kornilios Mitsis Poiitidis
8758348dfd
Dispatch: Support constant Rips, don't syncronize on context on ddisp
2021-01-13 17:26:40 +02:00
duck
ade89bba6a
XXX -> TODO
2021-01-12 15:19:45 -05:00
duck
059594cbd3
Add a quick comment for potential optimization
2021-01-12 15:15:41 -05:00
duck
501bccdd80
Faster PMOVMSKB, part 2
2021-01-12 14:06:52 -05:00
duck
49afb6bceb
Faster PMOVMSKB instruction.
2021-01-12 14:06:51 -05:00
duck
464eb13b93
One-byte horizontal add support on x86-64.
2021-01-12 11:10:16 -05:00
Stefanos Kornilios Mitsis Poiitidis
552895b896
Merge pull request #626 from Sonicadvance1/fix_16bit_addressing
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Fixes 16bit ModRM rm decoding
2021-01-11 16:19:56 +02:00
duck
a63339c50d
Fix JCC negative offsets as well
2021-01-11 03:34:52 -05:00
