Commit Graph
26 Commits
Author SHA1 Message Date
Scott Mansell 2babc1292c GdbServer: Breakpoint intergation 2020-03-06 07:56:01 +02:00
Ryan Houdek e0e708a9c0 Fixes three instructions necessary for shared apps to run
Fixes MOVHPD which was failing.
Fixes FXSTOR and FXSAVE which was accidently loading the memory location
rather than doing an LEA of the address.
2020-03-06 07:56:01 +02:00
Ryan Houdek af5a562508 Fixes bug in STOS and CMPS
We were storing one too many elements. So even if the counter register
was zero it would do a store or comparison
2020-03-06 07:56:00 +02:00
Scott Mansell 8a6efad301 Stub FNSTCW/FLDCW so libc.so.6 can be loaded
Apparently doesn't need any other x86 instructions.
Or anything more than noped out state save/restore.
2020-03-06 07:56:00 +02:00
Ryan Houdek 3f06f3e87d Fixes bug in PUSH op with RSP source.
We were modifying RSP to adjust the stack first.
Then if the source used RSP then it was offset by the store size.

`push [rsp]` was broken before this
2020-03-06 07:56:00 +02:00
Ryan Houdek 2df55d303a Fixes bug in SHR op
Smaller ops could have been shifting data from the larger source in to
the smaller op space when it should have been zero'd
2020-03-06 07:55:59 +02:00
Ryan Houdek afdbd9ebdc Fixes issues with PSLLDQ and PSRLDQ
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions

This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
2020-03-06 07:55:59 +02:00
Scott Mansell 20fc6a489e Fix STOS to not load SSA regs across blocks 2020-03-06 07:55:45 +02:00
Ryan Houdek 9e132e107a Adds alignment information to the mem loadstore IR ops
Allows us to not always emit unaligned loadstore ops for these
2020-03-06 07:55:45 +02:00
Ryan Houdek 435357e06e Fixes a bug in STOS 2020-03-06 07:55:44 +02:00
Ryan Houdek 3a041c3b1c Fixes bug in block creation for any block containing RET.
Would have a redundant StoreContext after the RET which broke IR
analysis
2020-03-06 07:55:44 +02:00
Ryan Houdek e1cecbcfe3 Changes to the new multiblock frontend decoder
Simple linear scan forward of instruction decoding isn't viable to do.
We need to break up the decoding at the block boundaries.
Otherwise our decoding gets in to the weeds and decodes trash.
2020-03-06 07:55:37 +02:00
Ryan Houdek b7c7a34cf6 Changes (aggressively) how branching is handled in the frontend.
This changes over CondJump to have a defined True and False branch path.
Additionally needing to change over everything to handle this.
This now means that a false branch condition will no longer assume
fallthrough past this instruction.
Currently the x86-64 JIT generates an additional jmp instruction on
fallthrough that isn't optimized away.

This is working towards improvements in our IR branching model and
improving IRValidation in doing so.
This is working towards the model that IRBlocks can only have 0-2
successors.
Ret/Exit - 0 successors
Jump - 2 successors
CondJump - 2 successors

TBD:
Syscall/CPUID - Breaking block?
2020-03-06 07:55:37 +02:00
Scott Mansell d1f2d85d0c Fix up usage tracking of Args.
Make sure we keep them up to date when removing
nodes.
2020-03-06 07:55:36 +02:00
Ryan Houdek 012805fd72 Fixes multiblock and a few bugs in RA.
This makes it so multiblock can now be enabled with the JITs.
Results in a decent performance increase by itself.
2020-03-06 07:55:35 +02:00
Ryan Houdek 570ff7b29b Supports FS/GS on CMPXCHG 2020-03-06 07:55:33 +02:00
Ryan Houdek 52b5ac9e19 Changes slightly how IR::IRHeader is represented 2020-03-06 07:55:33 +02:00
Ryan Houdek 6d92146578 Flesh out X86Tables some more
Adds an EVEX table and throws some ops in to an unimplemented function.
This is necessary for multiblock in the future where it will see
unsupported instructions but not actually execute them.
2020-03-06 07:55:18 +02:00
Ryan Houdek 4ccdd689ce Fixes a bug in the CBW/CWDE/CDQE instruction
Was running at the wrong size the entire time
2020-03-06 07:55:14 +02:00
Ryan Houdek 199cfd76d8 Refactor IR and other changes that are hard to split
I had to change how blocks are represented to make it easier to parse
This required a fairly substantial refactor that makes it so blocks are
represented differently and we can walk them sequentially.

This will make future analysis easier to deal with.
Had to rewrite the passes and core's parsing of the IR afterwards.

Moved RA in to a optimization pass to be shared between the JIT backends
This works because x86-64 and AArch64 RA can be identical.

Still doesn't support PHI nodes or spilling correctly, this is the first
step in the process of getting there.
2020-03-06 07:55:13 +02:00
Ryan Houdek 92d4aaf2e2 Partial FXSave/FXRStor instruction implementations. 2020-03-06 07:52:35 +02:00
Ryan Houdek 3e4743512d Stub FXSave and FXRStor instructions. Necessary for launching dynamic apps from ld.so 2020-03-06 07:52:34 +02:00
Ryan Houdek 46f983fbb6 Minor fix to SHL op to not update flags if the shift amount was zero. 2020-03-06 07:52:32 +02:00
Ryan Houdek f503bd573f Fix CBW/CWDE/CDQE instruction storage 2020-03-06 07:52:28 +02:00
Ryan Houdek 40cad15da9 Cleanup old IR emitter functions
Argumentless IR emitter functions were prone to generating invalid code.
Remove them from the python emitter and change the branch instructions
that were using them to a new version instead.
Adds NumUse tracking as well.
2020-03-06 07:48:41 +02:00
Ryan Houdek 7252050e42 Initial commit 2020-03-06 07:48:39 +02:00