steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-10 16:00:31 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity
12,219 Commits 11 Branches 71 Tags
16d5ca447fa38d46df4e29d474ce51ea536cce41
Commit Graph
2031 Commits
Author SHA1 Message Date
Ryan Houdek 16d5ca447f FEXCore: DebugData is never null now 
This is a required data structure to exist.

CID 482036
 2025-06-19 16:21:19 -07:00
Alyssa Rosenzweig 059d980c33 IR: give StoreRegister a precoloured destination 
this will eliminate an annoying special case in post-RA opts.

No difference proven at 95.0% confidence

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-19 13:44:23 -04:00
Alyssa Rosenzweig e57130e364 JIT: drop UDiv extensions 
we already extend in the dispatcher.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-12 16:45:49 -04:00
Alyssa Rosenzweig eedcb35270 IR: merge ldiv/lrem handlers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-12 16:45:49 -04:00
Alyssa Rosenzweig 1eb470083c IR: merge div/rem opcodes 
it's simpler & faster to calculate both together, matching the x86 semantic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-10 17:08:20 -04:00
Alyssa Rosenzweig 6864d48dcf OpcodeDispatcher: optimize cdq 
prereq to optimizing sign-ext+ldiv in a reasonable way.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-03 15:00:06 -04:00
Alyssa Rosenzweig 7d734740be Addressing: avoid a Bfe 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 06299cca4b OpcodeDispatcher: optimize out Bfi for storereg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig af5aaab38b OpcodeDispatcher: optimize a few ALU-with-constant ops 
instead of relying on ConstProp for this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 77bb01d384 OpcodeDispatcher: don't generate pointless Xor for AF 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig a9eb1bd4e6 OpcodeDispatcher: don't generate pointless Bfe for moves 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 83ef2da95f OpcodeDispatcher: avoid zero shift in SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig ba13ccadb8 OpcodeDispatcher: use ArithRef for 8/16-bit imul 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 4a2dee873d OpcodeDispatcher: use ArithRef for small rotates 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 589906e6e6 OpcodeDispatcher: generalize AF on constants optimization 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig f0fcf6d9e6 OpcodeDispatcher: optimize SVE vmovmskpd 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 1591ced5a7 OpcodeDispatcher: use ArithRef for ADC/SBB flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 0d235d63d0 OpcodeDispatcher: use ArithRef for bit tests 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 820d5c1447 OpcodeDispatcher: use ArithRef for rotates 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 8093e8f5f1 OpcodeDispatcher: optimize LoadDir 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig 802857e411 OpcodeDispatcher: add ArithRef helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig bf3a1839a2 OpcodeDispatcher: transform DF ourselves 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Alyssa Rosenzweig ad7844d7da OpcodeDispatcher: do not generate useless VMov 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-06-02 14:15:51 -04:00
Tony Wasserka a792dd0703 CPUBackend: Clean up CodeBuffer size limits 2025-06-01 22:45:50 +02:00
Tony Wasserka a9a6a645bf Arm64Emitter: Disable PC-relative constant encoding 
This no longer works since the JIT output is now relocated before execution.
 2025-06-01 22:45:50 +02:00
Tony Wasserka 7c93becd5f JIT: Increase estimate for CodeBuffer space use 
The previous bound was exceeded during Steam startup before.
 2025-06-01 22:45:50 +02:00
Tony Wasserka 4bbaef58e9 JIT: Re-enable parallel compilation by compiling to a temporary buffer 2025-06-01 22:45:50 +02:00
Tony Wasserka 95791a985a Core: Minimize the time CodeBufferWriteMutex is held 2025-06-01 22:45:50 +02:00
Tony Wasserka 0dfefe9730 Core: Re-check LookupCache before running compiler backend 
This further reduces lock contention by skipping the backend phase in case
another thread raced the active one for the same block.
 2025-06-01 22:45:49 +02:00
Tony Wasserka 8481c797df FEXCore/JIT: Extend LookupCache lock to all of ExitFunctionLink 2025-06-01 22:44:49 +02:00
Tony Wasserka a503b5e20b Rename CodeBufferManager reference 2025-06-01 22:44:49 +02:00
Tony Wasserka 4078840ef1 Core: Reduce JIT time by sharing CodeBuffers between threads 
This is changes the interface of CodeBuffer to that of a partially persistent
data structure based on reference counting:
- Exactly one CodeBuffer is now designated as "active", which means data can
  be *appended* to it
- Lossy modifications to the active CodeBuffer will not invalidate any data
  in use by other threads, which enables save sharing across threads
- Instead, such lossy modifications trigger a new "version" of the data in
  the modifying thread. Old versions of the CodeBuffer persist as read-only
  data for use by the other threads.
- The other threads can update their version of the CodeBuffer. This will
  decrease the reference count and eventually trigger deallocation of the
  old version
 2025-06-01 22:44:49 +02:00
Tony Wasserka ab51958b26 Move AllocateNewCodeBuffer from CPUBackend to a new CodeBufferManager interface 2025-06-01 22:42:55 +02:00
Tony Wasserka 3376587b6a CPUBackend: Manage CodeBuffers using shared_ptr 
This is required for sharing CodeBuffers between threads anyway, but it also
allows use of the constructor/destructor to manage memory automatically.
 2025-06-01 22:42:55 +02:00
Tony Wasserka 6681d7dcf9 LookupCache: Split L3 cache into a dedicated interface 
This data isn't really a cache, since the JIT is directly responsible of
writing its contents. Instead it be considered the source to populate the
L1/L2 caches from.

Furthermore, splitting off this data allows it to be shared across threads
in the future without affecting L1/L2 caches.
 2025-06-01 22:42:55 +02:00
Tony Wasserka 34224481c6 LookupCache: Prefer empty() over a size check 2025-06-01 22:42:55 +02:00
Ryan Houdek cdea8d7f74 Merge pull request #4593 from alyssarosenzweig/ici/zeroing-sub-regs 
InstructionCountCI: add more cases for mov 0/~0
 2025-05-29 12:26:15 -07:00
Ryan Houdek ef6dc3d802 Merge pull request #4592 from alyssarosenzweig/opt/x87-tag 
OpcodeDispatcher: optimize X87FTWTag
 2025-05-29 12:26:04 -07:00
Alyssa Rosenzweig 0fbe69ebcf OpcodeDispatcher: optimize xor-with-self flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-28 13:53:38 -04:00
Alyssa Rosenzweig ece817c691 OpcodeDispatcher: optimize logical flags 
seems to be strictly better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-28 13:34:50 -04:00
Alyssa Rosenzweig 3fbc8204b7 OpcodeDispatcher: clean up logical flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-28 13:28:31 -04:00
Alyssa Rosenzweig b8dd5d95b0 OpcodeDispatcher: optimize X87FTWTag 
using bit twiddling tricks :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-28 13:13:16 -04:00
Ryan Houdek 7cd52febc2 FEXCore/CPUID: Remove warning 
This is currently only used on win32 builds because Linux doesn't
understand TPIDRRO.
 2025-05-28 09:28:41 -07:00
Alyssa Rosenzweig 6927c7577a RegisterAllocationPass: delete trivial instructions 
lots of instructions only exist for RA, so RA can garbage collect them before
post-RA passes (including the JIT) deals with them. this simplifies our life
now, and makes post-RA passes a LOT simpler for little cost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-26 15:52:23 -04:00
Alyssa Rosenzweig 61ae53cc03 IR: add paired PushTwo/PopTwo helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-26 15:52:23 -04:00
Alyssa Rosenzweig 0e67f30103 OpcodeDispatcher: make Push do the right thing and use it 
this both optimizes and bug-fixes pusha while deleting a snotton of code.

Closes: https://github.com/FEX-Emu/FEX/issues/4589
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-26 15:52:23 -04:00
Ryan Houdek dc9f8aa855 Merge pull request #4580 from alyssarosenzweig/ir/inline-ra 
IR: Inline registers into the IR
 2025-05-26 09:44:51 -07:00
StanfordZhang 23cda2c961 Update Arm64Emitter.cpp 
fix callee saved floating-point arguments issue
 2025-05-23 22:14:37 +08:00
Alyssa Rosenzweig 65ee1fafa8 IR: drop RegisterAllocationData 
This sideband is now unused, registers are encoded directly in the IR. So we can
garbage collect all this code for quite some savings.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-19 13:42:59 -04:00
Alyssa Rosenzweig 49f8332c5b JIT: use registers directly from the IR 
This is the flag day change from the series, using all the new shiny
infrastructre we added.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-05-19 13:42:59 -04:00