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Code Issues Packages Projects Releases 67 Wiki Activity
6,103 Commits 11 Branches 71 Tags
11d396ca060d4eef536ef59f35a834aaa9dc0668
Commit Graph
2431 Commits
Author SHA1 Message Date
Lioncache c6ba51ee35 ARMEmitter: Handle SVE floating-point compare with zero group 2023-03-09 01:13:33 -05:00
Lioncache 19125720c2 ARMEmitter: Handle SVE Floating-point Serial Reduction (Predicated) group 2023-03-09 00:16:38 -05:00
Lioncache 02d06ee833 ARMEmitter: Handle SVE Floating Point Unary Operations - Unpredicated group 2023-03-08 23:11:50 -05:00
Lioncache 640cfcd0bd ARMEmitter: Make LDR (predicate) take an XRegister 
Matches assembly use more closely.
 2023-03-08 22:45:15 -05:00
Lioncache 5d71dfed86 ARMEmitter: Handle LDR (vector) 
Now we have the vector variant as well as the predicate variant.
 2023-03-08 22:43:13 -05:00
Lioncache a06fc3641f ARMEmitter: Handle FTMAD 
Finishes off the only top-level instruction in the SVE Floating-Point
Arithemtic - Predicated group (also FTMAD is unpredicated, so cool).
 2023-03-08 22:13:49 -05:00
Lioncache 5cbf984743 ARMEmitter: Move op and assertions into SVEFloatArithmeticPredicated helper 
Deduplicates some code.
 2023-03-08 22:13:44 -05:00
Lioncache d9da63d492 OpcodeDispatcher: Handle VPSADBW 2023-03-08 21:02:44 -05:00
Lioncache 597ffe5ba6 OpcodeDispatcher: Factor out PSADBW implementation to helper 
This can be reused when implementing the AVX equivalent of the
operation.
 2023-03-08 18:40:59 -05:00
Lioncache 73ff932bb6 OpcodeDispatcher: Handle VTESTPD 2023-03-08 17:27:41 -05:00
Lioncache 9b742b1fac OpcodeDispatcher: Handle VTESTPS 2023-03-08 17:27:41 -05:00
Lioncache 8c63afb345 OpcodeDispatcher: Add helper for VTESTP{D,S} 2023-03-08 17:27:38 -05:00
Ryan Houdek c14f4355b7 Merge pull request #2478 from lioncash/maddubsw 
OpcodeDispatcher: Handle VPMADDUBSW
 2023-03-08 13:27:43 -08:00
Ryan Houdek 6645e68c95 Merge pull request #2477 from lioncash/mskb 
OpcodeDispatcher: Handle VPMOVMSKB
 2023-03-08 13:19:22 -08:00
Lioncache ff9de85851 OpcodeDispatcher: Handle VPMADDUBSW 2023-03-08 16:01:34 -05:00
Lioncache 4dca609614 OpcodeDispatcher: Factor out PMADDUBSW implementation into helper 
This will be used to centralize the SSE and AVX implementations.
 2023-03-08 15:40:17 -05:00
Lioncache 4fc365c149 OpcodeDispatcher: Handle VPMOVMSKB 2023-03-08 15:29:58 -05:00
Lioncache 8804e0a62a OpcodeDispatcher: Make MOVMSKOpOne suitable for AVX 
Instead of hardcoding most sizes, derive them off the source register
size.

This will allow us to share the implementation between the SSE and AVX.
 2023-03-08 15:29:55 -05:00
Ryan Houdek 1f512b098e Merge pull request #2476 from lioncash/redundant 
Arm64/VectorOps: Remove unnecessary EOR in VAddP/VFAddP SVE path
 2023-03-08 11:21:49 -08:00
Lioncache a31c3ad87a Arm64/VectorOps: Remove unnecessary EOR in VAddP/VFAddP SVE path 
These aren't necessary for the operations anymore.
 2023-03-08 14:05:52 -05:00
Ryan Houdek e92cfc4d7a Merge pull request #2475 from lioncash/extract 
OpcodeDispatcher: Pass full register size through VExtractToGPR
 2023-03-08 10:56:10 -08:00
Lioncache 820d743321 OpcodeDispatcher: Pass full register size through VExtractToGPR 
While the register size field is currently unused, it's correct to
differentiate between 128-bit and 256-bit registers here.
 2023-03-08 13:29:51 -05:00
Ryan Houdek 3b74e34b47 Merge pull request #2474 from lioncash/ffr 
ARMEmitter: Handle SVE Write FFR group
 2023-03-08 10:04:55 -08:00
Lioncache aeff4346e8 ARMEmitter: Handle SVE Write FFR group 2023-03-08 12:37:28 -05:00
Lioncache 5b51440c87 ARMEmitter: Put precondition checks inside SVEBitwiseShiftbyVector 
Lets us deduplicate some code.
 2023-03-08 12:16:47 -05:00
Lioncache baace30e30 ARMEmitter: Move SVEBitwiseShiftbyVector into private section 
This is an internal helper, so it shouldn't be exposed.
 2023-03-08 12:08:58 -05:00
Ryan Houdek 79170a23e5 OpDispatcher: Implements REP MOVS as Memcpy IR op 
Just like the `REP STOS` instruction, this removes a fairly nasty bit of
code generation from our dispatcher. This instruction behaves like a
memcpy/memmove when not dealing with the faulting behaviour around the
instruction.

With a microbench things improves this instruction's throughput by 3.5%
to 25.5% depending on operating size.

There is a TODO for implementing this instruction with ARM's future MOPS
instructions which will accelerate this implementation further.
 2023-03-06 16:39:10 -08:00
Ryan Houdek 81e52ca19f IR: Implements a memcpy operation 
This matches the x86 REP MOVS instruction behaviour.
 2023-03-06 16:38:43 -08:00
Ryan Houdek 5301036968 Int/JIT64: Fixes Memset Prefix 
Accidentally missed appending the prefix to the address in x86 JIT and
interpreter
 2023-03-06 16:37:11 -08:00
Lioncache 9c2d29ee4e ARMEmitter/ASIMDOps: Remove unnecessary template constraints 
Now that our register types are strongly typed and don't implicitly convert
across one another, we can get rid of the templating on some member
functions, turning them into normal member functions.
 2023-03-06 18:37:53 -05:00
Ryan Houdek 4b8ac0f8c6 Merge pull request #2468 from lioncash/asimd 
ARMEmitter/ScalarOps: Move base opcodes into helper functions
 2023-03-06 15:16:29 -08:00
Lioncache 70c93efdfa ScalarOps: Simplify Floating-point data-processing (3 source) category 
We can move the opcode into the helper function
 2023-03-06 17:26:24 -05:00
Lioncache f5e207c28f ScalarOps: Simplify Floating-point data-processing (2 source) 
We can move the base opcode into the helper function
 2023-03-06 17:21:36 -05:00
Lioncache 9c64a22280 ScalarOps: Simplify Floating-point conditional select category 
We can move the base opcode into the helper
 2023-03-06 17:15:47 -05:00
Lioncache 5f57fa4b77 ScalarOps: Simplify Floating-point data-processing (1 source) category 
We can move the opcode into the helper function
 2023-03-06 17:06:58 -05:00
Lioncache fe81523179 ScalarOps: Simplify Advanced SIMD scalar shift by immediate category 
We can move the opcode into the helper
 2023-03-06 16:53:04 -05:00
Lioncache 4be61aaaaf ScalarOps: Simplify Advanced SIMD scalar three same category 
We can move the opcode into the helper
 2023-03-06 16:46:36 -05:00
Lioncache da0681ca81 ScalarOps: Simplify Advanced SIMD scalar three different category 
We can move the opcode into the helper function.
 2023-03-06 16:37:52 -05:00
Lioncache 02258073e3 ScalarOps: Simplify Advanced SIMD scalar two-register miscellaneous category 
We can move the opcode into the helper function.
 2023-03-06 16:34:38 -05:00
Lioncache cde55d44ef ScalarOps: Simplify Advanced SIMD scalar two-register miscellaneous FP16 category 
The opcode can be moved into the helper function, deduplicating it over
several functions
 2023-03-06 16:12:07 -05:00
Lioncache 97c12ef351 ScalarOps: Simplify Advanced SIMD scalar three same FP16 category 
We can move the opcode into the helper itself.
 2023-03-06 16:07:12 -05:00
Ryan Houdek 94e0591601 Merge pull request #2467 from lioncash/unused 
ARMEmitter: Remove unused helper functions
 2023-03-06 12:59:06 -08:00
Lioncache b802f64ffe ScalarOps: Simplify Floating-point compare category 
This category as well can have its opcode moved into the helper function
 2023-03-06 15:58:40 -05:00
Lioncache 0e32d8a8b6 ScalarOps: Simplify Floating-point conditional compare category 
We can move the opcode itself into the helper function, so it can be
deduplicated.
 2023-03-06 15:57:57 -05:00
Lioncache fe8bd17c88 ARMEmitter: Simplify bit size retrieval helpers 
We can collapse the array into a shift, and the others can just use 8 as
the starting value to be shifted instead of multiplying by 8.

Aside from the array change, everything else is likely already constant
folded, but it does make things a little more straightforward
 2023-03-06 15:24:58 -05:00
Lioncache f333068d9a ARMEmitter: Remove unused helper functions 
The templated variants were never used. Also we can just make these
helpers constexpr to begin with.
 2023-03-06 15:21:48 -05:00
Ryan Houdek 3bd4b23af7 Merge pull request #2466 from lioncash/misc 
ARMEmitter: Fully handle SVE Integer Misc - Unpredicated
 2023-03-06 12:19:03 -08:00
Lioncache 77ae7a8a3f ARMEmitter: Fully handle SVE Integer Misc - Unpredicated 
Finishes off an integer category that, at present, has more floating point
operations in it than anything else.
 2023-03-06 15:05:30 -05:00
Lioncache b989bb9569 ARMEmitter: Simplify uses of IsXOrWRegister 
Turns out these can be nicely simplified to being directly in the
template declaration.

Neat little tip pointed out by @neobrain
 2023-03-06 12:05:46 -05:00
Ryan Houdek 7e66508016 OpcodeDispatcher: Optimize REP STOS to MemSet operation 
x86's REP STOS instruction is a memset (with element size!) with the
ability to choose a direction of execution.
Additionally it has a feature where if it faults part-way through the
copy, an application can catch the fault and continue afterwards to know
how many bytes got copied.

RCX is the counter which decrements for each element, and RDI is the
memory pointer. On fault these will reflect the last location that was
attempted to be written. FEX doesn't support this behaviour which makes
our lives easier.

Without supporting that feature, this turns in to a directional memset
by element size. Let's remove all the multiple blocks and just emit a
single IR operation to improve performance of the JIT.
Our generated code here was terrible, the IR was terrible, multiblock is
always slow with RA. Just a general overall improvement.

With profiling pressure-vessel this change deletes the hottest block that
appeared in the trace. This instruction is very commonly used for
memsetting a region to zero so it should be quite fast.

We can also optimize REP MOVS in the future with a Memcpy IR operation
in a similar fashion.

Additionally in the future these can be optimized to use ARM's new MOPS
instructions since the most common case is memset by byte. Which is when
we should expose the "Fast REP STOS" CPUID bit. Both setp/setm/sete and
cpyfp/cpyfm/cpyfe match `REP STOS` and `REP MOVS` respectively.
 2023-03-03 09:16:28 -08:00