Commit Graph
205 Commits
Author SHA1 Message Date
Stefanos Kornilios Mitsis Poiitidis f34f8981ab Merge pull request #638 from Sonicadvance1/irvalidation_memoryleak
Fixes a memory leak in IRValidation
2021-01-13 12:07:33 +02:00
duck c690e65365 Make sure to only record when necessary 2021-01-12 12:49:49 -05:00
duck 4e3934eddd Make DeadContextStoreElimination aware of OP_INVALIDATEFLAGS 2021-01-12 12:47:32 -05:00
Ryan Houdek 8d2eebd644 Fixes a memory leak in IRValidation 2021-01-11 08:47:45 -08:00
Stefanos Kornilios Mitsis Poiitidis f3d5635182 IR: Make ExitFunction take NewRip as an argument, instead of implicit ctx store 2021-01-08 18:41:33 +02:00
Stefanos Kornilios Mitsis Poiitidis dd71a45175 Merge branch 'main' into skmp/static-ra 2021-01-07 01:04:16 +02:00
Stefanos Kornilios Mitsis Poiitidis 101b29c5ee ConstProp: Fix build breakage w/ operator == 2021-01-06 23:31:50 +02:00
Stefanos Kornilios Mitsis Poiitidis 94fb009f4b SRA: Address review feedback 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 82545796b8 static-ra: Use LogMan::* instead of assert/printf 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis b3600a453c RA/SRA: Don't read-alias not full sized regs, it is not safe 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 5f481ff56d IR: Fix Ashr, Ror OpSize calculation 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis c518151800 IR: Fix Lshr op size detection 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 5a3c55f621 RA: Fix Class Conflicts 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 204fda62f1 IR: Fix CreateElementPair edge cases, Remove Load/StoreContextPair 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis fbe87101db IR: Remove Load/StoreContextPair 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 17dc0bfcd8 SRA: Only do read-alias if accessing low part of register 2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c5a1fd5ea SRA: Static Register Allocation, arm64 only 2021-01-05 17:14:57 +02:00
Ryan Houdek 4907bda639 Adds support for proper sized GPR->FPR sized conversions
Both x86 and AArch64 support converting from one sized GPR to another
sized FPR. Expose it in our IR op.

Fixes a bug in CVTSI2SS with a 64bit source and it was treating the
input source as a 32bit value.

eg:
0x0000'0000'FFFF'FFFF was treated as converting to -1 float, which was wrong since it is a 64bit value
2020-12-30 10:07:12 -08:00
Stefanos Kornilios Mitsis Poiitidis 2fbf22a9de Hotfix: Disable ConstProp/RemoveUselessMasking, add a test for it 2020-12-25 15:04:27 +02:00
Stefanos Kornilios Mitsis Poiitidis ef75b8e4ec Merge pull request #582 from Sonicadvance1/move_syscalls
Moves FEXCore's SignalDelegator and SyscallHandler to the frontend
2020-12-16 12:52:39 +02:00
Ryan Houdek e50a03fcdc Some warning fixes and uninitialized values fixes in ConstProp 2020-12-14 04:00:04 -08:00
Ryan Houdek ba134ea634 Fixes a bug in RA that valgrind found
Needs to ensure the interference list only checks against the class
interference if that register fits in its array.

Checking only empty wasn't good enough, check the array size first.
2020-12-14 03:56:39 -08:00
Ryan Houdek 232fac8fb7 Makes sure to memset the invalid node
Valgrind caught it relying on uninitialized values
2020-12-14 03:56:04 -08:00
Ryan Houdek 37983006f0 Moves FEXCore's SignalDelegator and SyscallHandler to the frontend
Sadly these things can't be split without breaking functionality so it
turns in to a bit of a mess.

SyscallHandler is very much something that is a Linux only construct and
shouldn't be in FEXCore itself. Lets the frontend register a
Syscallhandler with FEXCore. FEXCore itself is then aware of the current
syscall ABI and handles the ABI in an optimal fashion.
So it is not a 100% clean break otherwise we would lose performance.

The SignalDelegator then needs to move to the frontend since the
SyscallHandler requires it for signal based syscalls.
The CPU backend signal handling still needs to happen in FEXCore because
it is a very tight coupling with the CPU backend.
Once we need to support more Signal handling we can give the backends
cleaner support to select which specific OS handler to handle.
2020-12-13 22:38:04 -08:00
Stefanos Kornilios Mitsis Poiitidis 22629b6f5a ConstProp: Remove ROR case, ROR no longer exists 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis 0df84be18c ConstProp: Remove some BFEs that do nothing 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis 784cd648f1 ConstProp: SBFE useless masking elim, VMOV elim 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis 60ce62cb2d ConstProp: Special case BFE, AND in RemoveUselessMasking sub-pass 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis 5eb42e4490 ConstProp: Documented different sub-passes, remove leftover continue; statements 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis b2eeb104f7 ConstProp: Add RemoveUselessMasking, implement for a few ops 2020-12-12 12:10:14 +02:00
Stefanos Kornilios Mitsis Poiitidis b044413952 OpDisp, IR, Backends: Add Float compares to Select, CondJump, COND_F* 2020-12-04 15:30:55 +02:00
Stefanos Kornilios Mitsis Poiitidis 3bc13581a8 Merge pull request #557 from FEX-Emu/skmp/memops-imm-pooling
ConstProp: LoadMem/StoreMem imm pooling
2020-12-04 08:54:13 +02:00
Stefanos Kornilios Mitsis Poiitidis 9b6f0df657 Merge pull request #545 from FEX-Emu/skmp/add-dfprse
IR: Add a rather ineffective DeadFPRStoreElim Pass
2020-12-04 08:52:47 +02:00
Stefanos Kornilios Mitsis Poiitidis 8e62a6891b Merge pull request #544 from FEX-Emu/skmp/lse-remove-partial-writes
LSE: Also optimize away partial writes
2020-12-04 08:52:21 +02:00
Stefanos Kornilios Mitsis Poiitidis 003991e495 Merge pull request #503 from Sonicadvance1/remove_duplicate_compaction
Remove duplicated compaction pass
2020-12-04 08:44:21 +02:00
Stefanos Kornilios Mitsis Poiitidis c29f890d7a IR: Add a rather ineffective DeadFPRStoreElim Pass 2020-12-04 08:08:23 +02:00
Stefanos Kornilios Mitsis Poiitidis 2f12fd6ee4 ConstProp: LoadMem/StoreMem imm pooling
If imms used in memops are close enough, generate them with address gen instead
of allocating a new const
2020-12-04 08:04:44 +02:00
Stefanos Kornilios Mitsis Poiitidis d622e7b557 LSE: Also optimize away partial writes 2020-12-04 07:53:33 +02:00
Ryan Houdek bce3d3be8d Merge pull request #556 from FEX-Emu/skmp/fcmp-optimization
ConstProp: FCMP Optimization
2020-12-03 20:21:35 -08:00
Ryan Houdek a0149dff07 Merge pull request #554 from FEX-Emu/skmp/cmt-around-select
CMT: Move unary ops before selects
2020-12-03 20:20:45 -08:00
Ryan Houdek 439d49b802 Merge pull request #550 from FEX-Emu/skmp/improve-dead-flags
DFSE: Fix dead clag calculation, Extend InvalidateFlags
2020-12-03 20:18:43 -08:00
Ryan Houdek 91ee753cae Merge pull request #553 from FEX-Emu/skmp/mul-to-lshl
ConstProp: Mul x,#powof2 -> Lshl x,ctz(#powof2)
2020-12-03 20:10:13 -08:00
Ryan Houdek eb57f5f489 Merge pull request #547 from FEX-Emu/skmp/optimize-flag-access
IR: Move BFEs to SetFlag, remove from OP_STOREFLAG
2020-12-03 20:07:53 -08:00
Ryan Houdek 17402aa02d Remove duplicated compaction pass
RA Pass and passmanager compaction pass don't need to be independent.
This saves some memory.

In the future we should allow passes to fetch passes by name, that will
be part of the PassManager improvement in the future
2020-12-03 19:58:47 -08:00
Ryan Houdek d3201ff498 Merge pull request #546 from FEX-Emu/skmp/sfbe-sext-switcheroo
IR: Replace Sext with Sbfe
2020-12-03 15:03:19 -08:00
Stefanos Kornilios Mitsis Poiitidis 0024b7bd46 RA: Fix global value range expansion 2020-12-03 20:19:00 +02:00
Stefanos Kornilios Mitsis Poiitidis b2d862a8c7 IR: Replace Sext with Sbfe 2020-12-03 20:08:08 +02:00
Stefanos Kornilios Mitsis Poiitidis 2e314400bc ConstProp: FCMP Optimization
Removes unused flags from OP_FCMPs
2020-12-03 19:34:57 +02:00
Stefanos Kornilios Mitsis Poiitidis c802b82450 CMT: Move unary ops before selects, if both True & False values are consts 2020-12-03 19:11:25 +02:00
Stefanos Kornilios Mitsis Poiitidis 46fb0503f0 ConstProp: Mul x,#powof2 -> Lshl x,clz(#powof2) 2020-12-03 19:06:14 +02:00