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079e70fc4e1a88eeb5d095eb20f358ad8364bb2e
Commit Graph
1899 Commits
Author SHA1 Message Date
Ryan Houdek b31e4a3c27 JIT: Moves Arm64 JIT up one folder 
We have only one JIT, there is no reason to subfolder this. Move it up
one folder.

NFC
 2024-10-25 18:44:20 -07:00
LC 992d6e8477 Merge pull request #4136 from Sonicadvance1/support_tpidrro 
FEXCore: Adds support for CPU Index through TPIDRRO
 2024-10-25 21:43:33 -04:00
LC f6cdb165a3 Merge pull request #4137 from Sonicadvance1/minor_pushf_opt 
OpcodeDispatcher: Minor optimization to small pushf
 2024-10-25 21:42:45 -04:00
Ryan Houdek f143462ebe OpcodeDispatcher: Minor optimization to small pushf 
The push operation already truncates the result, there's no need to bfe
it. Noticed this while cleaning up in #4134. Removes one instruction for
16-bit and 32-bit pushf instructions.
 2024-10-25 15:41:22 -07:00
Ryan Houdek 048e967546 FEXCore: Adds support for CPU Index through TPIDRRO 2024-10-25 15:07:57 -07:00
Ryan Houdek 01a6e914f2 X86Tables: Removes XOP tables 
These weren't even wired up to the frontend. We aren't going to support
XOP, so just remove the tables.
 2024-10-25 14:32:13 -07:00
Paulo Matos 5f6c0d2245 X87 code simplification 
Merges some of the code from reduced precision into the main path
since they are practically the same.
 2024-10-24 18:15:49 +02:00
Ryan Houdek caaacb6c15 Merge pull request #4127 from alyssarosenzweig/opt/masking 
Optimize bsf, bsr, register cmpxchg, pcmpistri
 2024-10-23 07:28:29 -07:00
Alyssa Rosenzweig 58a3d174ec OpcodeDispatcher: explain why we provide defined bsf behaviour 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:36:24 -04:00
Alyssa Rosenzweig 9c605e7333 OpcodeDispatcher: optimize bsf/bsr 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:31:49 -04:00
Alyssa Rosenzweig 1fd7e88ffd OpcodeDispatcher: optimize cmp in cmpxchg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig c5e7da0631 OpcodeDispatcher: optimize more cmpxchg mask 
none of it matters.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 68f58e415f OpcodeDispatcher: optimize cmpxchg masking 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 698abec25c JIT: drop FindMSB zero handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 1578f5ed47 JIT: drop FindLSB masking 
consequence of the UB

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig 80d7b5a5c9 JIT: drop FindLSB zero handling 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Alyssa Rosenzweig eb023ceb51 IR: make FindLSB/FindMSB undefined for zero 
these are used in places:

* bsf/bsr
* pcmpblabla
* x87 fild

In all cases we explicitly check for zero and change the behaviour accordingly.
So weaken the IR op to let us optimize. No sense checking twice.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-22 13:29:47 -04:00
Ryan Houdek fafc04a59e OpcodeDispatcher/AVX128: Fixes glibc allocation 2024-10-21 09:34:59 -07:00
Ryan Houdek fe8f5c745d OpcodeDispatcher/AVX128: Use unified PSHUF{L,H}W implementation 
Allows the AVX128 implementation to use the same implementation as the
128-bit SSE implementation, because it works per 128-bit lane just like
SSE. Is a minor optimization.
 2024-10-21 09:24:38 -07:00
Ryan Houdek d876224358 OpcodeDispatcher: Unify MMX and SSE PSHUF{L,H}W implementations 
No functional change.
 2024-10-21 09:11:05 -07:00
Ryan Houdek d7afcee622 AVX128: Fixes asome AVX bugs 
vblendvps, vblendvpd, vpblendvb all broke because of failing to zext the
128-bit register correctly.

vinsertps broke because it was accidentally using the wrong
implementation.

Extends each of their unittests to handle these cases.
 2024-10-18 15:49:25 -07:00
Paulo Matos 10ec6b63b6 Fix FXTRACT for 0.0 and -0.0 
Fixes fxtract by returning the correct values for 0.0 and -0.0. We moved the split of fxtract into _sig and _exp, to the opcode dispatcher, to ease some comparisons.

Also removed the IR node F80XTRACTStack which is not needed anymore.
 2024-10-17 09:05:10 +02:00
Paulo Matos 49087007be Implement NZCVSelectV for selection on FPRs 
Behaves like NZCVSelect for FPRs.
 2024-10-17 08:42:50 +02:00
Ryan Houdek 4b945a9041 Merge pull request #4105 from pmatos/X87MMXState 
Implement explicit state switch between X87 and MMX
 2024-10-16 15:52:27 -07:00
Paulo Matos 0d53f2b45c Implements explicit state switch between X87 and MMX 
Fixes #3850
 2024-10-15 17:58:53 +02:00
Ryan Houdek e53f3969e9 FEXCore: Change yield implementation to use wfe 
According to
https://github.com/rust-lang/rust/commit/c064b6560b7ce0adeb9bbf5d7dcf12b1acb0c807
turns out that the arm yield instruction is effectively a nop on all
reasonably new CPUs.
Instead switch over to wfe because it matches x86 `PAUSE` semantics more
closely.
 2024-10-15 05:50:26 -07:00
LC 389ad737e6 Merge pull request #4103 from Sonicadvance1/shared_vdso_mmap 
VDSOEmulation: Support loading VDSO thunk as shared
 2024-10-10 01:25:12 -04:00
Ryan Houdek e82d2c70c3 Merge pull request #4095 from alyssarosenzweig/opt/jit-time 
speed up the JIT
 2024-10-04 09:00:03 -07:00
Ryan Houdek c740801ea5 VDSOEmulation: Support loading VDSO thunk as shared 
Just requires a thread pointer check to be fixed in FEXCore.
This doesn't need unique pages to exist for the file mapping and can be
shared since it's readonly mapped.
 2024-10-03 21:06:35 -07:00
Ryan Houdek 7dda75646d OpcodeDispatcher: Fixes segment prefixing on vector element loadstores 
These had completely forgotten to load segment prefixes on the element
loadstore operations. This had caused a crash on the Linux version of
"Halls of Tormet" (steamid 2218750).

This game has TLS vector data which it was loading with a movhps and hit
this path.
 2024-10-03 20:51:37 -07:00
Alyssa Rosenzweig 44484a7b05 ConstProp: drop non-loadbearing opts 
every pattern costs us JIT time, but not every pattern is doing anything.
especially with the flag rework of 2023-2024, a lot of patterns just don't make
sense anymore. constant folding in particular isn't too useful now.

only instcountci change is AAD which i'm contractually forbidden from caring
about.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 14:01:32 -04:00
Alyssa Rosenzweig 6ac7ba388f ConstProp: rm leftover 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 36d0a67070 ConstProp: don't pool with a hash table 
hash tables have high overhead! but individual blocks are small, so the
quadratic search is _much_ faster in practice. knocks 8% off node.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 0650dd1992 ConstProp: defer initialization 
for blocks that don't need pooling. hopefully that's most of them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig e2d58809ed OpcodeDispatcher: rm dead 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 967a74cda9 OpcodeDispatcher: manually inline constants 
less work for constprop.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 6cc6181261 OpcodeDispatcher/Flags: dont emit zero 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig f175b525f4 OpcodeDispatcher/Flags: inline constants 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 319f1e66cb RegisterAllocationPass: eliminate a silly sxtb 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig d16969bdce RegisterAllocationPass: simplify 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig c17858bfeb RegisterAllocationPass: don't lookup sources 
lot of silly chasing. not needed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig ec24fc3d5d RegisterAllocationPass: infer AnyRemapped 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 8819fa88d5 RegisterAllocationPass: avoid allocating remaps 
shaves 6ms off.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 13:38:48 -04:00
Alyssa Rosenzweig 5aaa18e7a2 RegisterAllocationPass: remove Class->Allocated 
not needed anymore.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 12:41:37 -04:00
Alyssa Rosenzweig 8a551b9e64 RegisterAllocationPass: rm leftover comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 12:41:37 -04:00
Alyssa Rosenzweig aa548bd19c RegisterAllocationPass: track if we need a remap 
should be faster on average.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 12:41:37 -04:00
Alyssa Rosenzweig 9565f16d84 RegisterAllocationPass: simplify 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-10-02 12:41:37 -04:00
Paulo Matos eb76dbdf4d x87 small cleanups; NFC 2024-10-02 18:27:51 +02:00
Ryan Houdek 0b8b5108b9 Thunks: Moves AppendThunkDefinitions function to the frontend 
Backend doesn't need access to this at all
 2024-09-27 15:48:31 -07:00
Ryan Houdek 24211f8523 FEXCore: Move ThunksHandler class to FEXLoader 
With as little changes as possible, because this is fairly tricky.
 2024-09-27 15:48:31 -07:00