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009ae55ff090596bdb1c9ae12848d871321b6e44
Commit Graph
276 Commits
Author SHA1 Message Date
Ryan Houdek 009ae55ff0 Merge pull request #3475 from alyssarosenzweig/opt/lock-dec 
Optimize lock dec
 2024-02-29 08:44:24 -08:00
Alyssa Rosenzweig fed5e6d546 OpcodeDispatcher: use fetchadd for atomic DEC 
Avoids a NEG.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-29 09:28:21 -04:00
Alyssa Rosenzweig 811487ad98 OpcodeDispatcher: use real branch for INT 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 10:35:12 -04:00
Alyssa Rosenzweig 4f4e38ace2 OpcodeDispatcher: use real branch for rep cmps 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 10:35:12 -04:00
Alyssa Rosenzweig edd6becc56 OpcodeDispatcher: use real branch for rep scas 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 10:35:12 -04:00
Alyssa Rosenzweig e47a94cae7 OpcodeDispatcher: skip mask with shld 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 10:18:29 -04:00
Alyssa Rosenzweig 8232669b22 OpcodeDispatcher: simplify 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 10:00:13 -04:00
Alyssa Rosenzweig 28936073c4 OpcodeDispatcher: allow upper garbage on NEG 
like SUB.

due to RA silliness, this is a loss for inst count but a win for cycles.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 09:59:57 -04:00
Alyssa Rosenzweig ef2559d911 OpcodeDispatcher: allow garbage with SCAS 
it's just feeding SUB flags which allow it

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-28 09:16:08 -04:00
Ryan Houdek f346f89678 OpcodeDispatcher: Don't use AddShift with no shift 
This accidentally removed optimizations elsewhere that was only checking
for Add.
 2024-02-27 19:56:12 -08:00
Alyssa Rosenzweig 49e798ab2b Merge pull request #3461 from alyssarosenzweig/opt/sbc 
Optimize SBC
 2024-02-27 11:29:45 -04:00
Ryan Houdek 946c805d84 Merge pull request #3459 from Sonicadvance1/fix_591 
Capture a 64-bit process trying to jump to 32-bit syscall handler
 2024-02-26 21:57:03 -08:00
Alyssa Rosenzweig 270cbf39b5 OpcodeDispatcher: specialize SALC 
this gets rid of the awkward non-flag SBB case, which streamlines SBB. while
getting better codegen for the demon opcode (-:

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 16:33:41 -04:00
Alyssa Rosenzweig 2e0be0a5e7 OpcodeDispatcher: allow more upper garbage with adc 
missed this last series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:42:13 -04:00
Alyssa Rosenzweig d60c089697 OpcodeDispatcher: allow upper garbage with sbb 
for the usual reasons

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:35:14 -04:00
Alyssa Rosenzweig e76ebeab58 OpcodeDispatcher: use 1-op "src + CF" 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:35:14 -04:00
Alyssa Rosenzweig 333271d490 OpcodeDispatcher: fuse sbb when flags calculated 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:35:14 -04:00
Alyssa Rosenzweig a750870abf OpcodeDispatcher: use fused sbcs calculations 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:25:03 -04:00
Ryan Houdek 4f028b8614 Capture a 64-bit process trying to jump to 32-bit syscall handler 
Fixes #591

Adds a simple unittest
 2024-02-26 05:37:29 -08:00
Alyssa Rosenzweig 1e153e0c81 OpcodeDispatcher: allow garbage with adcs 
for the usual reasons

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-25 10:50:02 -04:00
Alyssa Rosenzweig 6994fc3a01 IR,OpcodeDispatcher,JIT: fuse adcs flags 
The usual tricks, also requires introducing a bare adc op to optimize adcs to,
but we wanted that anyway!

Also support a zero source, so we can calculate "foo + CF" in one instruction to
optimize the "lock adc" cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-25 10:49:32 -04:00
Ryan Houdek d703f3ccee Fixes zero register flag generation 
Fixes 140976d322

Adds a unit test to ensure it keeps working.
 2024-02-24 16:32:25 -08:00
Alyssa Rosenzweig 852e3c4e93 OpcodeDispatcher: fuse XADD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig e86547bbcb OpcodeDispatcher: fuse INC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 883cca2e8f OpcodeDispatcher: use AddWithFlags 
give it the same treatment we just gave sub.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig df5bdefb8a OpcodeDispatcher: merge secondary ALU with primary ALU 
It's the same, stop copypasting. This gets our flag and arithmetic opts (current
and future) applied to secondary ALU too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 3d1fb7701c OpcodeDispatcher: optimize sub 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 140976d322 OpcodeDispatcher: prep primary ALU for better flags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 9a11d3b1a2 OpcodeDispatcher: fuse NEG 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 96e652879f OpcodeDispatcher: fuse DEC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig c1d572951f OpcodeDispatcher: drop unused GenerateFlags_SUB arg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 2bcd285851 Merge pull request #3430 from Sonicadvance1/tsc_scale 
Implement small TSC scaling
 2024-02-21 13:16:27 -04:00
Ryan Houdek b902b8edab Implement small TSC scaling 
Games engines are expecting >1Ghz cycle counters. Scale them to work
around the issue.

Resolves the excessive busy waiting in Unreal Engine 5 games.
 2024-02-20 12:05:44 -08:00
Alyssa Rosenzweig 0503c89ff6 OpcodeDispatcher: use NZCV update helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-19 14:12:54 -04:00
Alyssa Rosenzweig 68232366e4 OpcodeDispatcher: don't mask add/sub sources 
not needed in the new approach

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-12 12:36:28 -04:00
Ryan Houdek df3d6938ae Merge pull request #3410 from alyssarosenzweig/opt/nzcv-pass-2 
Add NZCV+PF/AF optimization pass
 2024-02-10 05:03:12 -08:00
Alyssa Rosenzweig ad7202e7d7 OpcodeDispatcher: optimize test -1 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-08 14:10:13 -04:00
Alyssa Rosenzweig 175a57dd27 OpcodeDispatcher: emit AndWithFlags directly for primary alu 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-06 14:22:28 -04:00
Alyssa Rosenzweig e2ce60148c OpcodeDispatcher: emit AndWithFlags directly for 2ndary alu 
rely on opt pass to drop the flags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-06 14:22:28 -04:00
Alyssa Rosenzweig 99660129f3 IR: implement AndWithFlags for 8/16-bit 
easier to deal with in the JIT

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-06 14:22:28 -04:00
Alyssa Rosenzweig 4331753ca0 Merge pull request #3408 from alyssarosenzweig/opt/tst 
Optimize TST
 2024-02-06 11:28:02 -04:00
Paulo Matos fa8bcfd67a Clean up access to possible nullptr 
Patch suggested by @Sonicadvance1
 2024-02-06 12:31:38 +00:00
Alyssa Rosenzweig 2e0cb2fbd4 OpcodeDispatcher: optimize TST 
it's just an AndWithFlags setting the PF.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-05 15:32:21 -04:00
Mai 6993f4fd8d Merge pull request #3400 from Sonicadvance1/revert_runtime_longmode_switch 
Revert #3303
 2024-02-02 11:53:44 -05:00
Paulo Matos 4623544f69 Improve XCHG operations 
Marking loads as allowing upper garbage simplifies some operations.
Update InstCountCI as well.
 2024-02-02 08:16:13 +00:00
Ryan Houdek da0e1b515a Revert "OpcodeDispatcher: Initial support for runtime long-mode switch" 
This reverts commit 9e5d7aa5fe.
 2024-02-01 18:14:24 -08:00
Ryan Houdek cec1814a09 Merge pull request #3384 from pmatos/CDQOp-Opt 
Optimize CDQOp
 2024-01-31 17:51:23 -08:00
Mai 4d49ac7c3d Merge pull request #3387 from alyssarosenzweig/opt/rotates 
Optimize rotates
 2024-01-31 18:20:40 -05:00
Alyssa Rosenzweig 6d13d9fb56 Merge pull request #3395 from pmatos/StaticAnalysis 
Code cleanup - mainly dead store removal; NFC
 2024-01-31 17:24:48 -04:00
Mai ae7dc250db Merge pull request #3386 from alyssarosenzweig/opt/shift 
Optimize shifts a bit
 2024-01-31 14:11:58 -05:00