From 11eaf3d48a1a9932a87327efa3c933eef6b76724 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 29 Sep 2022 20:50:19 -0700
Subject: [PATCH] Ensure Arm64Emitter uses FEX allocator

Otherwise we will end up allocating code buffers in the lower 32-bits,
consuming precious virtual address space.
---
 .../Interface/Core/ArchHelpers/Arm64Emitter.cpp       | 11 ++++++++++-
 .../Source/Interface/Core/ArchHelpers/Arm64Emitter.h  |  1 +
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
index 39b0de909..5ba2e5cfe 100644
--- a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
@@ -20,7 +20,9 @@ namespace FEXCore::CPU {
 
 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
 Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size)
-  : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode)
+  : vixl::aarch64::Assembler(size ? (byte*)FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0) : reinterpret_cast<byte*>(~0ULL),
+                             size,
+                             vixl::aarch64::PositionDependentCode)
   , EmitterCTX {ctx} {
   CPU.SetUp();
 
@@ -37,6 +39,13 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::Context *ctx, size_t size)
   SetCPUFeatures(Features);
 }
 
+Arm64Emitter::~Arm64Emitter() {
+  auto CodeBuffer = GetBuffer();
+  if (CodeBuffer->GetCapacity()) {
+    FEXCore::Allocator::munmap(CodeBuffer->GetStartAddress<void*>(), CodeBuffer->GetCapacity());
+  }
+}
+
 void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant, bool NOPPad) {
   bool Is64Bit = Reg.IsX();
   int Segments = Is64Bit ? 4 : 2;
diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
index 7b098de18..9dd139050 100644
--- a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
+++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
@@ -88,6 +88,7 @@ const std::array<aarch64::VRegister, 12> RAFPR = {
 class Arm64Emitter : public vixl::aarch64::Assembler {
 protected:
   Arm64Emitter(FEXCore::Context::Context *ctx, size_t size);
+  ~Arm64Emitter();
 
   FEXCore::Context::Context *EmitterCTX;
   vixl::aarch64::CPU CPU;