diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index 50745f04e..a715aa82b 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -39,7 +39,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { "ExpectedInstructionCount": 87, "Comment": [ - "Bit mask (8-bit)", + "Equal Any, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -135,7 +135,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_00_01b": { "ExpectedInstructionCount": 64, "Comment": [ - "Bit mask (16-bit)", + "Equal Any, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -205,10 +205,10 @@ "msr nzcv, x20" ] }, - "pcmpestrm xmm0, xmm1, 0_1_00_00_00b": { - "ExpectedInstructionCount": 83, + "pcmpestrm xmm0, xmm1, 0_0_00_00_10b": { + "ExpectedInstructionCount": 87, "Comment": [ - "Expanded mask (8-bit)", + "Equal Any, Positive polarity, Signed bytes, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -282,25 +282,29 @@ "orr v4.16b, v4.16b, v5.16b", "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", - "and v16.16b, v3.16b, v2.16b", - "umaxv b2, v16.16b", - "umov w22, v2.b[0]", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", "cmp w22, #0x0 (0)", - "cset x22, eq", - "umov w23, v16.b[0]", + "cset x23, eq", "mov w26, #0x1", - "and x23, x23, #0x1", - "lsl x23, x23, #28", - "orr x22, x23, x22, lsl #29", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", "orr x21, x22, x21, lsl #30", "orr x20, x21, x20, lsl #31", "msr nzcv, x20" ] }, - "pcmpestrm xmm0, xmm1, 0_1_00_00_01b": { - "ExpectedInstructionCount": 59, + "pcmpestrm xmm0, xmm1, 0_0_00_00_11b": { + "ExpectedInstructionCount": 64, "Comment": [ - "Expanded mask (16-bit)", + "Equal Any, Positive polarity, Signed words, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -350,16 +354,21 @@ "orr v4.16b, v4.16b, v5.16b", "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", - "and v16.16b, v3.16b, v2.16b", - "umaxv h2, v16.8h", - "umov w22, v2.h[0]", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", "cmp w22, #0x0 (0)", - "cset x22, eq", - "umov w23, v16.h[0]", + "cset x23, eq", "mov w26, #0x1", - "and x23, x23, #0x1", - "lsl x23, x23, #28", - "orr x22, x23, x22, lsl #29", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", "orr x21, x22, x21, lsl #30", "orr x20, x21, x20, lsl #31", "msr nzcv, x20" @@ -368,7 +377,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_01_00b": { "ExpectedInstructionCount": 99, "Comment": [ - "Ranges (8-bit)", + "Ranges, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -476,7 +485,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_01_01b": { "ExpectedInstructionCount": 68, "Comment": [ - "Ranges (16-bit)", + "Ranges, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -550,10 +559,195 @@ "msr nzcv, x20" ] }, + "pcmpestrm xmm0, xmm1, 0_0_00_01_10b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_00_01_11b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, "pcmpestrm xmm0, xmm1, 0_0_00_10_00b": { "ExpectedInstructionCount": 40, "Comment": [ - "Equal each (8-bit)", + "Equal Each, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -602,7 +796,106 @@ "pcmpestrm xmm0, xmm1, 0_0_00_10_01b": { "ExpectedInstructionCount": 41, "Comment": [ - "Equal each (16-bit)", + "Equal Each, Positive polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_00_10_10b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_00_10_11b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive polarity, Signed words, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -652,7 +945,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_11_00b": { "ExpectedInstructionCount": 136, "Comment": [ - "Equal ordered (8-bit)", + "Equal Ordered, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -797,7 +1090,7 @@ "pcmpestrm xmm0, xmm1, 0_0_00_11_01b": { "ExpectedInstructionCount": 89, "Comment": [ - "Equal ordered (16-bit)", + "Equal Ordered, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ @@ -892,10 +1185,9789 @@ "msr nzcv, x20" ] }, + "pcmpestrm xmm0, xmm1, 0_0_00_11_10b": { + "ExpectedInstructionCount": 136, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_00_11_11b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_00_00b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_00_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_00_10b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_00_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_01_00b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_01_01b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_01_10b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_01_11b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_10_00b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_10_01b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_10_10b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_10_11b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_11_00b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_11_01b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_11_10b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_01_11_11b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_00_00b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_00_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_00_10b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_00_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_01_00b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_01_01b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_01_10b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_01_11b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_10_00b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_10_01b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_10_10b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_10_11b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_11_00b": { + "ExpectedInstructionCount": 136, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_11_01b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_11_10b": { + "ExpectedInstructionCount": 136, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_10_11_11b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_00_00b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_00_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_00_10b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_00_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_01_00b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_01_01b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_01_10b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_01_11b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_10_00b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_10_01b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_10_10b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_10_11b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_11_00b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_11_01b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_11_10b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_0_11_11_11b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_00_00b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_00_01b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_00_10b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_00_11b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_01_00b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_01_01b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_01_10b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_01_11b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_10_00b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_10_01b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_10_10b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_10_11b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_11_00b": { + "ExpectedInstructionCount": 132, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_11_01b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_11_10b": { + "ExpectedInstructionCount": 132, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_00_11_11b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_00_00b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_00_01b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_01_00b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_01_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_10_00b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_10_01b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_11_00b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_11_01b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_11_10b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_01_11_11b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_00_00b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_00_01b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_00_10b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_00_11b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_01_00b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_01_01b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_01_10b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_01_11b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_10_00b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_10_01b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_10_10b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_10_11b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_11_00b": { + "ExpectedInstructionCount": 132, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_11_01b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_11_10b": { + "ExpectedInstructionCount": 132, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_10_11_11b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_00_00b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_00_01b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_01_00b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_01_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_10_00b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_10_01b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_11_00b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_11_01b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_11_10b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestrm xmm0, xmm1, 0_1_11_11_11b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x60" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, "pcmpestri xmm0, xmm1, 0_0_00_00_00b": { "ExpectedInstructionCount": 85, "Comment": [ - "8-bit", + "Equal Any, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -989,7 +11061,171 @@ "pcmpestri xmm0, xmm1, 0_0_00_00_01b": { "ExpectedInstructionCount": 61, "Comment": [ - "16-bit", + "Equal Any, Positive polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_00_10b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_00_11b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Positive polarity, Signed words, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1059,7 +11295,7 @@ "pcmpestri xmm0, xmm1, 0_0_00_01_00b": { "ExpectedInstructionCount": 97, "Comment": [ - "Ranges (8-bit)", + "Ranges, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1165,7 +11401,7 @@ "pcmpestri xmm0, xmm1, 0_0_00_01_01b": { "ExpectedInstructionCount": 65, "Comment": [ - "Ranges (16-bit)", + "Ranges, Positive polarity, Unsigned words, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1236,10 +11472,190 @@ "msr nzcv, x20" ] }, + "pcmpestri xmm0, xmm1, 0_0_00_01_10b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_01_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Positive polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, "pcmpestri xmm0, xmm1, 0_0_00_10_00b": { "ExpectedInstructionCount": 38, "Comment": [ - "Equal each (8-bit)", + "Equal Each, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1286,7 +11702,101 @@ "pcmpestri xmm0, xmm1, 0_0_00_10_01b": { "ExpectedInstructionCount": 38, "Comment": [ - "Equal each (16-bit)", + "Equal Each, Positive polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_10_10b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_10_11b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive polarity, Signed words, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1333,7 +11843,7 @@ "pcmpestri xmm0, xmm1, 0_0_00_11_00b": { "ExpectedInstructionCount": 134, "Comment": [ - "Equal ordered (8-bit)", + "Equal Ordered, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1476,7 +11986,7 @@ "pcmpestri xmm0, xmm1, 0_0_00_11_01b": { "ExpectedInstructionCount": 86, "Comment": [ - "Equal ordered (16-bit)", + "Equal Ordered, Positive polarity, Unsigned words, LSB index", "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ @@ -1568,10 +12078,10112 @@ "msr nzcv, x20" ] }, + "pcmpestri xmm0, xmm1, 0_0_00_11_10b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_00_11_11b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_00_00b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_00_01b": { + "ExpectedInstructionCount": 62, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_00_10b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_00_11b": { + "ExpectedInstructionCount": 62, + "Comment": [ + "Equal Any, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_01_00b": { + "ExpectedInstructionCount": 98, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_01_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_01_10b": { + "ExpectedInstructionCount": 98, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_01_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Ranges, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_10_00b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_10_01b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_10_10b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_10_11b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_11_00b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_11_01b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_11_10b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_01_11_11b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_00_00b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_00_01b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_00_10b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_00_11b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_01_00b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_01_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_01_10b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_01_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_10_00b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_10_01b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_10_10b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_10_11b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_11_00b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_11_01b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_11_10b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_10_11_11b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_00_00b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_00_01b": { + "ExpectedInstructionCount": 62, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_00_10b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_00_11b": { + "ExpectedInstructionCount": 62, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_01_00b": { + "ExpectedInstructionCount": 98, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_01_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_01_10b": { + "ExpectedInstructionCount": 98, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_01_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_10_00b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_10_01b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_10_10b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w21, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w21", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_10_11b": { + "ExpectedInstructionCount": 39, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w21, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w21", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_11_00b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_11_01b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_11_10b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_0_11_11_11b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_00_00b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_00_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_00_10b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_00_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_01_00b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_01_01b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_01_10b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_01_11b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_10_00b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_10_01b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_10_10b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_10_11b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_11_00b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_11_01b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_11_10b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_00_11_11b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_00_00b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_00_01b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_00_10b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_00_11b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_01_00b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_01_01b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_01_10b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_01_11b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_10_00b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_10_01b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_10_10b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_10_11b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_11_00b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_11_01b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_11_10b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_01_11_11b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "mvn v3.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_00_00b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_00_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_00_10b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_00_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_01_00b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_01_01b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_01_10b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_01_11b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_10_00b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_10_01b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_10_10b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_10_11b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v4.16b, v5.16b, v6.16b", + "orn v3.16b, v4.16b, v3.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_11_00b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_11_01b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_11_10b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.16b, w20", + "cmgt v4.16b, v4.16b, v2.16b", + "and v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_10_11_11b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v4.8h, w20", + "cmgt v4.8h, v4.8h, v2.8h", + "and v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_00_00b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_00_01b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_00_10b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v7.16b, v6.b[1]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[2]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[3]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[4]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[5]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[6]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[7]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[8]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[9]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[10]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[11]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[12]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[13]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.16b, v6.b[14]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.16b, v6.b[15]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_00_11b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "mov v6.16b, v3.16b", + "bsl v6.16b, v16.16b, v5.16b", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v7.8h, v6.h[1]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[2]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[3]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[4]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[5]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v7.8h, v6.h[6]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v5.16b, v5.16b, v7.16b", + "dup v6.8h, v6.h[7]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_01_00b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_01_01b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_01_10b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "dup v6.16b, v16.b[1]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.16b, v16.b[2]", + "dup v7.16b, v16.b[3]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "dup v7.16b, v16.b[5]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "dup v7.16b, v16.b[7]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[7]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "dup v7.16b, v16.b[9]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[9]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "dup v7.16b, v16.b[11]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[11]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "dup v7.16b, v16.b[13]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[13]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "dup v7.16b, v16.b[15]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_01_11b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "dup v6.8h, v16.h[1]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[1]", + "bic v5.16b, v6.16b, v5.16b", + "dup v6.8h, v16.h[2]", + "dup v7.8h, v16.h[3]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[3]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "dup v7.8h, v16.h[5]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[5]", + "bic v6.16b, v7.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "dup v7.8h, v16.h[7]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v6.16b", + "orr v3.16b, v5.16b, v3.16b", + "and v3.16b, v3.16b, v4.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_10_00b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_10_01b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_10_10b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w22, #0x10 (16)", + "cset x22, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "cmeq v5.16b, v16.16b, v17.16b", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_10_11b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w22, #0x8 (8)", + "cset x22, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "cmeq v5.8h, v16.8h, v17.8h", + "and v6.16b, v3.16b, v4.16b", + "orr v3.16b, v3.16b, v4.16b", + "and v5.16b, v5.16b, v6.16b", + "orn v3.16b, v5.16b, v3.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x21, x30, #28", + "orr x21, x21, x24, lsl #29", + "orr x21, x21, x22, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_11_00b": { + "ExpectedInstructionCount": 142, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_11_01b": { + "ExpectedInstructionCount": 94, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_11_10b": { + "ExpectedInstructionCount": 142, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x10", + "cmp w20, #0x10 (16)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x10 (16)", + "csel w22, w22, w21, lo", + "dup v3.16b, w20", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, w22", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w22, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x10 (16)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.16b, #0x10", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpestri xmm0, xmm1, 0_1_11_11_11b": { + "ExpectedInstructionCount": 94, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x61" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "cneg w20, w4, mi", + "mov w21, #0x8", + "cmp w20, #0x8 (8)", + "csel w20, w20, w21, lo", + "cmp w5, #0x0 (0)", + "cneg w22, w5, mi", + "cmp w22, #0x8 (8)", + "csel w22, w22, w21, lo", + "dup v3.8h, w20", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, w22", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w22, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w22, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w22, #0x8 (8)", + "csel w22, w30, w21, lo", + "cmp w20, #0x0 (0)", + "csel w20, w21, w22, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v4.16b", + "movi v4.8h, #0x8", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x22, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w21, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x22, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, "pcmpistrm xmm0, xmm1, 0_0_00_00_00b": { "ExpectedInstructionCount": 87, "Comment": [ - "Bit mask (8-bit)", + "Equal Any, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -1667,7 +22279,7 @@ "pcmpistrm xmm0, xmm1, 0_0_00_00_01b": { "ExpectedInstructionCount": 64, "Comment": [ - "Bit mask (16-bit)", + "Equal Any, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -1737,10 +22349,10 @@ "msr nzcv, x20" ] }, - "pcmpistrm xmm0, xmm1, 0_1_00_00_00b": { - "ExpectedInstructionCount": 83, + "pcmpistrm xmm0, xmm1, 0_0_00_00_10b": { + "ExpectedInstructionCount": 87, "Comment": [ - "Expanded mask (8-bit)", + "Equal Any, Positive polarity, Signed bytes, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -1813,26 +22425,30 @@ "orr v4.16b, v4.16b, v5.16b", "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", - "and v16.16b, v3.16b, v2.16b", - "umaxv b2, v16.16b", - "umov w22, v2.b[0]", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", "mov w27, #0x0", "cmp w22, #0x0 (0)", - "cset x22, eq", - "umov w23, v16.b[0]", + "cset x23, eq", "mov w26, #0x1", - "and x23, x23, #0x1", - "lsl x23, x23, #28", - "orr x22, x23, x22, lsl #29", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", "orr x21, x22, x21, lsl #30", "orr x20, x21, x20, lsl #31", "msr nzcv, x20" ] }, - "pcmpistrm xmm0, xmm1, 0_1_00_00_01b": { - "ExpectedInstructionCount": 59, + "pcmpistrm xmm0, xmm1, 0_0_00_00_11b": { + "ExpectedInstructionCount": 64, "Comment": [ - "Expanded mask (16-bit)", + "Equal Any, Positive polarity, Signed words, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -1881,17 +22497,22 @@ "orr v4.16b, v4.16b, v5.16b", "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", - "and v16.16b, v3.16b, v2.16b", - "umaxv h2, v16.8h", - "umov w22, v2.h[0]", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", "mov w27, #0x0", "cmp w22, #0x0 (0)", - "cset x22, eq", - "umov w23, v16.h[0]", + "cset x23, eq", "mov w26, #0x1", - "and x23, x23, #0x1", - "lsl x23, x23, #28", - "orr x22, x23, x22, lsl #29", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", "orr x21, x22, x21, lsl #30", "orr x20, x21, x20, lsl #31", "msr nzcv, x20" @@ -1900,7 +22521,7 @@ "pcmpistrm xmm0, xmm1, 0_0_00_01_00b": { "ExpectedInstructionCount": 99, "Comment": [ - "Ranges (8-bit)", + "Ranges, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2008,7 +22629,7 @@ "pcmpistrm xmm0, xmm1, 0_0_00_01_01b": { "ExpectedInstructionCount": 68, "Comment": [ - "Ranges (16-bit)", + "Ranges, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2082,10 +22703,195 @@ "msr nzcv, x20" ] }, + "pcmpistrm xmm0, xmm1, 0_0_00_01_10b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_00_01_11b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, "pcmpistrm xmm0, xmm1, 0_0_00_10_00b": { "ExpectedInstructionCount": 40, "Comment": [ - "Equal each (8-bit)", + "Equal Each, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2134,7 +22940,106 @@ "pcmpistrm xmm0, xmm1, 0_0_00_10_01b": { "ExpectedInstructionCount": 41, "Comment": [ - "Equal each (16-bit)", + "Equal Each, Positive polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_00_10_10b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_00_10_11b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive polarity, Signed words, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2184,7 +23089,7 @@ "pcmpistrm xmm0, xmm1, 0_0_00_11_00b": { "ExpectedInstructionCount": 137, "Comment": [ - "Equal ordered (8-bit)", + "Equal Ordered, Positive polarity, Unsigned bytes, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2330,7 +23235,7 @@ "pcmpistrm xmm0, xmm1, 0_0_00_11_01b": { "ExpectedInstructionCount": 90, "Comment": [ - "Equal ordered (16-bit)", + "Equal Ordered, Positive polarity, Unsigned words, Bit mask", "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ @@ -2426,10 +23331,9819 @@ "msr nzcv, x20" ] }, + "pcmpistrm xmm0, xmm1, 0_0_00_11_10b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_00_11_11b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_00_00b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_00_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_00_10b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_00_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_01_00b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_01_01b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_01_10b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_01_11b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_10_00b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_10_01b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_10_10b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_10_11b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_11_00b": { + "ExpectedInstructionCount": 138, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_11_01b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_11_10b": { + "ExpectedInstructionCount": 138, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_01_11_11b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v2.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_00_00b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_00_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_00_10b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_00_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_01_00b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_01_01b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_01_10b": { + "ExpectedInstructionCount": 99, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_01_11b": { + "ExpectedInstructionCount": 68, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_10_00b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_10_01b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_10_10b": { + "ExpectedInstructionCount": 40, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_10_11b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_11_00b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_11_01b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_11_10b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_10_11_11b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_00_00b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_00_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_00_10b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_00_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_01_00b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_01_01b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_01_10b": { + "ExpectedInstructionCount": 100, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_01_11b": { + "ExpectedInstructionCount": 69, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_10_00b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_10_01b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_10_10b": { + "ExpectedInstructionCount": 41, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_10_11b": { + "ExpectedInstructionCount": 42, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v2.16b, v3.16b, v2.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w22, v16.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x23, eq", + "mov w26, #0x1", + "and x22, x22, #0x1", + "lsl x22, x22, #28", + "orr x22, x22, x23, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_11_00b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_11_01b": { + "ExpectedInstructionCount": 93, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_11_10b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.h[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_0_11_11_11b": { + "ExpectedInstructionCount": 93, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, Bit mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v2.16b, v2.16b, v4.16b", + "ldr q3, [x28, #3440]", + "movi v4.2d, #0x0", + "uzp1 v2.16b, v2.16b, v4.16b", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v2.16b, v2.16b, v4.16b", + "addp v16.16b, v2.16b, v4.16b", + "umov w20, v16.b[0]", + "cmp w20, #0x0 (0)", + "cset x21, eq", + "and x20, x20, #0x1", + "lsl x20, x20, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_00_00b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_00_01b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_00_10b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_00_11b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_01_00b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_01_01b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_01_10b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_01_11b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_10_00b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_10_01b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_10_10b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_10_11b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_11_00b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_11_01b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_11_10b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_00_11_11b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_00_00b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_00_01b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_01_00b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_01_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_10_00b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_10_01b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_11_00b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_11_01b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_11_10b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_01_11_11b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "mvn v16.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_00_00b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_00_01b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_00_10b": { + "ExpectedInstructionCount": 83, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_00_11b": { + "ExpectedInstructionCount": 59, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_01_00b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_01_01b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_01_10b": { + "ExpectedInstructionCount": 95, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_01_11b": { + "ExpectedInstructionCount": 63, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_10_00b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_10_01b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_10_10b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_10_11b": { + "ExpectedInstructionCount": 36, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v2.16b, v3.16b, v2.16b", + "and v3.16b, v4.16b, v5.16b", + "orn v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_11_00b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_11_01b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_11_10b": { + "ExpectedInstructionCount": 133, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v4.16b, v16.b[0]", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v5.16b, v3.b[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[1]", + "ext v6.16b, v17.16b, v5.16b, #1", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[2]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[3]", + "ext v6.16b, v17.16b, v5.16b, #3", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[5]", + "ext v6.16b, v17.16b, v5.16b, #5", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[7]", + "ext v6.16b, v17.16b, v5.16b, #7", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[7]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[8]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[9]", + "ext v6.16b, v17.16b, v5.16b, #9", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[9]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[10]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[11]", + "ext v6.16b, v17.16b, v5.16b, #11", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[11]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[12]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[13]", + "ext v6.16b, v17.16b, v5.16b, #13", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[13]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v6.16b, v3.b[14]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[15]", + "ext v6.16b, v17.16b, v5.16b, #15", + "cmeq v5.16b, v6.16b, v5.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.16b, w20", + "cmgt v2.16b, v4.16b, v2.16b", + "and v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_10_11_11b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v4.8h, v16.h[0]", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v5.8h, v3.h[0]", + "orn v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[1]", + "ext v6.16b, v17.16b, v5.16b, #2", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[1]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[2]", + "ext v6.16b, v17.16b, v5.16b, #4", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[2]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[3]", + "ext v6.16b, v17.16b, v5.16b, #6", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[3]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "ext v6.16b, v17.16b, v5.16b, #8", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[4]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[5]", + "ext v6.16b, v17.16b, v5.16b, #10", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[5]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "ext v6.16b, v17.16b, v5.16b, #12", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v6.8h, v3.h[6]", + "orn v5.16b, v5.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[7]", + "ext v6.16b, v17.16b, v5.16b, #14", + "cmeq v5.8h, v6.8h, v5.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v5.16b, v3.16b", + "and v3.16b, v4.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v4.8h, w20", + "cmgt v2.8h, v4.8h, v2.8h", + "and v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_00_00b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_00_01b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.16b, v17.16b, v4.16b", + "dup v6.16b, v5.b[1]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[2]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[3]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[4]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[5]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[6]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[7]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[8]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[9]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[10]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[11]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[12]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[13]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.16b, v5.b[14]", + "cmeq v6.16b, v17.16b, v6.16b", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.16b, v5.b[15]", + "cmeq v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "mov v5.16b, v3.16b", + "bsl v5.16b, v16.16b, v4.16b", + "cmeq v4.8h, v17.8h, v4.8h", + "dup v6.8h, v5.h[1]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[2]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[3]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[4]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[5]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v6.8h, v5.h[6]", + "cmeq v6.8h, v17.8h, v6.8h", + "orr v4.16b, v4.16b, v6.16b", + "dup v5.8h, v5.h[7]", + "cmeq v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_01_00b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmhi v4.16b, v4.16b, v17.16b", + "cmhi v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmhi v5.16b, v5.16b, v17.16b", + "cmhi v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_01_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmhi v4.8h, v4.8h, v17.8h", + "cmhi v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmhi v5.8h, v5.8h, v17.8h", + "cmhi v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "dup v4.16b, v16.b[0]", + "dup v5.16b, v16.b[1]", + "cmgt v4.16b, v4.16b, v17.16b", + "cmgt v5.16b, v17.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v3.b[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.16b, v16.b[2]", + "dup v6.16b, v16.b[3]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[4]", + "dup v6.16b, v16.b[5]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[6]", + "dup v6.16b, v16.b[7]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[7]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[8]", + "dup v6.16b, v16.b[9]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[9]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[10]", + "dup v6.16b, v16.b[11]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[11]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[12]", + "dup v6.16b, v16.b[13]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.16b, v3.b[13]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.16b, v16.b[14]", + "dup v6.16b, v16.b[15]", + "cmgt v5.16b, v5.16b, v17.16b", + "cmgt v6.16b, v17.16b, v6.16b", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "dup v4.8h, v16.h[0]", + "dup v5.8h, v16.h[1]", + "cmgt v4.8h, v4.8h, v17.8h", + "cmgt v5.8h, v17.8h, v5.8h", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v3.h[1]", + "bic v4.16b, v5.16b, v4.16b", + "dup v5.8h, v16.h[2]", + "dup v6.8h, v16.h[3]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[3]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[4]", + "dup v6.8h, v16.h[5]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v6.8h, v3.h[5]", + "bic v5.16b, v6.16b, v5.16b", + "orr v4.16b, v4.16b, v5.16b", + "dup v5.8h, v16.h[6]", + "dup v6.8h, v16.h[7]", + "cmgt v5.8h, v5.8h, v17.8h", + "cmgt v6.8h, v17.8h, v6.8h", + "orr v5.16b, v5.16b, v6.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v5.16b", + "orr v3.16b, v4.16b, v3.16b", + "and v3.16b, v3.16b, v2.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_10_00b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_10_01b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v2.16b, v4.16b, v2.16b", + "cmeq v4.16b, v16.16b, v17.16b", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv b2, v16.16b", + "umov w22, v2.b[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.b[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v2.8h, v4.8h, v2.8h", + "cmeq v4.8h, v16.8h, v17.8h", + "and v5.16b, v3.16b, v2.16b", + "orr v3.16b, v3.16b, v2.16b", + "and v4.16b, v4.16b, v5.16b", + "orn v3.16b, v4.16b, v3.16b", + "eor v16.16b, v3.16b, v2.16b", + "umaxv h2, v16.8h", + "umov w22, v2.h[0]", + "mov w27, #0x0", + "cmp w22, #0x0 (0)", + "cset x22, eq", + "umov w23, v16.h[0]", + "mov w26, #0x1", + "and x23, x23, #0x1", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_11_00b": { + "ExpectedInstructionCount": 136, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_11_01b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_11_10b": { + "ExpectedInstructionCount": 136, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, Byte mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b4, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v4.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v4.16b, v4.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v4.16b, v4.16b, v2.16b", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v2.16b, v5.16b, v2.16b", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv b2, v16.16b", + "umov w20, v2.b[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.b[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistrm xmm0, xmm1, 0_1_11_11_11b": { + "ExpectedInstructionCount": 88, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, Word mask", + "0x66 0x0f 0x3A 0x62" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h4, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v4.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v4.8h, v4.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v4.8h, v4.8h, v2.8h", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v2.8h, v5.8h, v2.8h", + "and v2.16b, v3.16b, v2.16b", + "eor v16.16b, v2.16b, v4.16b", + "umaxv h2, v16.8h", + "umov w20, v2.h[0]", + "cmp w20, #0x0 (0)", + "cset x20, eq", + "umov w21, v16.h[0]", + "and x21, x21, #0x1", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, "pcmpistri xmm0, xmm1, 0_0_00_00_00b": { "ExpectedInstructionCount": 84, "Comment": [ - "8-bit", + "Equal Any, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2522,7 +33236,169 @@ "pcmpistri xmm0, xmm1, 0_0_00_00_01b": { "ExpectedInstructionCount": 60, "Comment": [ - "16-bit", + "Equal Any, Positive polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Positive polarity, Signed words, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2591,7 +33467,7 @@ "pcmpistri xmm0, xmm1, 0_0_00_01_00b": { "ExpectedInstructionCount": 96, "Comment": [ - "Ranges (8-bit)", + "Ranges, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2696,7 +33572,7 @@ "pcmpistri xmm0, xmm1, 0_0_00_01_01b": { "ExpectedInstructionCount": 64, "Comment": [ - "Ranges (16-bit)", + "Ranges, Positive polarity, Unsigned words, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2766,10 +33642,188 @@ "msr nzcv, x20" ] }, + "pcmpistri xmm0, xmm1, 0_0_00_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Positive polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, "pcmpistri xmm0, xmm1, 0_0_00_10_00b": { "ExpectedInstructionCount": 37, "Comment": [ - "Equal each (8-bit)", + "Equal Each, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2815,7 +33869,99 @@ "pcmpistri xmm0, xmm1, 0_0_00_10_01b": { "ExpectedInstructionCount": 37, "Comment": [ - "Equal each (16-bit)", + "Equal Each, Positive polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive polarity, Signed words, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -2861,7 +34007,7 @@ "pcmpistri xmm0, xmm1, 0_0_00_11_00b": { "ExpectedInstructionCount": 134, "Comment": [ - "Equal ordered (8-bit)", + "Equal Ordered, Positive polarity, Unsigned bytes, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -3004,7 +34150,7 @@ "pcmpistri xmm0, xmm1, 0_0_00_11_01b": { "ExpectedInstructionCount": 86, "Comment": [ - "Equal ordered (16-bit)", + "Equal Ordered, Positive polarity, Unsigned words, LSB index", "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ @@ -3095,6 +34241,10072 @@ "orr x20, x20, x23, lsl #31", "msr nzcv, x20" ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_11_10b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_00_11_11b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_00_00b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_00_01b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_00_10b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_00_11b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_01_00b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_01_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_01_10b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_01_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_10_00b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_10_01b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_10_10b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_10_11b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_11_00b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_11_01b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_11_10b": { + "ExpectedInstructionCount": 135, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_01_11_11b": { + "ExpectedInstructionCount": 87, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_00_00b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_00_01b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_00_10b": { + "ExpectedInstructionCount": 84, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_00_11b": { + "ExpectedInstructionCount": 60, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_01_00b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_01_01b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_01_10b": { + "ExpectedInstructionCount": 96, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_01_11b": { + "ExpectedInstructionCount": 64, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_10_00b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_10_01b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_10_10b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_10_11b": { + "ExpectedInstructionCount": 37, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_11_00b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_11_01b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_11_10b": { + "ExpectedInstructionCount": 134, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_10_11_11b": { + "ExpectedInstructionCount": 86, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_00_00b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_00_01b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_00_10b": { + "ExpectedInstructionCount": 85, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_00_11b": { + "ExpectedInstructionCount": 61, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_01_00b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_01_01b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_01_10b": { + "ExpectedInstructionCount": 97, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_01_11b": { + "ExpectedInstructionCount": 65, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_10_00b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_10_01b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_10_10b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_10_11b": { + "ExpectedInstructionCount": 38, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x22, eq", + "mov w27, #0x0", + "cmp w7, #0x0 (0)", + "cset x23, eq", + "lsl x23, x23, #28", + "orr x22, x23, x22, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_11_00b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v7.16b, v3.b[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[1]", + "ext v8.16b, v17.16b, v7.16b, #1", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[2]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[3]", + "ext v8.16b, v17.16b, v7.16b, #3", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[5]", + "ext v8.16b, v17.16b, v7.16b, #5", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[7]", + "ext v8.16b, v17.16b, v7.16b, #7", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[7]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[8]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[9]", + "ext v8.16b, v17.16b, v7.16b, #9", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[9]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[10]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[11]", + "ext v8.16b, v17.16b, v7.16b, #11", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[11]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[12]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[13]", + "ext v8.16b, v17.16b, v7.16b, #13", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[13]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[14]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[15]", + "ext v8.16b, v17.16b, v7.16b, #15", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.16b, w20", + "cmgt v6.16b, v6.16b, v2.16b", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_11_01b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v7.8h, v3.h[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[1]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[2]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[3]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[5]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[7]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.8h, w20", + "cmgt v6.8h, v6.8h, v2.8h", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_11_10b": { + "ExpectedInstructionCount": 137, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v7.16b, v3.b[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[1]", + "ext v8.16b, v17.16b, v7.16b, #1", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[2]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[3]", + "ext v8.16b, v17.16b, v7.16b, #3", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[5]", + "ext v8.16b, v17.16b, v7.16b, #5", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[7]", + "ext v8.16b, v17.16b, v7.16b, #7", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[7]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[8]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[9]", + "ext v8.16b, v17.16b, v7.16b, #9", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[9]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[10]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[11]", + "ext v8.16b, v17.16b, v7.16b, #11", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[11]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[12]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[13]", + "ext v8.16b, v17.16b, v7.16b, #13", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[13]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[14]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[15]", + "ext v8.16b, v17.16b, v7.16b, #15", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.16b, w20", + "cmgt v6.16b, v6.16b, v2.16b", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b2, v3.16b", + "umov w7, v2.b[0]", + "cmp w7, #0x10 (16)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_0_11_11_11b": { + "ExpectedInstructionCount": 89, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, LSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v7.8h, v3.h[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[1]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[2]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[3]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[5]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[7]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.8h, w20", + "cmgt v6.8h, v6.8h, v2.8h", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h2, v3.8h", + "umov w7, v2.h[0]", + "cmp w7, #0x8 (8)", + "cset x20, eq", + "cmp w7, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #28", + "orr x20, x21, x20, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_00_00b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_00_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_00_10b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_00_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_01_00b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_01_01b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_01_10b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_01_11b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_10_00b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_10_01b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_10_10b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_10_11b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_11_00b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_11_01b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_11_10b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_00_11_11b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_00_00b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_00_01b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_00_10b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_00_11b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_01_00b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_01_01b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_01_10b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_01_11b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_10_00b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_10_01b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_10_10b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_10_11b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_11_00b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_11_01b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_11_10b": { + "ExpectedInstructionCount": 140, + "Comment": [ + "Equal Ordered, Negative polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_01_11_11b": { + "ExpectedInstructionCount": 92, + "Comment": [ + "Equal Ordered, Negative polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "mvn v3.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_00_00b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_00_01b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_00_10b": { + "ExpectedInstructionCount": 90, + "Comment": [ + "Equal Any, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_00_11b": { + "ExpectedInstructionCount": 66, + "Comment": [ + "Equal Any, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_01_00b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_01_01b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_01_10b": { + "ExpectedInstructionCount": 102, + "Comment": [ + "Ranges, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_01_11b": { + "ExpectedInstructionCount": 70, + "Comment": [ + "Ranges, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_10_00b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_10_01b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_10_10b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_10_11b": { + "ExpectedInstructionCount": 43, + "Comment": [ + "Equal Each, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v5.16b, v6.16b, v7.16b", + "orn v3.16b, v5.16b, v3.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_11_00b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_11_01b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_11_10b": { + "ExpectedInstructionCount": 139, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "dup v5.16b, v16.b[0]", + "cmeq v5.16b, v17.16b, v5.16b", + "dup v6.16b, v3.b[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[1]", + "ext v7.16b, v17.16b, v6.16b, #1", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[2]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[3]", + "ext v7.16b, v17.16b, v6.16b, #3", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[4]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[5]", + "ext v7.16b, v17.16b, v6.16b, #5", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[6]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[7]", + "ext v7.16b, v17.16b, v6.16b, #7", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[7]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[8]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[8]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[9]", + "ext v7.16b, v17.16b, v6.16b, #9", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[9]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[10]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[10]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[11]", + "ext v7.16b, v17.16b, v6.16b, #11", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[11]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[12]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[12]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[13]", + "ext v7.16b, v17.16b, v6.16b, #13", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[13]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[14]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v7.16b, v3.b[14]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.16b, v16.b[15]", + "ext v7.16b, v17.16b, v6.16b, #15", + "cmeq v6.16b, v7.16b, v6.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.16b, w20", + "cmgt v5.16b, v5.16b, v2.16b", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_10_11_11b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Ordered, Positive masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "dup v5.8h, v16.h[0]", + "cmeq v5.8h, v17.8h, v5.8h", + "dup v6.8h, v3.h[0]", + "orn v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[1]", + "ext v7.16b, v17.16b, v6.16b, #2", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[1]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[2]", + "ext v7.16b, v17.16b, v6.16b, #4", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[2]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[3]", + "ext v7.16b, v17.16b, v6.16b, #6", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[3]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[4]", + "ext v7.16b, v17.16b, v6.16b, #8", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[4]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[5]", + "ext v7.16b, v17.16b, v6.16b, #10", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[5]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[6]", + "ext v7.16b, v17.16b, v6.16b, #12", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v7.8h, v3.h[6]", + "orn v6.16b, v6.16b, v7.16b", + "and v5.16b, v5.16b, v6.16b", + "dup v6.8h, v16.h[7]", + "ext v7.16b, v17.16b, v6.16b, #14", + "cmeq v6.8h, v7.8h, v6.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v6.16b, v3.16b", + "and v3.16b, v5.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v5.8h, w20", + "cmgt v5.8h, v5.8h, v2.8h", + "and v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_00_00b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_00_01b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_00_10b": { + "ExpectedInstructionCount": 91, + "Comment": [ + "Equal Any, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v8.16b, v7.b[1]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[2]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[3]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[4]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[5]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[6]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[7]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[8]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[9]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[10]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[11]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[12]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[13]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.16b, v7.b[14]", + "cmeq v8.16b, v17.16b, v8.16b", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.16b, v7.b[15]", + "cmeq v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.16b, v3.b[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_00_11b": { + "ExpectedInstructionCount": 67, + "Comment": [ + "Equal Any, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "mov v7.16b, v3.16b", + "bsl v7.16b, v16.16b, v6.16b", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v8.8h, v7.h[1]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[2]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[3]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[4]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[5]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v8.8h, v7.h[6]", + "cmeq v8.8h, v17.8h, v8.8h", + "orr v6.16b, v6.16b, v8.16b", + "dup v7.8h, v7.h[7]", + "cmeq v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v3.8h, v3.h[0]", + "and v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_01_00b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmhi v6.16b, v6.16b, v17.16b", + "cmhi v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmhi v7.16b, v7.16b, v17.16b", + "cmhi v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_01_01b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmhi v6.8h, v6.8h, v17.8h", + "cmhi v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmhi v7.8h, v7.8h, v17.8h", + "cmhi v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_01_10b": { + "ExpectedInstructionCount": 103, + "Comment": [ + "Ranges, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "dup v7.16b, v16.b[1]", + "cmgt v6.16b, v6.16b, v17.16b", + "cmgt v7.16b, v17.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v3.b[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.16b, v16.b[2]", + "dup v8.16b, v16.b[3]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "dup v8.16b, v16.b[5]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "dup v8.16b, v16.b[7]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[7]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "dup v8.16b, v16.b[9]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[9]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "dup v8.16b, v16.b[11]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[11]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "dup v8.16b, v16.b[13]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.16b, v3.b[13]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "dup v8.16b, v16.b[15]", + "cmgt v7.16b, v7.16b, v17.16b", + "cmgt v8.16b, v17.16b, v8.16b", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.16b, v3.b[15]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_01_11b": { + "ExpectedInstructionCount": 71, + "Comment": [ + "Ranges, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "dup v7.8h, v16.h[1]", + "cmgt v6.8h, v6.8h, v17.8h", + "cmgt v7.8h, v17.8h, v7.8h", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v3.h[1]", + "bic v6.16b, v7.16b, v6.16b", + "dup v7.8h, v16.h[2]", + "dup v8.8h, v16.h[3]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[3]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "dup v8.8h, v16.h[5]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v8.8h, v3.h[5]", + "bic v7.16b, v8.16b, v7.16b", + "orr v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "dup v8.8h, v16.h[7]", + "cmgt v7.8h, v7.8h, v17.8h", + "cmgt v8.8h, v17.8h, v8.8h", + "orr v7.16b, v7.16b, v8.16b", + "dup v3.8h, v3.h[7]", + "bic v3.16b, v3.16b, v7.16b", + "orr v3.16b, v6.16b, v3.16b", + "and v3.16b, v3.16b, v5.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_10_00b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_10_01b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_10_10b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x20, lo", + "cmp w21, #0x10 (16)", + "cset x21, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "cmeq v6.16b, v16.16b, v17.16b", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w23, v4.b[0]", + "cmp w23, #0x10 (16)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w23, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_10_11b": { + "ExpectedInstructionCount": 44, + "Comment": [ + "Equal Each, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x20, lo", + "cmp w21, #0x8 (8)", + "cset x21, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "cmeq v6.8h, v16.8h, v17.8h", + "and v7.16b, v3.16b, v5.16b", + "orr v3.16b, v3.16b, v5.16b", + "and v6.16b, v6.16b, v7.16b", + "orn v3.16b, v6.16b, v3.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w23, v4.h[0]", + "cmp w23, #0x8 (8)", + "cset x24, eq", + "mov w27, #0x0", + "cmp w23, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w23, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x22, x30, #28", + "orr x22, x22, x24, lsl #29", + "orr x21, x22, x21, lsl #30", + "orr x20, x21, x20, lsl #31", + "mov w26, #0x1", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_11_00b": { + "ExpectedInstructionCount": 142, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v7.16b, v3.b[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[1]", + "ext v8.16b, v17.16b, v7.16b, #1", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[2]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[3]", + "ext v8.16b, v17.16b, v7.16b, #3", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[5]", + "ext v8.16b, v17.16b, v7.16b, #5", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[7]", + "ext v8.16b, v17.16b, v7.16b, #7", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[7]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[8]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[9]", + "ext v8.16b, v17.16b, v7.16b, #9", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[9]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[10]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[11]", + "ext v8.16b, v17.16b, v7.16b, #11", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[11]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[12]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[13]", + "ext v8.16b, v17.16b, v7.16b, #13", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[13]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[14]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[15]", + "ext v8.16b, v17.16b, v7.16b, #15", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.16b, w20", + "cmgt v6.16b, v6.16b, v2.16b", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_11_01b": { + "ExpectedInstructionCount": 94, + "Comment": [ + "Equal Ordered, Negative masked polarity, Unsigned words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v7.8h, v3.h[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[1]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[2]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[3]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[5]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[7]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.8h, w20", + "cmgt v6.8h, v6.8h, v2.8h", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_11_10b": { + "ExpectedInstructionCount": 142, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed bytes, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3168]", + "cmeq v3.16b, v16.16b, #0", + "movi v4.16b, #0x10", + "bsl v3.16b, v2.16b, v4.16b", + "uminv b3, v3.16b", + "cmeq v5.16b, v17.16b, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv b5, v5.16b", + "umov w20, v3.b[0]", + "umov w21, v5.b[0]", + "dup v3.16b, v3.b[0]", + "cmgt v3.16b, v3.16b, v2.16b", + "dup v5.16b, v5.b[0]", + "mov w22, #0x10", + "cmp w20, #0x10 (16)", + "cset x23, lo", + "cmp w21, #0x10 (16)", + "cset x24, lo", + "cmgt v5.16b, v5.16b, v2.16b", + "dup v6.16b, v16.b[0]", + "cmeq v6.16b, v17.16b, v6.16b", + "dup v7.16b, v3.b[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[1]", + "ext v8.16b, v17.16b, v7.16b, #1", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[2]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[3]", + "ext v8.16b, v17.16b, v7.16b, #3", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[4]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[5]", + "ext v8.16b, v17.16b, v7.16b, #5", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[6]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[7]", + "ext v8.16b, v17.16b, v7.16b, #7", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[7]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[8]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[8]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[9]", + "ext v8.16b, v17.16b, v7.16b, #9", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[9]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[10]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[10]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[11]", + "ext v8.16b, v17.16b, v7.16b, #11", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[11]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[12]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[12]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[13]", + "ext v8.16b, v17.16b, v7.16b, #13", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[13]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[14]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v8.16b, v3.b[14]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.16b, v16.b[15]", + "ext v8.16b, v17.16b, v7.16b, #15", + "cmeq v7.16b, v8.16b, v7.16b", + "dup v3.16b, v3.b[15]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x10 (16)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.16b, w20", + "cmgt v6.16b, v6.16b, v2.16b", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv b4, v4.16b", + "umov w20, v4.b[0]", + "cmp w20, #0x10 (16)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv b2, v2.16b", + "umov w18, v2.b[0]", + "cmp w20, #0x10 (16)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] + }, + "pcmpistri xmm0, xmm1, 0_1_11_11_11b": { + "ExpectedInstructionCount": 94, + "Comment": [ + "Equal Ordered, Negative masked polarity, Signed words, MSB index", + "0x66 0x0f 0x3A 0x63" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x28, #3136]", + "cmeq v3.8h, v16.8h, #0", + "movi v4.8h, #0x8", + "bsl v3.16b, v2.16b, v4.16b", + "uminv h3, v3.8h", + "cmeq v5.8h, v17.8h, #0", + "bsl v5.16b, v2.16b, v4.16b", + "uminv h5, v5.8h", + "umov w20, v3.h[0]", + "umov w21, v5.h[0]", + "dup v3.8h, v3.h[0]", + "cmgt v3.8h, v3.8h, v2.8h", + "dup v5.8h, v5.h[0]", + "mov w22, #0x8", + "cmp w20, #0x8 (8)", + "cset x23, lo", + "cmp w21, #0x8 (8)", + "cset x24, lo", + "cmgt v5.8h, v5.8h, v2.8h", + "dup v6.8h, v16.h[0]", + "cmeq v6.8h, v17.8h, v6.8h", + "dup v7.8h, v3.h[0]", + "orn v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[1]", + "ext v8.16b, v17.16b, v7.16b, #2", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[1]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[2]", + "ext v8.16b, v17.16b, v7.16b, #4", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[2]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[3]", + "ext v8.16b, v17.16b, v7.16b, #6", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[3]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[4]", + "ext v8.16b, v17.16b, v7.16b, #8", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[4]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[5]", + "ext v8.16b, v17.16b, v7.16b, #10", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[5]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[6]", + "ext v8.16b, v17.16b, v7.16b, #12", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v8.8h, v3.h[6]", + "orn v7.16b, v7.16b, v8.16b", + "and v6.16b, v6.16b, v7.16b", + "dup v7.8h, v16.h[7]", + "ext v8.16b, v17.16b, v7.16b, #14", + "cmeq v7.8h, v8.8h, v7.8h", + "dup v3.8h, v3.h[7]", + "orn v3.16b, v7.16b, v3.16b", + "and v3.16b, v6.16b, v3.16b", + "sub w30, w21, w20", + "mov w26, #0x1", + "add w30, w30, #0x1 (1)", + "cmp w21, #0x8 (8)", + "csel w21, w30, w22, lo", + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "csel w20, w22, w21, eq", + "dup v6.8h, w20", + "cmgt v6.8h, v6.8h, v2.8h", + "and v3.16b, v3.16b, v6.16b", + "eor v3.16b, v3.16b, v5.16b", + "bit v4.16b, v2.16b, v3.16b", + "uminv h4, v4.8h", + "umov w20, v4.h[0]", + "cmp w20, #0x8 (8)", + "cset x21, eq", + "cmp w20, #0x0 (0)", + "cset x30, eq", + "and v2.16b, v2.16b, v3.16b", + "umaxv h2, v2.8h", + "umov w18, v2.h[0]", + "cmp w20, #0x8 (8)", + "csel w7, w22, w18, eq", + "lsl x20, x30, #28", + "orr x20, x20, x21, lsl #29", + "orr x20, x20, x24, lsl #30", + "orr x20, x20, x23, lsl #31", + "msr nzcv, x20" + ] } } }