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Merge pull request #3115 from lioncash/sqxtun

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Arm64/VectorOps: Elide moves where applicable in 128-bit VSQXTUN2
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Ryan Houdek authored and GitHub committed 2023-09-17 14:51:27 -07:00
2 parents 950a8dbfe7 26e4d8ad59
commit fd1b639ad9
1 file changed
+11 -3
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FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+11 -3
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@@ -3419,9 +3419,17 @@ DEF_OP(VSQXTUN2) {
mov(Dst.Q(), VectorLower.Q());
ins(ARMEmitter::SubRegSize::i32Bit, Dst, 1, VTMP2, 0);
} else {
mov(VTMP1.Q(), VectorLower.Q());
sqxtun2(SubRegSize, VTMP1, VectorUpper);
mov(Dst.Q(), VTMP1.Q());
auto Lower = VectorLower;
if (Dst != VectorLower) {
mov(VTMP1.Q(), VectorLower.Q());
Lower = VTMP1;
}
sqxtun2(SubRegSize, Lower, VectorUpper);
if (Dst != VectorLower) {
mov(Dst.Q(), Lower.Q());
}
}
}
}