From 566b25a35b351a21a313308ddae6477f2ef32265 Mon Sep 17 00:00:00 2001
From: Simon Scherer <git69566@pinebound.com>
Date: Thu, 27 Aug 2026 10:33:05 +0200
Subject: [PATCH 1/3] unittests/ASM: Test pfacc simple addition

---
 unittests/ASM/FEX_bugs/PFACC_MMXWidth.asm | 25 +++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 unittests/ASM/FEX_bugs/PFACC_MMXWidth.asm

diff --git a/unittests/ASM/FEX_bugs/PFACC_MMXWidth.asm b/unittests/ASM/FEX_bugs/PFACC_MMXWidth.asm
new file mode 100644
index 000000000..316eae165
--- /dev/null
+++ b/unittests/ASM/FEX_bugs/PFACC_MMXWidth.asm
@@ -0,0 +1,25 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "MM0": "0x40e0000040400000"
+  },
+  "HostFeatures": ["3DNOW"]
+}
+%endif
+
+femms
+movq mm0, [rel .dst_value]
+movq mm1, [rel .src_value]
+
+pfacc mm0, mm1
+
+hlt
+
+align 8
+.dst_value:
+dd 0x3f800000 ; 1.0
+dd 0x40000000 ; 2.0
+
+.src_value:
+dd 0x40400000 ; 3.0
+dd 0x40800000 ; 4.0

From f0135eb332c7c7f11ca87eadcbc03e000ddc8575 Mon Sep 17 00:00:00 2001
From: Simon Scherer <git69566@pinebound.com>
Date: Thu, 27 Aug 2026 10:36:22 +0200
Subject: [PATCH 2/3] JIT/VectorOps: Separate 64-bit VFAddP path for MMX-sized
 operands

---
 FEXCore/Source/Interface/Core/JIT/VectorOps.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
index d9ad4294c..65a692354 100644
--- a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
@@ -1297,6 +1297,7 @@ DEF_OP(VFAddP) {
   const auto Op = IROp->C<IR::IROp_VFAddP>();
   const auto OpSize = IROp->Size;
 
+  const auto IsScalar = OpSize == IR::OpSize::i64Bit;
   const auto Is256Bit = OpSize == IR::OpSize::i256Bit;
   LOGMAN_THROW_A_FMT(!Is256Bit || HostSupportsSVE256, "Need SVE256 support in order to use {} with 256-bit operation", __func__);
 
@@ -1327,6 +1328,8 @@ DEF_OP(VFAddP) {
 
     // Merge upper half with lower half.
     splice<ARMEmitter::OpType::Destructive>(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), PRED_TMP_16B, Dst.Z(), VTMP2.Z());
+  } else if (IsScalar) {
+    faddp(SubRegSize, Dst.D(), VectorLower.D(), VectorUpper.D());
   } else {
     faddp(SubRegSize, Dst.Q(), VectorLower.Q(), VectorUpper.Q());
   }

From 79ef5031eb5c8cfffc6fc50b4c7ce72742f83a31 Mon Sep 17 00:00:00 2001
From: Simon Scherer <git69566@pinebound.com>
Date: Thu, 27 Aug 2026 10:36:31 +0200
Subject: [PATCH 3/3] InstcountCI: Update

---
 unittests/InstructionCountCI/DDD.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json
index 0c3d1288a..606f1e788 100644
--- a/unittests/InstructionCountCI/DDD.json
+++ b/unittests/InstructionCountCI/DDD.json
@@ -145,7 +145,7 @@
         "ldr d3, [x28, #1072]",
         "dup v4.2s, v2.s[1]",
         "fsub s2, s2, s4",
-        "faddp v3.4s, v3.4s, v3.4s",
+        "faddp v3.2s, v3.2s, v3.2s",
         "mov v2.s[1], v3.s[0]",
         "str d2, [x28, #1056]",
         "strh w20, [x28, #1064]"