diff --git a/FEXCore/Scripts/json_ir_generator.py b/FEXCore/Scripts/json_ir_generator.py index 66bf96dc6..27a7cefb2 100755 --- a/FEXCore/Scripts/json_ir_generator.py +++ b/FEXCore/Scripts/json_ir_generator.py @@ -678,6 +678,7 @@ def print_ir_allocator_helpers(): # Generate helpers with operands for op in IROps: if op.Name != "Last": + output_file.write("\t///\n".join(["\t/// {}\n" .format(comment) for comment in op.Desc])) output_file.write("\tIRPair _{}(" .format(op.Name, op.Name)) # Output SSA args first @@ -751,6 +752,7 @@ def print_ir_allocator_helpers(): # Now do the OrderedNode * version if necessary if op.SSAArgNum: + output_file.write("\t///\n".join(["\t/// {}\n" .format(comment) for comment in op.Desc])) output_file.write("\tIRPair _{}(" .format(op.Name, op.Name)) for i, arg in enumerate(op.Arguments): diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 565d4286d..ee933aed7 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -488,7 +488,7 @@ "HasSideEffects": true, "Desc": ["Spills an SSA value to memory", "Spill slots are register allocated and has live ranges calculated to handle slot calculation", - "```diff\n- !Don't use this op. It is for RA to handle spilling and filling!\n```" + "!Don't use this op. It is for RA to handle spilling and filling!" ], "EmitValidation": [ "WalkFindRegClass($Value) == $Class" @@ -498,7 +498,7 @@ "SSA = FillRegister OpSize:#Size, OpSize:#ElementSize, u32:$Slot, RegisterClass:$Class": { "Desc": ["Fills a register from a spill slot", "Spill slots are register allocated and has live ranges calculated to handle slot calculation", - "```diff\n- !Don't use this op. It is for RA to handle spilling and filling!\n```" + "!Don't use this op. It is for RA to handle spilling and filling!" ], "DestSize": "Size", "ElementSize": "ElementSize"