diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 7a93e64ed..7ee6fbcec 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -176,7 +176,7 @@ void OpDispatchBuilder::ThunkOp(OpcodeArgs) {
   auto Constant = _Constant(GPRSize);
   auto OldSP = LoadGPRRegister(X86State::REG_RSP);
   auto NewRIP = _LoadMem(GPRClass, GPRSize, OldSP, GPRSize);
-  OrderedNode *NewSP = _Add(OldSP, Constant);
+  OrderedNode *NewSP = _Add(IR::SizeToOpSize(GPRSize), OldSP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -235,10 +235,10 @@ void OpDispatchBuilder::RETOp(OpcodeArgs) {
   OrderedNode *NewSP;
   if (Op->OP == 0xC2) {
     auto Offset = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
-    NewSP = _Add(_Add(OldSP, Constant), Offset);
+    NewSP = _Add(IR::SizeToOpSize(GPRSize), _Add(IR::SizeToOpSize(GPRSize), OldSP, Constant), Offset);
   }
   else {
-    NewSP = _Add(OldSP, Constant);
+    NewSP = _Add(IR::SizeToOpSize(GPRSize), OldSP, Constant);
   }
 
   // Store the new stack pointer
@@ -278,30 +278,30 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) {
 
   // RIP (64/32/16 bits)
   auto NewRIP = _LoadMem(GPRClass, GPRSize, SP, GPRSize);
-  SP = _Add(SP, Constant);
+  SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
   // CS (lower 16 used)
   auto NewSegmentCS = _LoadMem(GPRClass, GPRSize, SP, GPRSize);
   _StoreContext(2, GPRClass, NewSegmentCS, offsetof(FEXCore::Core::CPUState, cs_idx));
   UpdatePrefixFromSegment(NewSegmentCS, FEXCore::X86Tables::DecodeFlags::FLAG_CS_PREFIX);
 
-  SP = _Add(SP, Constant);
+  SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
   //eflags (lower 16 used)
   auto eflags = _LoadMem(GPRClass, GPRSize, SP, GPRSize);
   SetPackedRFLAG(false, eflags);
-  SP = _Add(SP, Constant);
+  SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
 
   if (CTX->Config.Is64BitMode) {
     // RSP and SS only happen in 64-bit mode or if this is a CPL mode jump!
     // FEX doesn't support a CPL mode switch, so don't need to worry about this on 32-bit
     StoreGPRRegister(X86State::REG_RSP, _LoadMem(GPRClass, GPRSize, SP, GPRSize));
 
-    SP = _Add(SP, Constant);
+    SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
     // ss
     auto NewSegmentSS = _LoadMem(GPRClass, GPRSize, SP, GPRSize);
     _StoreContext(2, GPRClass, NewSegmentSS, offsetof(FEXCore::Core::CPUState, ss_idx));
     UpdatePrefixFromSegment(NewSegmentSS, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX);
 
-    SP = _Add(SP, Constant);
+    SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
   }
   else {
     // Store the stack in 32-bit mode
@@ -375,7 +375,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
     switch (IROp) {
       case FEXCore::IR::IROps::OP_ADD: {
         Dest = _AtomicFetchAdd(IR::SizeToOpSize(Size), Src, DestMem);
-        Result = _Add(Dest, Src);
+        Result = _Add(IR::SizeToOpSize(std::max<uint8_t>(4u, std::max(GetOpSize(Dest), GetOpSize(Src)))), Dest, Src);
         break;
       }
       case FEXCore::IR::IROps::OP_SUB: {
@@ -405,7 +405,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
   }
   else {
     Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
-    auto ALUOp = _Add(Dest, Src);
+    auto ALUOp = _Add(IR::SizeToOpSize(std::max<uint8_t>(4u, Size)), Dest, Src);
     // Overwrite our IR's op type
     ALUOp.first->Header.Op = IROp;
 
@@ -446,9 +446,10 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs) {
 
   OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
   uint8_t Size = GetDstSize(Op);
+  const auto OpSize = IR::SizeToOpSize(std::max<uint8_t>(4u, Size));
 
   auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC, IR::SizeToOpSize(Size));
-  auto ALUOp = _Add(Src, CF);
+  auto ALUOp = _Add(OpSize, Src, CF);
 
   OrderedNode *Result{};
   OrderedNode *Before{};
@@ -457,11 +458,11 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs) {
     OrderedNode *DestMem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1, false);
     DestMem = AppendSegmentOffset(DestMem, Op->Flags);
     Before = _AtomicFetchAdd(IR::SizeToOpSize(Size), ALUOp, DestMem);
-    Result = _Add(Before, ALUOp);
+    Result = _Add(OpSize, Before, ALUOp);
   }
   else {
     Before = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
-    Result = _Add(Before, ALUOp);
+    Result = _Add(OpSize, Before, ALUOp);
     StoreResult(GPRClass, Op, Result, -1);
   }
 
@@ -477,9 +478,10 @@ void OpDispatchBuilder::SBBOp(OpcodeArgs) {
 
   OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
   auto Size = GetDstSize(Op);
+  const auto OpSize = IR::SizeToOpSize(std::max<uint8_t>(4u, Size));
 
   auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC, IR::SizeToOpSize(Size));
-  auto ALUOp = _Add(Src, CF);
+  auto ALUOp = _Add(OpSize, Src, CF);
 
   OrderedNode *Result{};
   OrderedNode *Before{};
@@ -650,7 +652,7 @@ void OpDispatchBuilder::POPOp(OpcodeArgs) {
   auto Constant = _Constant(Size);
   auto OldSP = LoadGPRRegister(X86State::REG_RSP);
   auto NewGPR = _LoadMem(GPRClass, Size, OldSP, Size);
-  auto NewSP = _Add(OldSP, Constant);
+  auto NewSP = _Add(OpSize::i64Bit, OldSP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -680,32 +682,32 @@ void OpDispatchBuilder::POPAOp(OpcodeArgs) {
   OrderedNode *NewSP = OldSP;
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RDI, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RSI, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RBP, Src, Size);
-  NewSP = _Add(NewSP, _Constant(Size * 2));
+  NewSP = _Add(OpSize::i64Bit, NewSP, _Constant(Size * 2));
 
   // Skip SP loading
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RBX, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RDX, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RCX, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   Src = _LoadMem(GPRClass, Size, NewSP, Size);
   StoreGPRRegister(X86State::REG_RAX, Src, Size);
-  NewSP = _Add(NewSP, Constant);
+  NewSP = _Add(OpSize::i64Bit, NewSP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -719,7 +721,7 @@ void OpDispatchBuilder::POPSegmentOp(OpcodeArgs) {
   auto Constant = _Constant(SrcSize);
   auto OldSP = LoadGPRRegister(X86State::REG_RSP);
   auto NewSegment = _LoadMem(GPRClass, SrcSize, OldSP, SrcSize);
-  auto NewSP = _Add(OldSP, Constant);
+  auto NewSP = _Add(OpSize::i64Bit, OldSP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -757,7 +759,7 @@ void OpDispatchBuilder::LEAVEOp(OpcodeArgs) {
   auto OldBP = LoadGPRRegister(X86State::REG_RBP);
 
   auto NewGPR = _LoadMem(GPRClass, Size, OldBP, Size);
-  auto NewSP = _Add(OldBP, Constant);
+  auto NewSP = _Add(IR::SizeToOpSize(Size), OldBP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -786,7 +788,7 @@ void OpDispatchBuilder::CALLOp(OpcodeArgs) {
 
   OrderedNode *JMPPCOffset = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
 
-  OrderedNode *NewRIP = _Add(ConstantPC, JMPPCOffset);
+  OrderedNode *NewRIP = _Add(IR::SizeToOpSize(GPRSize), ConstantPC, JMPPCOffset);
   auto ConstantPCReturn = GetRelocatedPC(Op);
 
   auto ConstantSize = _Constant(GPRSize);
@@ -1356,7 +1358,7 @@ void OpDispatchBuilder::JUMPOp(OpcodeArgs) {
   // Fallback
   {
     auto RIPTargetConst = GetRelocatedPC(Op);
-    auto NewRIP = _Add(_Constant(TargetOffset), RIPTargetConst);
+    auto NewRIP = _Add(OpSize::i64Bit, _Constant(TargetOffset), RIPTargetConst);
 
     // Store the new RIP
     _ExitFunction(NewRIP);
@@ -2475,6 +2477,7 @@ void OpDispatchBuilder::PEXT(OpcodeArgs) {
 
 void OpDispatchBuilder::ADXOp(OpcodeArgs) {
   const auto OperandSize = GetSrcSize(Op);
+  const auto OpSize = OpSizeFromSrc(Op);
 
   // Calculate flags early.
   CalculateDeferredFlags();
@@ -2494,8 +2497,8 @@ void OpDispatchBuilder::ADXOp(OpcodeArgs) {
   auto* Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
   auto* Before = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
 
-  auto ALUOp = _Add(Src, Flag);
-  auto Result = _Add(Before, ALUOp);
+  auto ALUOp = _Add(OpSize, Src, Flag);
+  auto Result = _Add(OpSize, Before, ALUOp);
 
   StoreResult(GPRClass, Op, Result, -1);
 
@@ -2953,7 +2956,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) {
     // Then use that to index in to the memory location by size of op
 
     // Now add the addresses together and load the memory
-    OrderedNode *MemoryLocation = _Add(Dest, Src);
+    OrderedNode *MemoryLocation = _Add(OpSize::i64Bit, Dest, Src);
     Result = _LoadMemAutoTSO(GPRClass, 1, MemoryLocation, 1);
 
     // Now shift in to the correct bit location
@@ -3017,7 +3020,7 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
     // Then use that to index in to the memory location by size of op
 
     // Now add the addresses together and load the memory
-    OrderedNode *MemoryLocation = _Add(Dest, Src);
+    OrderedNode *MemoryLocation = _Add(OpSize::i64Bit, Dest, Src);
     OrderedNode *BitMask = _Lshl(OpSize::i64Bit, _Constant(1), BitSelect);
 
     if (DestIsLockedMem(Op)) {
@@ -3094,7 +3097,7 @@ void OpDispatchBuilder::BTSOp(OpcodeArgs) {
     // Then use that to index in to the memory location by size of op
 
     // Now add the addresses together and load the memory
-    OrderedNode *MemoryLocation = _Add(Dest, Src);
+    OrderedNode *MemoryLocation = _Add(OpSize::i64Bit, Dest, Src);
     OrderedNode *BitMask = _Lshl(OpSize::i64Bit, _Constant(1), BitSelect);
 
     if (DestIsLockedMem(Op)) {
@@ -3168,7 +3171,7 @@ void OpDispatchBuilder::BTCOp(OpcodeArgs) {
     // Then use that to index in to the memory location by size of op
 
     // Now add the addresses together and load the memory
-    OrderedNode *MemoryLocation = _Add(Dest, Src);
+    OrderedNode *MemoryLocation = _Add(OpSize::i64Bit, Dest, Src);
     OrderedNode *BitMask = _Lshl(OpSize::i64Bit, _Constant(1), BitSelect);
 
     if (DestIsLockedMem(Op)) {
@@ -3363,10 +3366,11 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
   OrderedNode *Result;
 
   const auto Size = GetSrcBitSize(Op);
+  const auto OpSize = Size == 64 ? OpSize::i64Bit : OpSize::i32Bit;
 
   if (Op->Dest.IsGPR()) {
     // If this is a GPR then we can just do an Add
-    Result = _Add(Dest, Src);
+    Result = _Add(OpSize, Dest, Src);
 
     // Previous value in dest gets stored in src
     StoreResult(GPRClass, Op, Op->Src[0], Dest, -1);
@@ -3385,7 +3389,7 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
     Dest = AppendSegmentOffset(Dest, Op->Flags);
     auto Before = _AtomicFetchAdd(OpSizeFromSrc(Op), Src, Dest);
     StoreResult(GPRClass, Op, Op->Src[0], Before, -1);
-    Result = _Add(Before, Src); // Seperate result just for flags
+    Result = _Add(OpSize, Before, Src); // Seperate result just for flags
 
     if (Size < 32) {
       Result = _Bfe(OpSize::i32Bit, Size, 0, Result);
@@ -3426,7 +3430,7 @@ void OpDispatchBuilder::DAAOp(OpcodeArgs) {
   }
   SetCurrentCodeBlock(TrueBlock);
   {
-    auto NewAL = _Add(AL, _Constant(0x6));
+    auto NewAL = _Add(OpSize::i64Bit, AL, _Constant(0x6));
     StoreGPRRegister(X86State::REG_RAX, NewAL, 1);
     CalculateDeferredFlags();
     auto NewCF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
@@ -3456,7 +3460,7 @@ void OpDispatchBuilder::DAAOp(OpcodeArgs) {
   {
     AL = LoadGPRRegister(X86State::REG_RAX, 1);
 
-    auto NewAL = _Add(AL, _Constant(0x60));
+    auto NewAL = _Add(OpSize::i64Bit, AL, _Constant(0x60));
     StoreGPRRegister(X86State::REG_RAX, NewAL, 1);
     SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Constant(1));
     CalculateDeferredFlags();
@@ -3561,7 +3565,7 @@ void OpDispatchBuilder::AAAOp(OpcodeArgs) {
   }
   SetCurrentCodeBlock(TrueBlock);
   {
-    auto NewAX = _Add(AX, _Constant(0x106));
+    auto NewAX = _Add(OpSize::i64Bit, AX, _Constant(0x106));
     auto Result = _And(OpSize::i64Bit, NewAX, _Constant(0xFF0F));
     StoreGPRRegister(X86State::REG_RAX, Result, 2);
     SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Constant(1));
@@ -3616,7 +3620,7 @@ void OpDispatchBuilder::AAMOp(OpcodeArgs) {
   auto UDivOp = _UDiv(OpSize::i64Bit, AL, Imm8);
   auto URemOp = _URem(OpSize::i64Bit, AL, Imm8);
   auto AH = _Lshl(OpSize::i64Bit, UDivOp, _Constant(8));
-  auto AX = _Add(AH, URemOp);
+  auto AX = _Add(OpSize::i64Bit, AH, URemOp);
   StoreGPRRegister(X86State::REG_RAX, AX, 2);
 
   // Update Flags
@@ -3632,7 +3636,7 @@ void OpDispatchBuilder::AADOp(OpcodeArgs) {
   auto AL = LoadGPRRegister(X86State::REG_RAX, 1);
   auto AH = _Lshr(OpSize::i32Bit, LoadGPRRegister(X86State::REG_RAX, 2), _Constant(8));
   auto Imm8 = _Constant(Op->Src[0].Data.Literal.Value & 0xFF);
-  auto NewAL = _Add(AL, _Mul(OpSize::i64Bit, AH, Imm8));
+  auto NewAL = _Add(OpSize::i64Bit, AL, _Mul(OpSize::i64Bit, AH, Imm8));
   auto Result = _And(OpSize::i64Bit, NewAL, _Constant(0xFF));
   StoreGPRRegister(X86State::REG_RAX, Result, 2);
 
@@ -3648,7 +3652,7 @@ void OpDispatchBuilder::XLATOp(OpcodeArgs) {
   OrderedNode *Offset = LoadGPRRegister(X86State::REG_RAX, 1);
 
   Src = AppendSegmentOffset(Src, Op->Flags, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX);
-  Src = _Add(Src, Offset);
+  Src = _Add(OpSize::i64Bit, Src, Offset);
 
   auto Res = _LoadMemAutoTSO(GPRClass, 1, Src, 1);
 
@@ -3743,7 +3747,7 @@ void OpDispatchBuilder::SGDTOp(OpcodeArgs) {
   }
 
   _StoreMemAutoTSO(GPRClass, 2, DestAddress, _Constant(0));
-  _StoreMemAutoTSO(GPRClass, GDTStoreSize, _Add(DestAddress, _Constant(2)), _Constant(GDTAddress));
+  _StoreMemAutoTSO(GPRClass, GDTStoreSize, _Add(OpSize::i64Bit, DestAddress, _Constant(2)), _Constant(GDTAddress));
 }
 
 void OpDispatchBuilder::RDTSCOp(OpcodeArgs) {
@@ -3778,7 +3782,7 @@ void OpDispatchBuilder::INCOp(OpcodeArgs) {
     Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
   }
 
-  Result = _Add(Dest, OneConst);
+  Result = _Add(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, OneConst);
   if (!IsLocked) {
     StoreResult(GPRClass, Op, Result, -1);
   }
@@ -3854,7 +3858,7 @@ void OpDispatchBuilder::STOSOp(OpcodeArgs) {
 
     // Offset the pointer
     OrderedNode *TailDest = LoadGPRRegister(X86State::REG_RDI);
-    TailDest = _Add(TailDest, PtrDir);
+    TailDest = _Add(OpSize::i64Bit, TailDest, PtrDir);
 
     StoreGPRRegister(X86State::REG_RDI, TailDest);
   }
@@ -3925,8 +3929,8 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) {
     // Store to memory where RDI points
     _StoreMemAutoTSO(GPRClass, Size, RDI, Src, Size);
 
-    RSI = _Add(RSI, PtrDir);
-    RDI = _Add(RDI, PtrDir);
+    RSI = _Add(OpSize::i64Bit, RSI, PtrDir);
+    RDI = _Add(OpSize::i64Bit, RDI, PtrDir);
 
     StoreGPRRegister(X86State::REG_RSI, RSI);
     StoreGPRRegister(X86State::REG_RDI, RDI);
@@ -3967,11 +3971,11 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
         _Constant(Size), _Constant(-Size));
 
     // Offset the pointer
-    Dest_RDI = _Add(Dest_RDI, PtrDir);
+    Dest_RDI = _Add(OpSize::i64Bit, Dest_RDI, PtrDir);
     StoreGPRRegister(X86State::REG_RDI, Dest_RDI);
 
     // Offset second pointer
-    Dest_RSI = _Add(Dest_RSI, PtrDir);
+    Dest_RSI = _Add(OpSize::i64Bit, Dest_RSI, PtrDir);
     StoreGPRRegister(X86State::REG_RSI, Dest_RSI);
   }
   else {
@@ -4033,11 +4037,11 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
       StoreGPRRegister(X86State::REG_RCX, TailCounter);
 
       // Offset the pointer
-      Dest_RDI = _Add(Dest_RDI, PtrDir);
+      Dest_RDI = _Add(OpSize::i64Bit, Dest_RDI, PtrDir);
       StoreGPRRegister(X86State::REG_RDI, Dest_RDI);
 
       // Offset second pointer
-      Dest_RSI = _Add(Dest_RSI, PtrDir);
+      Dest_RSI = _Add(OpSize::i64Bit, Dest_RSI, PtrDir);
       StoreGPRRegister(X86State::REG_RSI, Dest_RSI);
 
       OrderedNode *ZF = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC);
@@ -4087,7 +4091,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) {
     // Offset the pointer
     OrderedNode *TailDest_RSI = LoadGPRRegister(X86State::REG_RSI);
 
-    TailDest_RSI = _Add(TailDest_RSI, PtrDir);
+    TailDest_RSI = _Add(OpSize::i64Bit, TailDest_RSI, PtrDir);
     StoreGPRRegister(X86State::REG_RSI, TailDest_RSI);
   }
   else {
@@ -4146,7 +4150,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) {
       StoreGPRRegister(X86State::REG_RCX, TailCounter);
 
       // Offset the pointer
-      TailDest_RSI = _Add(TailDest_RSI, PtrDir);
+      TailDest_RSI = _Add(OpSize::i64Bit, TailDest_RSI, PtrDir);
       StoreGPRRegister(X86State::REG_RSI, TailDest_RSI);
 
       // Jump back to the start, we have more work to do
@@ -4192,7 +4196,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
     // Offset the pointer
     OrderedNode *TailDest_RDI = LoadGPRRegister(X86State::REG_RDI);
 
-    TailDest_RDI = _Add(TailDest_RDI, PtrDir);
+    TailDest_RDI = _Add(OpSize::i64Bit, TailDest_RDI, PtrDir);
     StoreGPRRegister(X86State::REG_RDI, TailDest_RDI);
   }
   else {
@@ -4256,7 +4260,7 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) {
       StoreGPRRegister(X86State::REG_RCX, TailCounter);
 
       // Offset the pointer
-      TailDest_RDI = _Add(TailDest_RDI, PtrDir);
+      TailDest_RDI = _Add(OpSize::i64Bit, TailDest_RDI, PtrDir);
       StoreGPRRegister(X86State::REG_RDI, TailDest_RDI);
 
       OrderedNode *ZF = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC);
@@ -4313,7 +4317,7 @@ void OpDispatchBuilder::POPFOp(OpcodeArgs) {
   auto Constant = _Constant(Size);
   auto OldSP = LoadGPRRegister(X86State::REG_RSP);
   OrderedNode *Src = _LoadMem(GPRClass, Size, OldSP, Size);
-  auto NewSP = _Add(OldSP, Constant);
+  auto NewSP = _Add(OpSize::i64Bit, OldSP, Constant);
 
   // Store the new stack pointer
   StoreGPRRegister(X86State::REG_RSP, NewSP);
@@ -4833,7 +4837,7 @@ OrderedNode *OpDispatchBuilder::GetSegment(uint32_t Flags, uint32_t DefaultPrefi
 OrderedNode *OpDispatchBuilder::AppendSegmentOffset(OrderedNode *Value, uint32_t Flags, uint32_t DefaultPrefix, bool Override) {
   auto Segment = GetSegment(Flags, DefaultPrefix, Override);
   if (Segment) {
-    Value = _Add(Value, Segment);
+    Value = _Add(IR::SizeToOpSize(std::max<uint8_t>(4, std::max(GetOpSize(Value), GetOpSize(Segment)))), Value, Segment);
   }
 
   return Value;
@@ -5004,7 +5008,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
 
     auto Constant = _Constant(GPRSize * 8, Operand.Data.GPRIndirect.Displacement);
 
-    Src = _Add(GPR, Constant);
+    Src = _Add(IR::SizeToOpSize(GPRSize), GPR, Constant);
 
     LoadableType = true;
     if (Operand.Data.GPRIndirect.GPR == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::ACCESS_DEFAULT) {
@@ -5051,7 +5055,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
       auto GPR = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
 
       if (Tmp != nullptr) {
-        Tmp = _Add(Tmp, GPR);
+        Tmp = _Add(IR::SizeToOpSize(GPRSize), Tmp, GPR);
       }
       else {
         Tmp = GPR;
@@ -5064,7 +5068,7 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
 
     if (Operand.Data.SIB.Offset) {
       if (Tmp != nullptr) {
-        Src = _Add(Tmp, _Constant(GPRSize * 8, Operand.Data.SIB.Offset));
+        Src = _Add(IR::SizeToOpSize(GPRSize), Tmp, _Constant(GPRSize * 8, Operand.Data.SIB.Offset));
       }
       else {
         Src = _Constant(GPRSize * 8, Operand.Data.SIB.Offset);
@@ -5252,7 +5256,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
     auto GPR = LoadGPRRegister(Operand.Data.GPRIndirect.GPR, GPRSize);
     auto Constant = _Constant(GPRSize * 8, Operand.Data.GPRIndirect.Displacement);
 
-    MemStoreDst = _Add(GPR, Constant);
+    MemStoreDst = _Add(IR::SizeToOpSize(GPRSize), GPR, Constant);
     MemStore = true;
     if (Operand.Data.GPRIndirect.GPR == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::ACCESS_DEFAULT) {
       AccessType = MemoryAccessType::ACCESS_NONTSO;
@@ -5283,7 +5287,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
       auto GPR = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
 
       if (Tmp != nullptr) {
-        Tmp = _Add(Tmp, GPR);
+        Tmp = _Add(IR::SizeToOpSize(GPRSize), Tmp, GPR);
       }
       else {
         Tmp = GPR;
@@ -5292,7 +5296,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
 
     if (Operand.Data.SIB.Offset) {
       if (Tmp != nullptr) {
-        MemStoreDst = _Add(Tmp, _Constant(GPRSize * 8, Operand.Data.SIB.Offset));
+        MemStoreDst = _Add(IR::SizeToOpSize(GPRSize), Tmp, _Constant(GPRSize * 8, Operand.Data.SIB.Offset));
       }
       else {
         MemStoreDst = _Constant(GPRSize * 8, Operand.Data.SIB.Offset);
@@ -5323,7 +5327,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
       // For X87 extended doubles, split before storing
       _StoreMem(FPRClass, 8, MemStoreDst, Src, Align);
       auto Upper = _VExtractToGPR(16, 8, Src, 1);
-      auto DestAddr = _Add(MemStoreDst, _Constant(8));
+      auto DestAddr = _Add(OpSize::i64Bit, MemStoreDst, _Constant(8));
       _StoreMem(GPRClass, 2, DestAddr, Upper, std::min<uint8_t>(Align, 8));
     } else {
       if (AccessType == MemoryAccessType::ACCESS_NONTSO || AccessType == MemoryAccessType::ACCESS_STREAM) {
@@ -5381,6 +5385,7 @@ void OpDispatchBuilder::MOVGPRNTOp(OpcodeArgs) {
 
 void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask) {
   auto Size = GetDstSize(Op);
+  const auto OpSize = Size == 8 ? OpSize::i64Bit : OpSize::i32Bit;
 
   // X86 basic ALU ops just do the operation between the destination and a single source
   OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
@@ -5398,7 +5403,7 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor
     FetchOp.first->Header.Op = AtomicFetchOp;
     Dest = FetchOp;
 
-    auto ALUOp = _Add(Dest, Src);
+    auto ALUOp = _Add(OpSize, Dest, Src);
     // Overwrite our IR's op type
     ALUOp.first->Header.Op = ALUIROp;
 
@@ -5419,7 +5424,7 @@ void OpDispatchBuilder::ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCor
 
         Result = _Constant(0);
     } else {
-        auto ALUOp = _Add(Dest, Src);
+        auto ALUOp = _Add(OpSize, Dest, Src);
         // Overwrite our IR's op type
         ALUOp.first->Header.Op = ALUIROp;
 
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
index 6e6a608f6..facf8a138 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
@@ -26,7 +26,7 @@ void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) {
   OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
 
   auto Tmp = _Ror(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 3), _Constant(32, 2));
-  auto Top = _Add(_VExtractToGPR(16, 4, Src, 3), Tmp);
+  auto Top = _Add(OpSize::i32Bit, _VExtractToGPR(16, 4, Src, 3), Tmp);
   auto Result = _VInsGPR(16, 4, 3, Src, Top);
 
   StoreResult(FPRClass, Op, Result, -1);
@@ -117,7 +117,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
     auto C = _VExtractToGPR(16, 4, Dest, 1);
     auto D = _VExtractToGPR(16, 4, Dest, 0);
 
-    auto A1 = _Add(_Add(_Add(Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W0E), K);
+    auto A1 = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W0E), K);
     auto B1 = A;
     auto C1 = _Ror(OpSize::i32Bit, B, _Constant(32, 2));
     auto D1 = C;
@@ -127,7 +127,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
   };
   const auto Round1To3 = [&](OrderedNode *A, OrderedNode *B, OrderedNode *C,
                              OrderedNode *D, OrderedNode *E, OrderedNode *W) -> RoundResult {
-    auto ANext = _Add(_Add(_Add(_Add(Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W), E), K);
+    auto ANext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W), E), K);
     auto BNext = A;
     auto CNext = _Ror(OpSize::i32Bit, B, _Constant(32, 2));
     auto DNext = C;
@@ -163,10 +163,10 @@ void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) {
   auto W1 = _VExtractToGPR(16, 4, Dest, 1);
   auto W0 = _VExtractToGPR(16, 4, Dest, 0);
 
-  auto Sig3 = _Add(W3, Sigma0(W4));
-  auto Sig2 = _Add(W2, Sigma0(W3));
-  auto Sig1 = _Add(W1, Sigma0(W2));
-  auto Sig0 = _Add(W0, Sigma0(W1));
+  auto Sig3 = _Add(OpSize::i32Bit, W3, Sigma0(W4));
+  auto Sig2 = _Add(OpSize::i32Bit, W2, Sigma0(W3));
+  auto Sig1 = _Add(OpSize::i32Bit, W1, Sigma0(W2));
+  auto Sig0 = _Add(OpSize::i32Bit, W0, Sigma0(W1));
 
   auto D3 = _VInsGPR(16, 4, 3, Dest, Sig3);
   auto D2 = _VInsGPR(16, 4, 2, D3, Sig2);
@@ -186,10 +186,10 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
 
   auto W14 = _VExtractToGPR(16, 4, Src, 2);
   auto W15 = _VExtractToGPR(16, 4, Src, 3);
-  auto W16 = _Add(_VExtractToGPR(16, 4, Dest, 0), Sigma1(W14));
-  auto W17 = _Add(_VExtractToGPR(16, 4, Dest, 1), Sigma1(W15));
-  auto W18 = _Add(_VExtractToGPR(16, 4, Dest, 2), Sigma1(W16));
-  auto W19 = _Add(_VExtractToGPR(16, 4, Dest, 3), Sigma1(W17));
+  auto W16 = _Add(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 0), Sigma1(W14));
+  auto W17 = _Add(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 1), Sigma1(W15));
+  auto W18 = _Add(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 2), Sigma1(W16));
+  auto W19 = _Add(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 3), Sigma1(W17));
 
   auto D3 = _VInsGPR(16, 4, 3, Dest, W19);
   auto D2 = _VInsGPR(16, 4, 2, D3, W18);
@@ -234,11 +234,11 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
   const auto Round = [&](OrderedNode *A, OrderedNode *B, OrderedNode *C, OrderedNode *D,
                          OrderedNode *E, OrderedNode *F, OrderedNode *G, OrderedNode *H,
                          OrderedNode* WK) -> RoundResult {
-    auto ANext = _Add(_Add(_Add(_Add(_Add(Ch(E, F, G), Sigma1(E)), WK), H), Major(A, B, C)), Sigma0(A));
+    auto ANext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Ch(E, F, G), Sigma1(E)), WK), H), Major(A, B, C)), Sigma0(A));
     auto BNext = A;
     auto CNext = B;
     auto DNext = C;
-    auto ENext = _Add(_Add(_Add(_Add(Ch(E, F, G), Sigma1(E)), WK), H), D);
+    auto ENext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Ch(E, F, G), Sigma1(E)), WK), H), D);
     auto FNext = E;
     auto GNext = F;
     auto HNext = G;
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index a66a6a357..824fd4d1b 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -2581,7 +2581,7 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
 
   // Update XSTATE_BV region of the XSAVE header
   {
-    OrderedNode *HeaderOffset = _Add(Base, _Constant(512));
+    OrderedNode *HeaderOffset = _Add(OpSize, Base, _Constant(512));
 
     // NOTE: We currently only support the first 3 bits (x87, SSE, and AVX)
     OrderedNode *RequestedFeatures = _Bfe(OpSize, 3, 0, Mask);
@@ -2593,6 +2593,7 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SaveX87State(OpcodeArgs, OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
   // Saves 512bytes to the memory location provided
   // Header changes depending on if REX.W is set or not
   if (Op->Flags & X86Tables::DecodeFlags::FLAG_REX_WIDENING) {
@@ -2614,13 +2615,13 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, OrderedNode *MemBase) {
   }
 
   {
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(2));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(2));
     _StoreMem(GPRClass, 2, MemLocation, ReconstructFSW(), 2);
   }
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(4));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(4));
     auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
     _StoreMem(GPRClass, 2, MemLocation, FTW, 2);
   }
@@ -2671,39 +2672,43 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, OrderedNode *MemBase) {
   // This is implementation dependent
   for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
     OrderedNode *MMReg = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, mm[i]));
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 32));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 32));
 
     _StoreMem(FPRClass, 16, MemLocation, MMReg, 16);
   }
 }
 
 void OpDispatchBuilder::SaveSSEState(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; ++i) {
     OrderedNode *XMMReg = LoadXMMRegister(i);
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 160));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 160));
 
     _StoreMem(FPRClass, 16, MemLocation, XMMReg, 16);
   }
 }
 
 void OpDispatchBuilder::SaveMXCSRState(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
+
   OrderedNode *MXCSR = GetMXCSR();
-  OrderedNode *MXCSRLocation = _Add(MemBase, _Constant(24));
+  OrderedNode *MXCSRLocation = _Add(OpSize, MemBase, _Constant(24));
   _StoreMem(GPRClass, 4, MXCSRLocation, MXCSR, 4);
 
   // Store the mask for all bits.
-  OrderedNode *MXCSRMaskLocation = _Add(MXCSRLocation, _Constant(4));
+  OrderedNode *MXCSRMaskLocation = _Add(OpSize, MXCSRLocation, _Constant(4));
   _StoreMem(GPRClass, 4, MXCSRMaskLocation, _Constant(0xFFFF), 4);
 }
 
 void OpDispatchBuilder::SaveAVXState(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; ++i) {
     OrderedNode *Upper = _VDupElement(32, 16, LoadXMMRegister(i), 1);
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 576));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 576));
 
     _StoreMem(FPRClass, 16, MemLocation, Upper, 16);
   }
@@ -2717,18 +2722,22 @@ OrderedNode *OpDispatchBuilder::GetMXCSR() {
 }
 
 void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
+
   OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1, false);
   Mem = AppendSegmentOffset(Mem, Op->Flags);
 
   RestoreX87State(Mem);
   RestoreSSEState(Mem);
 
-  OrderedNode *MXCSRLocation = _Add(Mem, _Constant(24));
+  OrderedNode *MXCSRLocation = _Add(OpSize, Mem, _Constant(24));
   OrderedNode *MXCSR = _LoadMem(GPRClass, 4, MXCSRLocation, 4);
   RestoreMXCSRState(MXCSR);
 }
 
 void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
+
   const auto XSaveBase = [this, Op] {
     OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1, false);
     return AppendSegmentOffset(Mem, Op->Flags);
@@ -2737,8 +2746,7 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
   // Set up base address for the XSAVE region to restore from, and also read the
   // XSTATE_BV bit flags out of the XSTATE header.
   OrderedNode *Base = XSaveBase();
-  OrderedNode *Mask = _LoadMem(GPRClass, 8, _Add(Base, _Constant(512)), 8);
-  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
+  OrderedNode *Mask = _LoadMem(GPRClass, 8, _Add(OpSize, Base, _Constant(512)), 8);
 
   // If a bit in our XSTATE_BV is set, then we restore from that region of the XSAVE area,
   // otherwise, if not set, then we need to set the relevant data the bit corresponds to
@@ -2790,8 +2798,8 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
   {
     // We need to restore the MXCSR if either SSE or AVX are requested to be saved
     RestoreIfFlagSetOrDefault(1,
-                              [this, Base] {
-                                OrderedNode *MXCSRLocation = _Add(Base, _Constant(24));
+                              [this, Base, OpSize] {
+                                OrderedNode *MXCSRLocation = _Add(OpSize, Base, _Constant(24));
                                 OrderedNode *MXCSR = _LoadMem(GPRClass, 4, MXCSRLocation, 4);
                                 RestoreMXCSRState(MXCSR);
                               },
@@ -2800,35 +2808,38 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::RestoreX87State(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
+
   auto NewFCW = _LoadMem(GPRClass, 2, MemBase, 2);
   _F80LoadFCW(NewFCW);
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
   {
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(2));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(2));
     auto NewFSW = _LoadMem(GPRClass, 2, MemLocation, 2);
     ReconstructX87StateFromFSW(NewFSW);
   }
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(4));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(4));
     auto NewFTW = _LoadMem(GPRClass, 2, MemLocation, 2);
     _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
   }
 
   for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 32));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 32));
     auto MMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     _StoreContext(16, FPRClass, MMReg, offsetof(FEXCore::Core::CPUState, mm[i]));
   }
 }
 
 void OpDispatchBuilder::RestoreSSEState(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; ++i) {
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 160));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 160));
     OrderedNode *XMMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     StoreXMMRegister(i, XMMReg);
   }
@@ -2841,11 +2852,12 @@ void OpDispatchBuilder::RestoreMXCSRState(OrderedNode *MXCSR) {
 }
 
 void OpDispatchBuilder::RestoreAVXState(OrderedNode *MemBase) {
+  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; ++i) {
     OrderedNode *XMMReg = LoadXMMRegister(i);
-    OrderedNode *MemLocation = _Add(MemBase, _Constant(i * 16 + 576));
+    OrderedNode *MemLocation = _Add(OpSize, MemBase, _Constant(i * 16 + 576));
     OrderedNode *YMMHReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     OrderedNode *YMM = _VInsElement(32, 16, 1, 0, XMMReg, YMMHReg);
     StoreXMMRegister(i, YMM);
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
index 89299b25e..d19d9da67 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
@@ -108,7 +108,7 @@ void OpDispatchBuilder::FLD(OpcodeArgs) {
   else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    data = _And(OpSize::i64Bit, _Add(orig_top, offset), mask);
+    data = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, offset), mask);
     data = _LoadContextIndexed(data, 16, MMBaseOffset(), 16, FPRClass);
   }
   OrderedNode *converted = data;
@@ -157,7 +157,7 @@ void OpDispatchBuilder::FBSTP(OpcodeArgs) {
 
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 }
 
@@ -248,7 +248,7 @@ void OpDispatchBuilder::FST(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(orig_top, X87Tag::Empty);
     // Set the new top now
-    auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+    auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
 }
@@ -274,7 +274,7 @@ void OpDispatchBuilder::FIST(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(orig_top, X87Tag::Empty);
     // Set the new top now
-    auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+    auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
 }
@@ -309,7 +309,7 @@ void OpDispatchBuilder::FADD(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -323,7 +323,7 @@ void OpDispatchBuilder::FADD(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -370,7 +370,7 @@ void OpDispatchBuilder::FMUL(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -386,7 +386,7 @@ void OpDispatchBuilder::FMUL(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -433,7 +433,7 @@ void OpDispatchBuilder::FDIV(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -455,7 +455,7 @@ void OpDispatchBuilder::FDIV(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -518,7 +518,7 @@ void OpDispatchBuilder::FSUB(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -540,7 +540,7 @@ void OpDispatchBuilder::FSUB(OpcodeArgs) {
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
 
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -700,7 +700,7 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
   }
 
@@ -736,17 +736,17 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) {
   if constexpr (poptwice) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
   else if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 }
@@ -779,7 +779,7 @@ void OpDispatchBuilder::FXCH(OpcodeArgs) {
 
   // Implicit arg
   auto offset = _Constant(Op->OP & 7);
-  arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+  arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
 
   auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
   auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
@@ -797,7 +797,7 @@ void OpDispatchBuilder::FST(OpcodeArgs) {
 
   // Implicit arg
   auto offset = _Constant(Op->OP & 7);
-  arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+  arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
 
   auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
 
@@ -807,7 +807,7 @@ void OpDispatchBuilder::FST(OpcodeArgs) {
   if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), _Constant(7));
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
 }
@@ -845,7 +845,7 @@ void OpDispatchBuilder::X87BinaryOp(OpcodeArgs) {
   auto top = GetX87Top();
 
   auto mask = _Constant(7);
-  OrderedNode *st1 = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+  OrderedNode *st1 = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
 
   auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
   st1 = _LoadContextIndexed(st1, 16, MMBaseOffset(), 16, FPRClass);
@@ -875,7 +875,7 @@ template<bool Inc>
 void OpDispatchBuilder::X87ModifySTP(OpcodeArgs) {
   auto orig_top = GetX87Top();
   if (Inc) {
-    auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+    auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
   else {
@@ -914,7 +914,7 @@ void OpDispatchBuilder::X87FYL2X(OpcodeArgs) {
   auto orig_top = GetX87Top();
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 
   OrderedNode *st0 = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
@@ -961,7 +961,7 @@ void OpDispatchBuilder::X87ATAN(OpcodeArgs) {
   auto orig_top = GetX87Top();
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 
   auto a = _LoadContextIndexed(orig_top, 16, MMBaseOffset(), 16, FPRClass);
@@ -982,13 +982,13 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) {
   _F80LoadFCW(NewFCW);
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
-  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+  OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
   auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
   ReconstructX87StateFromFSW(NewFSW);
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
     _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
   }
@@ -1024,7 +1024,7 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) {
   }
 
   {
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
     _StoreMem(GPRClass, Size, MemLocation, ReconstructFSW(), Size);
   }
 
@@ -1032,32 +1032,32 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) {
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
     _StoreMem(GPRClass, Size, MemLocation, FTW, Size);
   }
 
   {
     // Instruction Offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 3));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 3));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Instruction CS selector (+ Opcode)
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 4));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 4));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 5));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 5));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer selector
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 6));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 6));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 }
@@ -1114,7 +1114,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
   }
 
   {
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
     _StoreMem(GPRClass, Size, MemLocation, ReconstructFSW(), Size);
   }
 
@@ -1122,36 +1122,36 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
     _StoreMem(GPRClass, Size, MemLocation, FTW, Size);
   }
 
   {
     // Instruction Offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 3));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 3));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Instruction CS selector (+ Opcode)
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 4));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 4));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 5));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 5));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer selector
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 6));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 6));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
-  OrderedNode *ST0Location = _Add(Mem, _Constant(Size * 7));
+  OrderedNode *ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7));
 
   auto OneConst = _Constant(1);
   auto SevenConst = _Constant(7);
@@ -1159,8 +1159,8 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
   for (int i = 0; i < 7; ++i) {
     auto data = _LoadContextIndexed(Top, 16, MMBaseOffset(), 16, FPRClass);
     _StoreMem(FPRClass, 16, ST0Location, data, 1);
-    ST0Location = _Add(ST0Location, TenConst);
-    Top = _And(OpSize::i64Bit, _Add(Top, OneConst), SevenConst);
+    ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst);
+    Top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -1169,7 +1169,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) {
   // Lower 64bits [63:0]
   // upper 16 bits [79:64]
   _StoreMem(FPRClass, 8, ST0Location, data, 1);
-  ST0Location = _Add(ST0Location, _Constant(8));
+  ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8));
   auto topBytes = _VDupElement(16, 2, data, 4);
   _StoreMem(FPRClass, 2, ST0Location, topBytes, 1);
 
@@ -1186,17 +1186,17 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
   _F80LoadFCW(NewFCW);
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
-  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+  OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
   auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
   auto Top = ReconstructX87StateFromFSW(NewFSW);
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
     _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
   }
 
-  OrderedNode *ST0Location = _Add(Mem, _Constant(Size * 7));
+  OrderedNode *ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7));
 
   auto OneConst = _Constant(1);
   auto SevenConst = _Constant(7);
@@ -1214,8 +1214,8 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
 
     _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass);
 
-    ST0Location = _Add(ST0Location, TenConst);
-    Top = _And(OpSize::i64Bit, _Add(Top, OneConst), SevenConst);
+    ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst);
+    Top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -1224,7 +1224,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
   // upper 16 bits [79:64]
 
   OrderedNode *Reg = _LoadMem(FPRClass, 8, ST0Location, 1);
-  ST0Location = _Add(ST0Location, _Constant(8));
+  ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8));
   OrderedNode *RegHigh = _LoadMem(FPRClass, 2, ST0Location, 1);
   Reg = _VInsElement(16, 2, 4, 0, Reg, RegHigh);
   _StoreContextIndexed(Reg, Top, 16, MMBaseOffset(), 16, FPRClass);
@@ -1338,7 +1338,7 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
 
   // Implicit arg
   auto offset = _Constant(Op->OP & 7);
-  arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+  arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
 
   auto a = _LoadContextIndexed(top, 16, MMBaseOffset(), 16, FPRClass);
   auto b = _LoadContextIndexed(arg, 16, MMBaseOffset(), 16, FPRClass);
@@ -1359,7 +1359,7 @@ void OpDispatchBuilder::X87FFREE(OpcodeArgs) {
 
   // Implicit arg
   auto offset = _Constant(Op->OP & 7);
-  top = _And(OpSize::i64Bit, _Add(top, offset), _Constant(7));
+  top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), _Constant(7));
 
   // Set this argument's tag as empty now
   SetX87TopTag(top, X87Tag::Empty);
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
index fe8aedf12..c03241a78 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
@@ -79,13 +79,13 @@ void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) {
 
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
-  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+  OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
   auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
   ReconstructX87StateFromFSW(NewFSW);
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
     _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
   }
@@ -134,7 +134,7 @@ void OpDispatchBuilder::FLDF64(OpcodeArgs) {
   else {
     // Implicit arg (does this need to change with width?)
     auto offset = _Constant(Op->OP & 7);
-    data = _And(OpSize::i64Bit, _Add(orig_top, offset), mask);
+    data = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, offset), mask);
     data = _LoadContextIndexed(data, 8, MMBaseOffset(), 16, FPRClass);
     converted = data;
   }
@@ -179,7 +179,7 @@ void OpDispatchBuilder::FBSTPF64(OpcodeArgs) {
 
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 }
 
@@ -249,7 +249,7 @@ void OpDispatchBuilder::FSTF64(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(orig_top, X87Tag::Empty);
     // Set the new top now
-    auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+    auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
 }
@@ -278,7 +278,7 @@ void OpDispatchBuilder::FISTF64(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(orig_top, X87Tag::Empty);
     // Set the new top now
-    auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+    auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
     SetX87Top(top);
   }
 }
@@ -315,7 +315,7 @@ void OpDispatchBuilder::FADDF64(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -328,7 +328,7 @@ void OpDispatchBuilder::FADDF64(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -376,7 +376,7 @@ void OpDispatchBuilder::FMULF64(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -392,7 +392,7 @@ void OpDispatchBuilder::FMULF64(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -440,7 +440,7 @@ void OpDispatchBuilder::FDIVF64(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -462,7 +462,7 @@ void OpDispatchBuilder::FDIVF64(OpcodeArgs) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -526,7 +526,7 @@ void OpDispatchBuilder::FSUBF64(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     if constexpr (ResInST0 == OpResult::RES_STI) {
       StackLocation = arg;
     }
@@ -549,7 +549,7 @@ void OpDispatchBuilder::FSUBF64(OpcodeArgs) {
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
 
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 
@@ -688,7 +688,7 @@ void OpDispatchBuilder::FCOMIF64(OpcodeArgs) {
   } else {
     // Implicit arg
     auto offset = _Constant(Op->OP & 7);
-    arg = _And(OpSize::i64Bit, _Add(top, offset), mask);
+    arg = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, offset), mask);
     b = _LoadContextIndexed(arg, 8, MMBaseOffset(), 16, FPRClass);
   }
 
@@ -725,17 +725,17 @@ void OpDispatchBuilder::FCOMIF64(OpcodeArgs) {
   if constexpr (poptwice) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
   else if ((Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) != 0) {
     // if we are popping then we must first mark this location as empty
     SetX87TopTag(top, X87Tag::Empty);
     // Set the new top now
-    top = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+    top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
     SetX87Top(top);
   }
 }
@@ -803,7 +803,7 @@ void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs) {
   auto top = GetX87Top();
 
   auto mask = _Constant(7);
-  OrderedNode *st1 = _And(OpSize::i64Bit, _Add(top, _Constant(1)), mask);
+  OrderedNode *st1 = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, top, _Constant(1)), mask);
 
   auto a = _LoadContextIndexed(top, 8, MMBaseOffset(), 16, FPRClass);
   st1 = _LoadContextIndexed(st1, 8, MMBaseOffset(), 16, FPRClass);
@@ -854,7 +854,7 @@ void OpDispatchBuilder::X87FYL2XF64(OpcodeArgs) {
   auto orig_top = GetX87Top();
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 
   OrderedNode *st0 = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass);
@@ -895,7 +895,7 @@ void OpDispatchBuilder::X87ATANF64(OpcodeArgs) {
   auto orig_top = GetX87Top();
   // if we are popping then we must first mark this location as empty
   SetX87TopTag(orig_top, X87Tag::Empty);
-  auto top = _And(OpSize::i64Bit, _Add(orig_top, _Constant(1)), _Constant(7));
+  auto top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, orig_top, _Constant(1)), _Constant(7));
   SetX87Top(top);
 
   auto a = _LoadContextIndexed(orig_top, 8, MMBaseOffset(), 16, FPRClass);
@@ -940,7 +940,7 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) {
   }
 
   {
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
     _StoreMem(GPRClass, Size, MemLocation, ReconstructFSW(), Size);
   }
 
@@ -948,36 +948,36 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) {
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto FTW = _LoadContext(2, GPRClass, offsetof(FEXCore::Core::CPUState, FTW));
     _StoreMem(GPRClass, Size, MemLocation, FTW, Size);
   }
 
   {
     // Instruction Offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 3));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 3));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Instruction CS selector (+ Opcode)
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 4));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 4));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer offset
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 5));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 5));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
   {
     // Data pointer selector
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 6));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 6));
     _StoreMem(GPRClass, Size, MemLocation, ZeroConst, Size);
   }
 
-  OrderedNode *ST0Location = _Add(Mem, _Constant(Size * 7));
+  OrderedNode *ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7));
 
   auto OneConst = _Constant(1);
   auto SevenConst = _Constant(7);
@@ -986,8 +986,8 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) {
     OrderedNode* data = _LoadContextIndexed(Top, 8, MMBaseOffset(), 16, FPRClass);
     data = _F80CVTTo(data, 8);
     _StoreMem(FPRClass, 16, ST0Location, data, 1);
-    ST0Location = _Add(ST0Location, TenConst);
-    Top = _And(OpSize::i64Bit, _Add(Top, OneConst), SevenConst);
+    ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst);
+    Top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -997,7 +997,7 @@ void OpDispatchBuilder::X87FNSAVEF64(OpcodeArgs) {
   // Lower 64bits [63:0]
   // upper 16 bits [79:64]
   _StoreMem(FPRClass, 8, ST0Location, data, 1);
-  ST0Location = _Add(ST0Location, _Constant(8));
+  ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8));
   auto topBytes = _VDupElement(16, 2, data, 4);
   _StoreMem(FPRClass, 2, ST0Location, topBytes, 1);
 
@@ -1025,18 +1025,18 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) {
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
-  OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 1));
+  OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1));
   auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size);
   auto Top = ReconstructX87StateFromFSW(NewFSW);
 
   {
     // FTW
-    OrderedNode *MemLocation = _Add(Mem, _Constant(Size * 2));
+    OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 2));
     auto NewFTW = _LoadMem(GPRClass, Size, MemLocation, Size);
     _StoreContext(2, GPRClass, NewFTW, offsetof(FEXCore::Core::CPUState, FTW));
   }
 
-  OrderedNode *ST0Location = _Add(Mem, _Constant(Size * 7));
+  OrderedNode *ST0Location = _Add(OpSize::i64Bit, Mem, _Constant(Size * 7));
 
   auto OneConst = _Constant(1);
   auto SevenConst = _Constant(7);
@@ -1055,8 +1055,8 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) {
     Reg = _F80CVT(8, Reg);
     _StoreContextIndexed(Reg, Top, 8, MMBaseOffset(), 16, FPRClass);
 
-    ST0Location = _Add(ST0Location, TenConst);
-    Top = _And(OpSize::i64Bit, _Add(Top, OneConst), SevenConst);
+    ST0Location = _Add(OpSize::i64Bit, ST0Location, TenConst);
+    Top = _And(OpSize::i64Bit, _Add(OpSize::i64Bit, Top, OneConst), SevenConst);
   }
 
   // The final st(7) needs a bit of special handling here
@@ -1065,7 +1065,7 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) {
   // upper 16 bits [79:64]
 
   OrderedNode *Reg = _LoadMem(FPRClass, 8, ST0Location, 1);
-  ST0Location = _Add(ST0Location, _Constant(8));
+  ST0Location = _Add(OpSize::i64Bit, ST0Location, _Constant(8));
   OrderedNode *RegHigh = _LoadMem(FPRClass, 2, ST0Location, 1);
   Reg = _VInsElement(16, 2, 4, 0, Reg, RegHigh);
   Reg = _F80CVT(8, Reg); //Convert to double precision
diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h
index d5cfc7460..1f411a98c 100644
--- a/FEXCore/include/FEXCore/IR/IREmitter.h
+++ b/FEXCore/include/FEXCore/IR/IREmitter.h
@@ -91,13 +91,6 @@ friend class FEXCore::IR::PassManager;
     return InvalidNode;
   }
 
-  // Temporary naughty implicit IR operation handlers
-  ///< ALU
-  IRPair<IROp_Add> _Add(OrderedNode *_Src1, OrderedNode *_Src2) {
-    return _Add(static_cast<OpSize>(std::max<uint8_t>(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2);
-  }
-  // End of Temporary naughty implicit IR operation handlers
-
   void AddPhiValue(IR::IROp_Phi *Phi, OrderedNode *Value) {
     // Got to do some bookkeeping first
     Value->AddUse();