diff --git a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp index 32613224f..453dc6a8d 100644 --- a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp @@ -588,7 +588,7 @@ DEF_OP(ShiftFlags) { and_(ARMEmitter::Size::i32Bit, TMP1, Src2, OpSize == IR::OpSize::i64Bit ? 0x3f : 0x1f); ARMEmitter::ForwardLabel Done; - cbz(EmitSize, TMP1, &Done); + (void)cbz(EmitSize, TMP1, &Done); { // PF/SF/ZF/OF if (OpSize >= IR::OpSize::i32Bit) { @@ -652,7 +652,7 @@ DEF_OP(ShiftFlags) { msr(ARMEmitter::SystemRegister::NZCV, TMP2); } } - Bind(&Done); + (void)Bind(&Done); // TODO: Make RA less dumb so this can't happen (e.g. with late-kill). if (PFOutput != PFTemp) { @@ -669,7 +669,7 @@ DEF_OP(RotateFlags) { // If shift=0, flags are unaffected. Wrap the whole implementation in a cbz. ARMEmitter::ForwardLabel Done; - cbz(EmitSize, Shift, &Done); + (void)cbz(EmitSize, Shift, &Done); { // Extract the last bit shifted in to CF const auto BitSize = IR::OpSizeToSize(Op->Size) * 8; @@ -701,7 +701,7 @@ DEF_OP(RotateFlags) { msr(ARMEmitter::SystemRegister::NZCV, TMP3); } } - Bind(&Done); + (void)Bind(&Done); } DEF_OP(Extr) { @@ -767,14 +767,14 @@ DEF_OP(PDep) { // Now, they're copied, so we can start setting Dest (even if it overlaps with // one of them). Handle early exit case mov(EmitSize, Dest, 0); - cbz(EmitSize, OrigMask, &Done); + (void)cbz(EmitSize, OrigMask, &Done); // Setup for first iteration neg(EmitSize, T0, Mask); and_(EmitSize, T0, T0, Mask); // Main loop - Bind(&NextBit); + (void)Bind(&NextBit); sbfx(EmitSize, T1, Input, 0, 1); eor(EmitSize, Mask, Mask, T0); and_(EmitSize, T0, T1, T0); @@ -782,10 +782,10 @@ DEF_OP(PDep) { orr(EmitSize, Dest, Dest, T0); lsr(EmitSize, Input, Input, 1); and_(EmitSize, T0, Mask, T1); - cbnz(EmitSize, T0, &NextBit); + (void)cbnz(EmitSize, T0, &NextBit); // All done with nothing to do. - Bind(&Done); + (void)Bind(&Done); } } @@ -821,27 +821,27 @@ DEF_OP(PExt) { ARMEmitter::BackwardLabel NextBit; ARMEmitter::ForwardLabel Done; - cbz(EmitSize, Mask, &EarlyExit); + (void)cbz(EmitSize, Mask, &EarlyExit); mov(EmitSize, MaskReg, Mask); mov(EmitSize, ValueReg, Input); mov(EmitSize, Dest, ARMEmitter::Reg::zr); // Main loop - Bind(&NextBit); - cbz(EmitSize, MaskReg, &Done); + (void)Bind(&NextBit); + (void)cbz(EmitSize, MaskReg, &Done); clz(EmitSize, BitReg, MaskReg); lslv(EmitSize, ValueReg, ValueReg, BitReg); lslv(EmitSize, MaskReg, MaskReg, BitReg); extr(EmitSize, Dest, Dest, ValueReg, OpSizeBitsM1); bfc(EmitSize, MaskReg, OpSizeBitsM1, 1); - b(&NextBit); + (void)b(&NextBit); // Early exit - Bind(&EarlyExit); + (void)Bind(&EarlyExit); mov(EmitSize, Dest, ARMEmitter::Reg::zr); // All done with nothing to do. - Bind(&Done); + (void)Bind(&Done); } } @@ -909,7 +909,7 @@ DEF_OP(Div) { eor(EmitSize, TMP1, TMP1, Upper); // If the sign bit matches then the result is zero - cbz(EmitSize, TMP1, &Only64Bit); + (void)cbz(EmitSize, TMP1, &Only64Bit); // Long divide { @@ -928,17 +928,17 @@ DEF_OP(Div) { mov(EmitSize, Remainder, TMP2); // Skip 64-bit path - b(&LongDIVRet); + (void)b(&LongDIVRet); } - Bind(&Only64Bit); + (void)Bind(&Only64Bit); // 64-Bit only { sdiv(EmitSize, Quotient, Lower, Divisor); msub(EmitSize, Remainder, Quotient, Divisor, Lower); } - Bind(&LongDIVRet); + (void)Bind(&LongDIVRet); break; } default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", OpSize); break; @@ -992,7 +992,7 @@ DEF_OP(UDiv) { // Check the upper bits for zero // If the upper bits are zero then we can do a 64-bit divide - cbz(EmitSize, Upper, &Only64Bit); + (void)cbz(EmitSize, Upper, &Only64Bit); // Long divide { @@ -1011,17 +1011,17 @@ DEF_OP(UDiv) { mov(EmitSize, Remainder, TMP2); // Skip 64-bit path - b(&LongDIVRet); + (void)b(&LongDIVRet); } - Bind(&Only64Bit); + (void)Bind(&Only64Bit); // 64-Bit only { udiv(EmitSize, Quotient, Lower, Divisor); msub(EmitSize, Remainder, Quotient, Divisor, Lower); } - Bind(&LongDIVRet); + (void)Bind(&LongDIVRet); break; } default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", OpSize); break; diff --git a/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp index 8612493c5..51ea83ec1 100644 --- a/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp @@ -62,27 +62,27 @@ DEF_OP(CASPair) { ARMEmitter::BackwardLabel LoopTop; ARMEmitter::ForwardLabel LoopNotExpected; ARMEmitter::ForwardLabel LoopExpected; - Bind(&LoopTop); + (void)Bind(&LoopTop); // This instruction sequence must be synced with HandleCASPAL_Armv8. ldaxp(EmitSize, TMP2, TMP3, MemSrc); cmp(EmitSize, TMP2, Expected0); ccmp(EmitSize, TMP3, Expected1, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ); - b(ARMEmitter::Condition::CC_NE, &LoopNotExpected); + (void)b(ARMEmitter::Condition::CC_NE, &LoopNotExpected); stlxp(EmitSize, TMP2, Desired0, Desired1, MemSrc); - cbnz(EmitSize, TMP2, &LoopTop); + (void)cbnz(EmitSize, TMP2, &LoopTop); mov(EmitSize, Dst0, Expected0); mov(EmitSize, Dst1, Expected1); - b(&LoopExpected); + (void)b(&LoopExpected); - Bind(&LoopNotExpected); + (void)Bind(&LoopNotExpected); mov(EmitSize, Dst0, TMP2.R()); mov(EmitSize, Dst1, TMP3.R()); // exclusive monitor needs to be cleared here // Might have hit the case where ldaxr was hit but stlxr wasn't clrex(); - Bind(&LoopExpected); + (void)Bind(&LoopExpected); // Restore msr(ARMEmitter::SystemRegister::NZCV, TMP1); @@ -114,7 +114,7 @@ DEF_OP(CAS) { ARMEmitter::BackwardLabel LoopTop; ARMEmitter::ForwardLabel LoopNotExpected; ARMEmitter::ForwardLabel LoopExpected; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); if (IROp->Size == IR::OpSize::i8Bit) { cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTB, 0); @@ -123,18 +123,18 @@ DEF_OP(CAS) { } else { cmp(EmitSize, TMP2, Expected); } - b(ARMEmitter::Condition::CC_NE, &LoopNotExpected); + (void)b(ARMEmitter::Condition::CC_NE, &LoopNotExpected); stlxr(SubEmitSize, TMP3, Desired, MemSrc); - cbnz(EmitSize, TMP3, &LoopTop); + (void)cbnz(EmitSize, TMP3, &LoopTop); mov(EmitSize, Dst, Expected); - b(&LoopExpected); + (void)b(&LoopExpected); - Bind(&LoopNotExpected); + (void)Bind(&LoopNotExpected); mov(EmitSize, Dst, TMP2.R()); // exclusive monitor needs to be cleared here // Might have hit the case where ldaxr was hit but stlxr wasn't clrex(); - Bind(&LoopExpected); + (void)Bind(&LoopExpected); } } @@ -150,11 +150,11 @@ DEF_OP(AtomicXor) { steorl(SubEmitSize, Src, MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); eor(EmitSize, TMP2, TMP2, Src); stlxr(SubEmitSize, TMP2, TMP2, MemSrc); - cbnz(EmitSize, TMP2, &LoopTop); + (void)cbnz(EmitSize, TMP2, &LoopTop); } } @@ -179,10 +179,10 @@ DEF_OP(AtomicSwap) { ldswpal(SubEmitSize, Src, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); stlxr(SubEmitSize, TMP4, Src, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); ubfm(EmitSize, GetReg(Node), TMP2, 0, IR::OpSizeAsBits(OpSize) - 1); } } @@ -199,11 +199,11 @@ DEF_OP(AtomicFetchAdd) { ldaddal(SubEmitSize, Src, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); add(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -221,11 +221,11 @@ DEF_OP(AtomicFetchSub) { ldaddal(SubEmitSize, TMP2, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); sub(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -243,11 +243,11 @@ DEF_OP(AtomicFetchAnd) { ldclral(SubEmitSize, TMP2, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); and_(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -264,11 +264,11 @@ DEF_OP(AtomicFetchCLR) { ldclral(SubEmitSize, Src, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); bic(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -285,11 +285,11 @@ DEF_OP(AtomicFetchOr) { ldsetal(SubEmitSize, Src, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); orr(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -306,11 +306,11 @@ DEF_OP(AtomicFetchXor) { ldeoral(SubEmitSize, Src, GetReg(Node), MemSrc); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); eor(EmitSize, TMP3, TMP2, Src); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -326,20 +326,20 @@ DEF_OP(AtomicFetchNeg) { // Use a CAS loop to avoid needing to emulate unaligned LLSC atomics ldr(SubEmitSize, TMP2, MemSrc); ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); mov(EmitSize, TMP4, TMP2); neg(EmitSize, TMP3, TMP2); casal(SubEmitSize, TMP2, TMP3, MemSrc); sub(EmitSize, TMP3, TMP2, TMP4); - cbnz(EmitSize, TMP3, &LoopTop); + (void)cbnz(EmitSize, TMP3, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(SubEmitSize, TMP2, MemSrc); neg(EmitSize, TMP3, TMP2); stlxr(SubEmitSize, TMP4, TMP3, MemSrc); - cbnz(EmitSize, TMP4, &LoopTop); + (void)cbnz(EmitSize, TMP4, &LoopTop); mov(EmitSize, GetReg(Node), TMP2.R()); } } @@ -359,11 +359,11 @@ DEF_OP(TelemetrySetValue) { stsetl(ARMEmitter::SubRegSize::i64Bit, TMP1, TMP2); } else { ARMEmitter::BackwardLabel LoopTop; - Bind(&LoopTop); + (void)Bind(&LoopTop); ldaxr(ARMEmitter::SubRegSize::i64Bit, TMP3, TMP2); orr(ARMEmitter::Size::i32Bit, TMP3, TMP3, Src); stlxr(ARMEmitter::SubRegSize::i64Bit, TMP3, TMP3, TMP2); - cbnz(ARMEmitter::Size::i32Bit, TMP3, &LoopTop); + (void)cbnz(ARMEmitter::Size::i32Bit, TMP3, &LoopTop); } #endif } diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp index fc2121367..e5534734b 100644 --- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp @@ -141,7 +141,7 @@ DEF_OP(ExitFunction) { if (!Op->CallReturnBlock.IsInvalid()) { auto CallReturnAddressReg = GetReg(Op->CallReturnAddress).X(); PendingCallReturnTargetLabel = &CallReturnTargets.try_emplace(Op->CallReturnBlock.ID()).first->second; - adr(TMP1, &l_CallReturn); + (void)adr(TMP1, &l_CallReturn); stp(CallReturnAddressReg, TMP1, REG_CALLRET_SP, -0x10); } else { stp(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10); @@ -149,16 +149,16 @@ DEF_OP(ExitFunction) { } else if (Op->Hint == IR::BranchHint::CheckTF) { ARMEmitter::ForwardLabel TFUnset; ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); - cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset); + (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset); LoadConstant(ARMEmitter::Size::i64Bit, TMP1, NewRIP); str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)); blr(TMP2); - Bind(&TFUnset); + (void)Bind(&TFUnset); } EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call); - Bind(&l_CallReturn); + (void)Bind(&l_CallReturn); #ifdef _M_ARM_64EC } #endif @@ -170,7 +170,7 @@ DEF_OP(ExitFunction) { // First try to pop from the call-ret stack, otherwise follow the normal path (but ending in a ret) ldp(TMP1, TMP2, REG_CALLRET_SP, 0x10); sub(TMP1, TMP1, RipReg.X()); - cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup); } // L1 Cache @@ -185,23 +185,23 @@ DEF_OP(ExitFunction) { // Note: sub+cbnz used over cmp+br to preserve flags. sub(TMP1, TMP1, RipReg.X()); - cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup); ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)); str(RipReg.X(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); - Bind(&SkipFullLookup); + (void)Bind(&SkipFullLookup); if (Op->Hint == IR::BranchHint::Call) { ARMEmitter::ForwardLabel l_CallReturn; if (!Op->CallReturnBlock.IsInvalid()) { auto CallReturnAddressReg = GetReg(Op->CallReturnAddress).X(); PendingCallReturnTargetLabel = &CallReturnTargets.try_emplace(Op->CallReturnBlock.ID()).first->second; - adr(TMP1, &l_CallReturn); + (void)adr(TMP1, &l_CallReturn); stp(CallReturnAddressReg, TMP1, REG_CALLRET_SP, -0x10); } else { stp(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10); } blr(TMP2); - Bind(&l_CallReturn); + (void)Bind(&l_CallReturn); } else if (Op->Hint == IR::BranchHint::Return) { ret(TMP2); } else { diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp index 73f5ebb6c..1adf7cf8b 100644 --- a/FEXCore/Source/Interface/Core/JIT/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp @@ -11,8 +11,6 @@ desc: Main glue logic of the arm64 splatter backend $end_info$ */ -#include "Common/SoftFloat.h" - #include "Interface/Context/Context.h" #include "Interface/Core/LookupCache.h" #include "Interface/Core/Dispatcher/Dispatcher.h" @@ -37,7 +35,6 @@ $end_info$ #include #include -#include #include namespace { @@ -742,11 +739,11 @@ void Arm64JITCore::EmitTFCheck() { // Note that this needs to be before the below suspend checks, as X86 checks this flag immediately after executing an instruction. ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); - cbz(ARMEmitter::Size::i32Bit, TMP1, &l_TFUnset); + (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &l_TFUnset); // X86 semantically checks TF after executing each instruction, so e.g. setting a context with TF set will execute a single instruction // and then raise an exception. However on the FEX side this is simpler to implement by checking at the start of each instruction, handle this by having bit 1 being unset in the flag state indicate that TF is blocked for a single instruction. - tbz(TMP1, 1, &l_TFBlocked); + (void)tbz(TMP1, 1, &l_TFBlocked); // Block TF for a single instruction when the frontend jumps to a new context by unsetting bit 1. ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); @@ -769,11 +766,11 @@ void Arm64JITCore::EmitTFCheck() { ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)); br(TMP1); - Bind(&l_TFBlocked); + (void)Bind(&l_TFBlocked); // If TF was blocked for this instruction, unblock it for the next. LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 0b11); strb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); - Bind(&l_TFUnset); + (void)Bind(&l_TFUnset); } void Arm64JITCore::EmitSuspendInterruptCheck() { @@ -844,7 +841,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size // Put the code header at the start of the data block. ARMEmitter::BackwardLabel JITCodeHeaderLabel {}; - Bind(&JITCodeHeaderLabel); + (void)Bind(&JITCodeHeaderLabel); JITCodeHeader* CodeHeader = GetCursorAddress(); CursorIncrement(sizeof(JITCodeHeader)); diff --git a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp index 6ed72349d..17861a03f 100644 --- a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp @@ -912,7 +912,7 @@ DEF_OP(VLoadVectorMasked) { // If the sign bit is zero then skip the load ARMEmitter::ForwardLabel Skip {}; - tbz(WorkingReg, ElementSizeInBits - 1, &Skip); + (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip); // Do the gather load for this element into the destination switch (IROp->ElementSize) { case IR::OpSize::i8Bit: ld1(TempDst.Q(), i, TempMemReg); break; @@ -923,7 +923,7 @@ DEF_OP(VLoadVectorMasked) { default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, IROp->ElementSize); return; } - Bind(&Skip); + (void)Bind(&Skip); if ((i + 1) != NumElements) { // Handle register rename to save a move. @@ -1013,7 +1013,7 @@ DEF_OP(VStoreVectorMasked) { // If the sign bit is zero then skip the load ARMEmitter::ForwardLabel Skip {}; - tbz(WorkingReg, ElementSizeInBits - 1, &Skip); + (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip); // Do the gather load for this element into the destination switch (IROp->ElementSize) { case IR::OpSize::i8Bit: st1(RegData.Q(), i, TempMemReg); break; @@ -1024,7 +1024,7 @@ DEF_OP(VStoreVectorMasked) { default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, IROp->ElementSize); return; } - Bind(&Skip); + (void)Bind(&Skip); if ((i + 1) != NumElements) { // Handle register rename to save a move. @@ -1102,7 +1102,7 @@ void Arm64JITCore::Emulate128BitGather(IR::OpSize Size, IR::OpSize ElementSize, PerformMove(ElementSize, WorkingReg, MaskReg, i); // Skip if the mask's sign bit isn't set - tbz(WorkingReg, ElementSizeInBits - 1, &Skip); + (void)tbz(WorkingReg, ElementSizeInBits - 1, &Skip); // Extract Index Element if ((IndexElement * IR::OpSizeToSize(VectorIndexSize)) >= 16) { @@ -1140,7 +1140,7 @@ void Arm64JITCore::Emulate128BitGather(IR::OpSize Size, IR::OpSize ElementSize, default: LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, ElementSize); FEX_UNREACHABLE; } - Bind(&Skip); + (void)Bind(&Skip); } if (NeedsDestTmp) { @@ -1874,7 +1874,7 @@ DEF_OP(MemSet) { if (!DirectionIsInline) { // Backward or forwards implementation depends on flag - tbnz(DirectionReg, 1, &BackwardImpl); + (void)tbnz(DirectionReg, 1, &BackwardImpl); } auto MemStore = [this](auto Value, uint32_t OpSize, int32_t Size) { @@ -1922,7 +1922,7 @@ DEF_OP(MemSet) { ARMEmitter::ForwardLabel DoneInternal {}; // Early exit if zero count. - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); if (!IsAtomic) { ARMEmitter::ForwardLabel AgainInternal256Exit {}; @@ -1939,50 +1939,50 @@ DEF_OP(MemSet) { // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the // single copy loop if size < 64. sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal128Exit); + (void)tbnz(TMP1, 63, &AgainInternal128Exit); // Fill VTMP2 with the set pattern dup(SubRegSize, VTMP2.Q(), Value); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal256Exit); + (void)tbnz(TMP1, 63, &AgainInternal256Exit); - Bind(&AgainInternal256); + (void)Bind(&AgainInternal256); stp(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction); stp(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size); - tbz(TMP1, 63, &AgainInternal256); + (void)tbz(TMP1, 63, &AgainInternal256); - Bind(&AgainInternal256Exit); + (void)Bind(&AgainInternal256Exit); add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size); - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal128Exit); - Bind(&AgainInternal128); + (void)tbnz(TMP1, 63, &AgainInternal128Exit); + (void)Bind(&AgainInternal128); stp(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbz(TMP1, 63, &AgainInternal128); + (void)tbz(TMP1, 63, &AgainInternal128); - Bind(&AgainInternal128Exit); + (void)Bind(&AgainInternal128Exit); add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); if (Direction == -1) { add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size); } } - Bind(&AgainInternal); + (void)Bind(&AgainInternal); if (IsAtomic) { MemStoreTSO(Value, OpSize, SizeDirection); } else { MemStore(Value, OpSize, SizeDirection); } sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1); - cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal); + (void)cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal); - Bind(&DoneInternal); + (void)Bind(&DoneInternal); if (SizeDirection >= 0) { switch (OpSize) { @@ -2012,12 +2012,12 @@ DEF_OP(MemSet) { EmitMemset(Direction); if (Direction == 1) { - b(&Done); - Bind(&BackwardImpl); + (void)b(&Done); + (void)Bind(&BackwardImpl); } } - Bind(&Done); + (void)Bind(&Done); // Destination already set to the final pointer. } } @@ -2067,7 +2067,7 @@ DEF_OP(MemCpy) { if (!DirectionIsInline) { // Backward or forwards implementation depends on flag - tbnz(DirectionReg, 1, &BackwardImpl); + (void)tbnz(DirectionReg, 1, &BackwardImpl); } auto MemCpy = [this](uint32_t OpSize, int32_t Size) { @@ -2164,7 +2164,7 @@ DEF_OP(MemCpy) { ARMEmitter::ForwardLabel DoneInternal {}; // Early exit if zero count. - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); if (!IsAtomic) { ARMEmitter::ForwardLabel AbsPos {}; @@ -2174,11 +2174,11 @@ DEF_OP(MemCpy) { ARMEmitter::BackwardLabel AgainInternal256 {}; sub(ARMEmitter::Size::i64Bit, TMP4, TMP2, TMP3); - tbz(TMP4, 63, &AbsPos); + (void)tbz(TMP4, 63, &AbsPos); neg(ARMEmitter::Size::i64Bit, TMP4, TMP4); - Bind(&AbsPos); + (void)Bind(&AbsPos); sub(ARMEmitter::Size::i64Bit, TMP4, TMP4, 32); - tbnz(TMP4, 63, &AgainInternal); + (void)tbnz(TMP4, 63, &AgainInternal); if (Direction == -1) { sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size); @@ -2190,30 +2190,30 @@ DEF_OP(MemCpy) { // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the // single copy loop if size < 64. sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal128Exit); + (void)tbnz(TMP1, 63, &AgainInternal128Exit); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal256Exit); + (void)tbnz(TMP1, 63, &AgainInternal256Exit); - Bind(&AgainInternal256); + (void)Bind(&AgainInternal256); MemCpy(32, 32 * Direction); MemCpy(32, 32 * Direction); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size); - tbz(TMP1, 63, &AgainInternal256); + (void)tbz(TMP1, 63, &AgainInternal256); - Bind(&AgainInternal256Exit); + (void)Bind(&AgainInternal256Exit); add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size); - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbnz(TMP1, 63, &AgainInternal128Exit); - Bind(&AgainInternal128); + (void)tbnz(TMP1, 63, &AgainInternal128Exit); + (void)Bind(&AgainInternal128); MemCpy(32, 32 * Direction); sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - tbz(TMP1, 63, &AgainInternal128); + (void)tbz(TMP1, 63, &AgainInternal128); - Bind(&AgainInternal128Exit); + (void)Bind(&AgainInternal128Exit); add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size); - cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); + (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal); if (Direction == -1) { add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size); @@ -2221,16 +2221,16 @@ DEF_OP(MemCpy) { } } - Bind(&AgainInternal); + (void)Bind(&AgainInternal); if (IsAtomic) { MemCpyTSO(OpSize, SizeDirection); } else { MemCpy(OpSize, SizeDirection); } sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1); - cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal); + (void)cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal); - Bind(&DoneInternal); + (void)Bind(&DoneInternal); // Needs to use temporaries just in case of overwrite mov(TMP1, MemRegDest.X()); @@ -2288,11 +2288,11 @@ DEF_OP(MemCpy) { for (int32_t Direction : {1, -1}) { EmitMemcpy(Direction); if (Direction == 1) { - b(&Done); - Bind(&BackwardImpl); + (void)b(&Done); + (void)Bind(&BackwardImpl); } } - Bind(&Done); + (void)Bind(&Done); // Destination already set to the final pointer. } }