diff --git a/Source/Interface/Core/Interpreter/InterpreterCore.cpp b/Source/Interface/Core/Interpreter/InterpreterCore.cpp index 6b524cbfd..ecb18d533 100644 --- a/Source/Interface/Core/Interpreter/InterpreterCore.cpp +++ b/Source/Interface/Core/Interpreter/InterpreterCore.cpp @@ -1952,6 +1952,44 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) { } \ break; \ } + case IR::OP_VUSHRI: { + auto Op = IROp->C(); + void *Src = GetSrc(Op->Header.Args[0]); + uint8_t BitShift = Op->BitShift; + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + + auto Func = [BitShift](auto a) { return a >> BitShift; }; + switch (Op->ElementSize) { + DO_VECTOR_1SRC_OP(1, uint8_t, Func) + DO_VECTOR_1SRC_OP(2, uint16_t, Func) + DO_VECTOR_1SRC_OP(4, uint32_t, Func) + DO_VECTOR_1SRC_OP(8, uint64_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } + case IR::OP_VSSHRI: { + auto Op = IROp->C(); + void *Src = GetSrc(Op->Header.Args[0]); + uint8_t BitShift = Op->BitShift; + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + + auto Func = [BitShift](auto a) { return a >> BitShift; }; + switch (Op->ElementSize) { + DO_VECTOR_1SRC_OP(1, int8_t, Func) + DO_VECTOR_1SRC_OP(2, int16_t, Func) + DO_VECTOR_1SRC_OP(4, int32_t, Func) + DO_VECTOR_1SRC_OP(8, int64_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } case IR::OP_VADD: { auto Op = IROp->C(); void *Src1 = GetSrc(Op->Header.Args[0]); @@ -2159,6 +2197,16 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) { } \ break; \ } + #define DO_VECTOR_2SRC_2TYPE_OP(size, type, type2, func) \ + case size: { \ + auto *Dst_d = reinterpret_cast(Tmp); \ + auto *Src1_d = reinterpret_cast(Src1); \ + auto *Src2_d = reinterpret_cast(Src2); \ + for (uint8_t i = 0; i < Elements; ++i) { \ + Dst_d[i] = (type)func((type)Src1_d[i], (type)Src2_d[i]); \ + } \ + break; \ + } case IR::OP_VSQXTUN: { auto Op = IROp->C(); @@ -2225,6 +2273,44 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) { memcpy(GDP, Tmp, Op->RegisterSize); break; } + case IR::OP_VUMULL: { + auto Op = IROp->C(); + void *Src1 = GetSrc(Op->Header.Args[0]); + void *Src2 = GetSrc(Op->Header.Args[1]); + + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + + auto Func = [](auto a, auto b) { return a * b; }; + switch (Op->ElementSize) { + DO_VECTOR_2SRC_2TYPE_OP(1, uint16_t, uint8_t, Func) + DO_VECTOR_2SRC_2TYPE_OP(2, uint32_t, uint16_t, Func) + DO_VECTOR_2SRC_2TYPE_OP(4, uint64_t, uint32_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } + case IR::OP_VSMULL: { + auto Op = IROp->C(); + void *Src1 = GetSrc(Op->Header.Args[0]); + void *Src2 = GetSrc(Op->Header.Args[1]); + + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + + auto Func = [](auto a, auto b) { return a * b; }; + switch (Op->ElementSize) { + DO_VECTOR_2SRC_2TYPE_OP(1, int16_t, int8_t, Func) + DO_VECTOR_2SRC_2TYPE_OP(2, int32_t, int16_t, Func) + DO_VECTOR_2SRC_2TYPE_OP(4, int64_t, int32_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } case IR::OP_VFCVTL: { auto Op = IROp->C(); void *Src = GetSrc(Op->Header.Args[0]); @@ -2404,6 +2490,46 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) { memcpy(GDP, Tmp, Op->RegisterSize); break; } + case IR::OP_VUSHRS: { + auto Op = IROp->C(); + void *Src1 = GetSrc(Op->Header.Args[0]); + void *Src2 = GetSrc(Op->Header.Args[1]); + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + auto Func = [](auto a, auto b) { return a >> b; }; + + switch (Op->ElementSize) { + DO_VECTOR_SCALAR_OP(1, uint8_t, Func) + DO_VECTOR_SCALAR_OP(2, uint16_t, Func) + DO_VECTOR_SCALAR_OP(4, uint32_t, Func) + DO_VECTOR_SCALAR_OP(8, uint64_t, Func) + DO_VECTOR_SCALAR_OP(16, __uint128_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } + case IR::OP_VSSHRS: { + auto Op = IROp->C(); + void *Src1 = GetSrc(Op->Header.Args[0]); + void *Src2 = GetSrc(Op->Header.Args[1]); + uint8_t Tmp[16]; + + uint8_t Elements = Op->RegisterSize / Op->ElementSize; + auto Func = [](auto a, auto b) { return a >> b; }; + + switch (Op->ElementSize) { + DO_VECTOR_SCALAR_OP(1, int8_t, Func) + DO_VECTOR_SCALAR_OP(2, int16_t, Func) + DO_VECTOR_SCALAR_OP(4, int32_t, Func) + DO_VECTOR_SCALAR_OP(8, int64_t, Func) + DO_VECTOR_SCALAR_OP(16, __int128_t, Func) + default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break; + } + memcpy(GDP, Tmp, Op->RegisterSize); + break; + } case IR::OP_VUSHR: { auto Op = IROp->C(); void *Src1 = GetSrc(Op->Header.Args[0]); diff --git a/Source/Interface/Core/OpcodeDispatcher.cpp b/Source/Interface/Core/OpcodeDispatcher.cpp index 3038e8350..224d7248b 100644 --- a/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1958,10 +1958,12 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { OrderedNode *Counter = _LoadContext(8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass); // Can we end the block? - auto CanLeaveCond = _Select(FEXCore::IR::COND_EQ, + OrderedNode *CanLeaveCond = _Select(FEXCore::IR::COND_EQ, Counter, _Constant(0), _Constant(1), _Constant(0)); + auto CondJump = _CondJump(CanLeaveCond); + IRPair InternalCondJump; auto LoopTail = CreateNewCodeBlock(); SetFalseJumpTarget(CondJump, LoopTail); @@ -1999,13 +2001,17 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { Dest_RSI = _Add(Dest_RSI, PtrDir); _StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RSI]), Dest_RSI); - // Jump back to the start, we have more work to do - _Jump(LoopStart); + OrderedNode *ZF = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); + InternalCondJump = _CondJump(ZF); + + // Jump back to the start if we have more work to do + SetTrueJumpTarget(InternalCondJump, LoopStart); } // Make sure to start a new block after ending this one auto LoopEnd = CreateNewCodeBlock(); SetTrueJumpTarget(CondJump, LoopEnd); + SetFalseJumpTarget(InternalCondJump, LoopEnd); SetCurrentCodeBlock(LoopEnd); } @@ -2014,8 +2020,6 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { auto Size = GetSrcSize(Op); - SetRFLAG(_Constant(0)); - auto JumpStart = _Jump(); // Make sure to start a new block after ending this one auto LoopStart = CreateNewCodeBlock(); @@ -2032,11 +2036,9 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { Counter, ZeroConst, OneConst, ZeroConst); - auto ZF = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); - CanLeaveCond = _Or(CanLeaveCond, ZF); - // We leave if RCX = 0 auto CondJump = _CondJump(CanLeaveCond); + IRPair InternalCondJump; auto LoopTail = CreateNewCodeBlock(); SetFalseJumpTarget(CondJump, LoopTail); @@ -2072,11 +2074,17 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { // Offset the pointer TailDest_RDI = _Add(TailDest_RDI, PtrDir); _StoreContext(GPRClass, 8, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDI]), TailDest_RDI); - _Jump(LoopStart); + + OrderedNode *ZF = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); + InternalCondJump = _CondJump(ZF); + + // Jump back to the start if we have more work to do + SetFalseJumpTarget(InternalCondJump, LoopStart); } // Make sure to start a new block after ending this one auto LoopEnd = CreateNewCodeBlock(); SetTrueJumpTarget(CondJump, LoopEnd); + SetTrueJumpTarget(InternalCondJump, LoopEnd); SetCurrentCodeBlock(LoopEnd); } @@ -3830,6 +3838,32 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } +template +void OpDispatchBuilder::PSRAOp(OpcodeArgs) { + LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here"); + + OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); + OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + + auto Size = GetDstSize(Op); + + auto Result = _VSShrS(Size, ElementSize, Dest, Src); + StoreResult(FPRClass, Op, Result, -1); +} + +template +void OpDispatchBuilder::PSRAIOp(OpcodeArgs) { + LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here"); + uint64_t Shift = Op->Src[1].TypeLiteral.Literal; + + OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); + + auto Size = GetDstSize(Op); + + auto Result = _VSShrI(Size, ElementSize, Dest, Shift); + StoreResult(FPRClass, Op, Result, -1); +} + void OpDispatchBuilder::MOVDDUPOp(OpcodeArgs) { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); OrderedNode *Res = _CreateVector2(Src, Src); @@ -4253,6 +4287,36 @@ void OpDispatchBuilder::PACKUSOp(OpcodeArgs) { StoreResult(FPRClass, Op, Res, -1); } +template +void OpDispatchBuilder::PMULOp(OpcodeArgs) { + auto Size = GetSrcSize(Op); + + OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); + OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + + OrderedNode* Srcs1[2]{}; + OrderedNode* Srcs2[2]{}; + + Srcs1[0] = _VExtr(Size, ElementSize, Src1, Src1, 0); + Srcs1[1] = _VExtr(Size, ElementSize, Src1, Src1, 2); + + Srcs2[0] = _VExtr(Size, ElementSize, Src2, Src2, 0); + Srcs2[1] = _VExtr(Size, ElementSize, Src2, Src2, 2); + + Src1 = _VInsElement(Size, ElementSize, 1, 0, Srcs1[0], Srcs1[1]); + Src2 = _VInsElement(Size, ElementSize, 1, 0, Srcs2[0], Srcs2[1]); + + OrderedNode *Res{}; + if (Signed) { + Res = _VSMull(Size, ElementSize, Src1, Src2); + } + else { + Res = _VUMull(Size, ElementSize, Src1, Src2); + + } + StoreResult(FPRClass, Op, Res, -1); +} + void OpDispatchBuilder::UnimplementedOp(OpcodeArgs) { // We don't actually support this instruction // Multiblock may hit it though @@ -4427,7 +4491,6 @@ void InstallOpcodeHandlers() { {0xBB, 1, &OpDispatchBuilder::BTCOp<0>}, {0xBC, 1, &OpDispatchBuilder::BSFOp}, // BSF {0xBD, 1, &OpDispatchBuilder::BSROp}, // BSF - // XXX: Broken on LLVM? {0xBE, 2, &OpDispatchBuilder::MOVSXOp}, {0xC0, 2, &OpDispatchBuilder::XADDOp}, {0xC8, 8, &OpDispatchBuilder::BSWAPOp}, @@ -4435,6 +4498,7 @@ void InstallOpcodeHandlers() { // SSE // XXX: Broken on LLVM? {0x10, 2, &OpDispatchBuilder::MOVUPSOp}, + {0x12, 2, &OpDispatchBuilder::MOVLPOp}, {0x14, 1, &OpDispatchBuilder::PUNPCKLOp<4>}, {0x16, 1, &OpDispatchBuilder::MOVLHPSOp}, {0x17, 1, &OpDispatchBuilder::MOVUPSOp}, @@ -4445,6 +4509,7 @@ void InstallOpcodeHandlers() { {0x57, 1, &OpDispatchBuilder::VectorALUOp}, {0x58, 1, &OpDispatchBuilder::VectorALUOp}, {0x59, 1, &OpDispatchBuilder::VectorALUOp}, + {0x5A, 1, &OpDispatchBuilder::VFCVTF<8, 4>}, {0x5B, 1, &OpDispatchBuilder::FCVT<4, true>}, {0x5C, 1, &OpDispatchBuilder::VectorALUOp}, {0x5D, 1, &OpDispatchBuilder::VectorALUOp}, @@ -4467,6 +4532,7 @@ void InstallOpcodeHandlers() { {0xB9, 1, nullptr}, // GROUP 10 {0xBA, 1, nullptr}, // GROUP 8 + {0xC4, 1, &OpDispatchBuilder::PINSROp<4>}, {0xC6, 1, &OpDispatchBuilder::SHUFOp<4>}, {0xC7, 1, nullptr}, // GROUP 9 @@ -4687,6 +4753,8 @@ void InstallOpcodeHandlers() { {0xDB, 1, &OpDispatchBuilder::VectorALUOp}, {0xDE, 1, &OpDispatchBuilder::PMAXUOp<1>}, {0xDF, 1, &OpDispatchBuilder::ANDNOp}, + {0xE1, 1, &OpDispatchBuilder::PSRAIOp<2>}, + {0xE2, 1, &OpDispatchBuilder::PSRAIOp<4>}, {0xE7, 1, &OpDispatchBuilder::MOVVectorOp}, {0xEA, 1, &OpDispatchBuilder::PMINSWOp}, @@ -4695,6 +4763,7 @@ void InstallOpcodeHandlers() { {0xEF, 1, &OpDispatchBuilder::VectorALUOp}, {0xF2, 1, &OpDispatchBuilder::PSLL<4, true, 0>}, {0xF3, 1, &OpDispatchBuilder::PSLL<8, true, 0>}, + {0xF4, 1, &OpDispatchBuilder::PMULOp<4, false>}, {0xF8, 4, &OpDispatchBuilder::PSUBQOp}, {0xFD, 1, &OpDispatchBuilder::PADDQOp}, {0xFE, 1, &OpDispatchBuilder::PADDQOp}, @@ -4727,10 +4796,16 @@ constexpr uint16_t PF_F2 = 3; {OPD(FEXCore::X86Tables::TYPE_GROUP_8, PF_66, 7), 1, &OpDispatchBuilder::BTCOp<1>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_8, PF_F2, 7), 1, &OpDispatchBuilder::BTCOp<1>}, + // GROUP 12 + {OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAOp<2>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 4), 1, &OpDispatchBuilder::PSRAOp<2>}, + // GROUP 13 {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLD<4, 1>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAOp<4>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 6), 1, &OpDispatchBuilder::PSLL<4, true, 1>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 2), 1, &OpDispatchBuilder::PSRLD<4, 1>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 4), 1, &OpDispatchBuilder::PSRAOp<4>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 6), 1, &OpDispatchBuilder::PSLL<4, true, 1>}, // GROUP 14 diff --git a/Source/Interface/Core/OpcodeDispatcher.h b/Source/Interface/Core/OpcodeDispatcher.h index ae7897915..e4f643c8b 100644 --- a/Source/Interface/Core/OpcodeDispatcher.h +++ b/Source/Interface/Core/OpcodeDispatcher.h @@ -217,6 +217,10 @@ public: void PSLL(OpcodeArgs); void PSRLDQ(OpcodeArgs); void PSLLDQ(OpcodeArgs); + template + void PSRAOp(OpcodeArgs); + template + void PSRAIOp(OpcodeArgs); void MOVDDUPOp(OpcodeArgs); template void CVT(OpcodeArgs); @@ -256,6 +260,9 @@ public: template void PACKUSOp(OpcodeArgs); + template + void PMULOp(OpcodeArgs); + void UnimplementedOp(OpcodeArgs); #undef OpcodeArgs @@ -361,6 +368,12 @@ public: IRPair _VUShlS(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { return _VUShlS(ssa0, ssa1, RegisterSize, ElementSize); } + IRPair _VUShrS(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VUShrS(ssa0, ssa1, RegisterSize, ElementSize); + } + IRPair _VSShrS(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VSShrS(ssa0, ssa1, RegisterSize, ElementSize); + } IRPair _VUShr(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { return _VUShr(ssa0, ssa1, RegisterSize, ElementSize); } @@ -373,6 +386,12 @@ public: IRPair _VSRI(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, uint8_t ByteShift) { return _VSRI(ssa0, RegisterSize, ElementSize, ByteShift); } + IRPair _VUShrI(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, uint8_t BitShift) { + return _VUShrI(ssa0, RegisterSize, ElementSize, BitShift); + } + IRPair _VSShrI(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, uint8_t BitShift) { + return _VSShrI(ssa0, RegisterSize, ElementSize, BitShift); + } IRPair _VFSqrt(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0) { return _VFSqrt(ssa0, RegisterSize, ElementSize); } @@ -406,6 +425,18 @@ public: IRPair _VInsGPR(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1, uint8_t Index) { return _VInsGPR(ssa0, ssa1, RegisterSize, ElementSize, Index); } + IRPair _VUMul(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VUMul(ssa0, ssa1, RegisterSize, ElementSize); + } + IRPair _VSMul(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VSMul(ssa0, ssa1, RegisterSize, ElementSize); + } + IRPair _VUMull(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VUMull(ssa0, ssa1, RegisterSize, ElementSize); + } + IRPair _VSMull(uint8_t RegisterSize, uint8_t ElementSize, OrderedNode *ssa0, OrderedNode *ssa1) { + return _VSMull(ssa0, ssa1, RegisterSize, ElementSize); + } IRPair _Jump() { return _Jump(InvalidNode); diff --git a/Source/Interface/Core/X86Tables/SecondaryTables.cpp b/Source/Interface/Core/X86Tables/SecondaryTables.cpp index a9aaf5ba4..50a7639fb 100644 --- a/Source/Interface/Core/X86Tables/SecondaryTables.cpp +++ b/Source/Interface/Core/X86Tables/SecondaryTables.cpp @@ -192,7 +192,7 @@ void InitializeSecondaryTables() { {0xC1, 1, X86InstInfo{"XADD", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST, 0, nullptr}}, {0xC2, 1, X86InstInfo{"CMPPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC3, 1, X86InstInfo{"MOVNTI", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST, 0, nullptr}}, - {0xC4, 1, X86InstInfo{"PINSRW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}}, + {0xC4, 1, X86InstInfo{"PINSRW", TYPE_MMX, GenFlagsSizes(SIZE_64BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}}, {0xC5, 1, X86InstInfo{"PEXTRW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC6, 1, X86InstInfo{"SHUFPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC7, 1, X86InstInfo{"", TYPE_GROUP_9, FLAGS_NONE, 0, nullptr}}, @@ -492,7 +492,7 @@ void InitializeSecondaryTables() { {0xC0, 2, X86InstInfo{"", TYPE_COPY_OTHER, FLAGS_NONE, 0, nullptr}}, {0xC2, 1, X86InstInfo{"CMPPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC3, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, - {0xC4, 1, X86InstInfo{"PINSRW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_SRC_GPR | FLAGS_XMM_FLAGS, 1, nullptr}}, + {0xC4, 1, X86InstInfo{"PINSRW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_SF_SRC_GPR | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC5, 1, X86InstInfo{"PEXTRW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC6, 1, X86InstInfo{"SHUFPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}}, {0xC7, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, diff --git a/Source/Interface/IR/IR.json b/Source/Interface/IR/IR.json index 1cdb0954c..f3d47b580 100644 --- a/Source/Interface/IR/IR.json +++ b/Source/Interface/IR/IR.json @@ -879,6 +879,15 @@ ] }, + "VUShr": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + "VUShlS": { "HasDest": true, "SSAArgs": "2", @@ -888,8 +897,17 @@ ] }, - "VUShr": { - "HasDest": true, + "VUShrS": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + + "VSShrS": { + "HasDest": true, "SSAArgs": "2", "Args": [ "uint8_t", "RegisterSize", @@ -948,6 +966,26 @@ ] }, + "VUShrI": { + "HasDest": true, + "SSAArgs": "1", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize", + "uint8_t", "BitShift" + ] + }, + + "VSShrI": { + "HasDest": true, + "SSAArgs": "1", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize", + "uint8_t", "BitShift" + ] + }, + "VBitcast": { "HasDest": true, "SSAArgs": "1" @@ -1076,6 +1114,42 @@ ] }, + "VUMul": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + + "VSMul": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + + "VUMull": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + + "VSMull": { + "HasDest": true, + "SSAArgs": "2", + "Args": [ + "uint8_t", "RegisterSize", + "uint8_t", "ElementSize" + ] + }, + "Last": { "Last": true, "Args": []