From b8dd5d95b015b2c5d5861af8a00009df022783a0 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 20 May 2025 16:00:32 -0400 Subject: [PATCH 1/2] OpcodeDispatcher: optimize X87FTWTag using bit twiddling tricks :-) Signed-off-by: Alyssa Rosenzweig --- .../Source/Interface/Core/OpcodeDispatcher.h | 1 - .../Interface/Core/OpcodeDispatcher/X87.cpp | 33 ++++++++++--------- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 456e09cc4..4794fcdef 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -2334,7 +2334,6 @@ private: /** @} */ Ref GetX87Top(); - Ref GetX87Tag(Ref Value, Ref AbridgedFTW); void SetX87FTW(Ref FTW); Ref GetX87FTW_Helper(); void SetX87Top(Ref Value); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index 3441e3896..e11846eda 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -31,14 +31,6 @@ Ref OpDispatchBuilder::GetX87Top() { return _LoadContext(OpSize::i8Bit, GPRClass, offsetof(FEXCore::Core::CPUState, flags) + FEXCore::X86State::X87FLAG_TOP_LOC); } -Ref OpDispatchBuilder::GetX87Tag(Ref Value, Ref AbridgedFTW) { - Ref RegValid = _And(OpSize::i32Bit, _Lshr(OpSize::i32Bit, AbridgedFTW, Value), _Constant(1)); - Ref X87Empty = _Constant(static_cast(FPState::X87Tag::Empty)); - Ref X87Valid = _Constant(static_cast(FPState::X87Tag::Valid)); - - return _Select(FEXCore::IR::COND_EQ, RegValid, _Constant(0), X87Empty, X87Valid); -} - void OpDispatchBuilder::SetX87FTW(Ref FTW) { Ref X87Empty = _Constant(static_cast(FPState::X87Tag::Empty)); Ref NewAbridgedFTW {}; @@ -312,14 +304,25 @@ void OpDispatchBuilder::FSUB(OpcodeArgs, IR::OpSize Width, bool Integer, bool Re } Ref OpDispatchBuilder::GetX87FTW_Helper() { - Ref FTW = _Constant(0); + // AbridgedFTWIndex has 1-bit per slot (8 slots). Duplicate each bit to get + // 2-bits per slot (16-bit result). Duplicating bits is equivalent to + // Morton interleaving a number with itself. To interleave efficiently two + // bytes, we use the well-known bit twiddling algorithm: + // + // https://graphics.stanford.edu/~seander/bithacks.html#InterleaveBMN + Ref X = LoadContext(AbridgedFTWIndex); + X = _Orlshl(OpSize::i32Bit, X, X, 4); + X = _And(OpSize::i32Bit, X, _Constant(0x0f0f0f0f)); + X = _Orlshl(OpSize::i32Bit, X, X, 2); + X = _And(OpSize::i32Bit, X, _Constant(0x33333333)); + X = _Orlshl(OpSize::i32Bit, X, X, 1); + X = _And(OpSize::i32Bit, X, _Constant(0x55555555)); + X = _Orlshl(OpSize::i32Bit, X, X, 1); - for (int i = 0; i < 8; i++) { - Ref RegTag = GetX87Tag(_Constant(i), LoadContext(AbridgedFTWIndex)); - FTW = _Orlshl(OpSize::i32Bit, FTW, RegTag, i * 2); - } - - return FTW; + // The above sequence sets valid to 11 and empty to 00, so invert to finalize. + static_assert(static_cast(FPState::X87Tag::Valid) == 0b00); + static_assert(static_cast(FPState::X87Tag::Empty) == 0b11); + return _Xor(OpSize::i32Bit, X, _Constant(0xffff)); } void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) { From cf2ff90f87ffb12f5fd04b4566ce3c59d71ab580 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 28 May 2025 13:14:06 -0400 Subject: [PATCH 2/2] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/FlagM/x87.json | 112 ++++-------------- .../InstructionCountCI/FlagM/x87_f64.json | 109 ++++------------- unittests/InstructionCountCI/x87.json | 112 ++++-------------- unittests/InstructionCountCI/x87_f64.json | 109 ++++------------- 4 files changed, 82 insertions(+), 360 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 078e3eea2..946457a57 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -2169,7 +2169,7 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 27, "Comment": [ "0xd9 !11b /6" ], @@ -2187,55 +2187,20 @@ "ldrb w21, [x28, #1022]", "orr x20, x20, x21, lsl #14", "str w20, [x4, #4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", - "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x20, x23, x20, eq", - "orr w20, w22, w20, lsl #14", + "ldrb w20, [x28, #1298]", + "orr w20, w20, w20, lsl #4", + "and w20, w20, #0xf0f0f0f", + "orr w20, w20, w20, lsl #2", + "and w20, w20, #0x33333333", + "orr w20, w20, w20, lsl #1", + "and w20, w20, #0x55555555", + "orr w20, w20, w20, lsl #1", + "eor w20, w20, #0xffff", "str w20, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", "str wzr, [x4, #20]", - "str wzr, [x4, #24]", - "msr nzcv, x24" + "str wzr, [x4, #24]" ] }, "fnstcw [rax]": { @@ -7195,7 +7160,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 76, "Comment": [ "0xdd !11b /6" ], @@ -7214,49 +7179,15 @@ "ldrb w22, [x28, #1022]", "orr x21, x21, x22, lsl #14", "str w21, [x4, #4]", - "mov w21, #0x0", - "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", - "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x21, x24, x21, eq", - "orr w21, w23, w21, lsl #14", + "ldrb w21, [x28, #1298]", + "orr w21, w21, w21, lsl #4", + "and w21, w21, #0xf0f0f0f", + "orr w21, w21, w21, lsl #2", + "and w21, w21, #0x33333333", + "orr w21, w21, w21, lsl #1", + "and w21, w21, #0x55555555", + "orr w21, w21, w21, lsl #1", + "eor w21, w21, #0xffff", "str w21, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", @@ -7309,7 +7240,6 @@ "strb wzr, [x28, #1017]", "strb wzr, [x28, #1018]", "strb wzr, [x28, #1022]", - "msr nzcv, x25", "strb wzr, [x28, #1298]" ] }, diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 7062bb2c2..088917188 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -1633,7 +1633,7 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 27, "Comment": [ "0xd9 !11b /6" ], @@ -1651,55 +1651,20 @@ "ldrb w21, [x28, #1022]", "orr x20, x20, x21, lsl #14", "str w20, [x4, #4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", - "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x20, x23, x20, eq", - "orr w20, w22, w20, lsl #14", + "ldrb w20, [x28, #1298]", + "orr w20, w20, w20, lsl #4", + "and w20, w20, #0xf0f0f0f", + "orr w20, w20, w20, lsl #2", + "and w20, w20, #0x33333333", + "orr w20, w20, w20, lsl #1", + "and w20, w20, #0x55555555", + "orr w20, w20, w20, lsl #1", + "eor w20, w20, #0xffff", "str w20, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", "str wzr, [x4, #20]", - "str wzr, [x4, #24]", - "msr nzcv, x24" + "str wzr, [x4, #24]" ] }, "fnstcw [rax]": { @@ -5900,7 +5865,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 174, + "ExpectedInstructionCount": 140, "Comment": [ "0xdd !11b /6" ], @@ -5921,47 +5886,14 @@ "str w21, [x4, #4]", "mov w21, #0x0", "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", - "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x22, x24, x21, eq", - "orr w22, w23, w22, lsl #14", + "orr w22, w22, w22, lsl #4", + "and w22, w22, #0xf0f0f0f", + "orr w22, w22, w22, lsl #2", + "and w22, w22, #0x33333333", + "orr w22, w22, w22, lsl #1", + "and w22, w22, #0x55555555", + "orr w22, w22, w22, lsl #1", + "eor w22, w22, #0xffff", "str w22, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", @@ -6077,7 +6009,6 @@ "strb wzr, [x28, #1017]", "strb wzr, [x28, #1018]", "strb wzr, [x28, #1022]", - "msr nzcv, x25", "strb wzr, [x28, #1298]" ] }, diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index e27a1b7cd..c25f52e22 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -2168,7 +2168,7 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 27, "Comment": [ "0xd9 !11b /6" ], @@ -2186,55 +2186,20 @@ "ldrb w21, [x28, #1022]", "orr x20, x20, x21, lsl #14", "str w20, [x4, #4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", - "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x20, x23, x20, eq", - "orr w20, w22, w20, lsl #14", + "ldrb w20, [x28, #1298]", + "orr w20, w20, w20, lsl #4", + "and w20, w20, #0xf0f0f0f", + "orr w20, w20, w20, lsl #2", + "and w20, w20, #0x33333333", + "orr w20, w20, w20, lsl #1", + "and w20, w20, #0x55555555", + "orr w20, w20, w20, lsl #1", + "eor w20, w20, #0xffff", "str w20, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", "str wzr, [x4, #20]", - "str wzr, [x4, #24]", - "msr nzcv, x24" + "str wzr, [x4, #24]" ] }, "fnstcw [rax]": { @@ -7226,7 +7191,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 76, "Comment": [ "0xdd !11b /6" ], @@ -7245,49 +7210,15 @@ "ldrb w22, [x28, #1022]", "orr x21, x21, x22, lsl #14", "str w21, [x4, #4]", - "mov w21, #0x0", - "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", - "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x21, x24, x21, eq", - "orr w21, w23, w21, lsl #14", + "ldrb w21, [x28, #1298]", + "orr w21, w21, w21, lsl #4", + "and w21, w21, #0xf0f0f0f", + "orr w21, w21, w21, lsl #2", + "and w21, w21, #0x33333333", + "orr w21, w21, w21, lsl #1", + "and w21, w21, #0x55555555", + "orr w21, w21, w21, lsl #1", + "eor w21, w21, #0xffff", "str w21, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", @@ -7340,7 +7271,6 @@ "strb wzr, [x28, #1017]", "strb wzr, [x28, #1018]", "strb wzr, [x28, #1022]", - "msr nzcv, x25", "strb wzr, [x28, #1298]" ] }, diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index d76cb3554..ea49cc4a9 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -1650,7 +1650,7 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 27, "Comment": [ "0xd9 !11b /6" ], @@ -1668,55 +1668,20 @@ "ldrb w21, [x28, #1022]", "orr x20, x20, x21, lsl #14", "str w20, [x4, #4]", - "mov w20, #0x0", - "ldrb w21, [x28, #1298]", - "and w22, w21, #0x1", - "mov w23, #0x3", - "mrs x24, nzcv", - "cmp x22, #0x0 (0)", - "csel x22, x23, x20, eq", - "orr w22, w20, w22", - "lsr w25, w21, #1", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #2", - "lsr w25, w21, #2", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #4", - "lsr w25, w21, #3", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #6", - "lsr w25, w21, #4", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #8", - "lsr w25, w21, #5", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #10", - "lsr w25, w21, #6", - "and w25, w25, #0x1", - "cmp x25, #0x0 (0)", - "csel x25, x23, x20, eq", - "orr w22, w22, w25, lsl #12", - "lsr w21, w21, #7", - "and w21, w21, #0x1", - "cmp x21, #0x0 (0)", - "csel x20, x23, x20, eq", - "orr w20, w22, w20, lsl #14", + "ldrb w20, [x28, #1298]", + "orr w20, w20, w20, lsl #4", + "and w20, w20, #0xf0f0f0f", + "orr w20, w20, w20, lsl #2", + "and w20, w20, #0x33333333", + "orr w20, w20, w20, lsl #1", + "and w20, w20, #0x55555555", + "orr w20, w20, w20, lsl #1", + "eor w20, w20, #0xffff", "str w20, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", "str wzr, [x4, #20]", - "str wzr, [x4, #24]", - "msr nzcv, x24" + "str wzr, [x4, #24]" ] }, "fnstcw [rax]": { @@ -5939,7 +5904,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 174, + "ExpectedInstructionCount": 140, "Comment": [ "0xdd !11b /6" ], @@ -5960,47 +5925,14 @@ "str w21, [x4, #4]", "mov w21, #0x0", "ldrb w22, [x28, #1298]", - "and w23, w22, #0x1", - "mov w24, #0x3", - "mrs x25, nzcv", - "cmp x23, #0x0 (0)", - "csel x23, x24, x21, eq", - "orr w23, w21, w23", - "lsr w30, w22, #1", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #2", - "lsr w30, w22, #2", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #4", - "lsr w30, w22, #3", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #6", - "lsr w30, w22, #4", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #8", - "lsr w30, w22, #5", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #10", - "lsr w30, w22, #6", - "and w30, w30, #0x1", - "cmp x30, #0x0 (0)", - "csel x30, x24, x21, eq", - "orr w23, w23, w30, lsl #12", - "lsr w22, w22, #7", - "and w22, w22, #0x1", - "cmp x22, #0x0 (0)", - "csel x22, x24, x21, eq", - "orr w22, w23, w22, lsl #14", + "orr w22, w22, w22, lsl #4", + "and w22, w22, #0xf0f0f0f", + "orr w22, w22, w22, lsl #2", + "and w22, w22, #0x33333333", + "orr w22, w22, w22, lsl #1", + "and w22, w22, #0x55555555", + "orr w22, w22, w22, lsl #1", + "eor w22, w22, #0xffff", "str w22, [x4, #8]", "str wzr, [x4, #12]", "str wzr, [x4, #16]", @@ -6116,7 +6048,6 @@ "strb wzr, [x28, #1017]", "strb wzr, [x28, #1018]", "strb wzr, [x28, #1022]", - "msr nzcv, x25", "strb wzr, [x28, #1298]" ] },