From ef19242be3cd630d9523c7af197b61f598636bc2 Mon Sep 17 00:00:00 2001 From: LC Date: Mon, 29 Jun 2026 12:11:47 -0400 Subject: [PATCH] IR: Add constant for swapping midsections of 256-bit vectors around This'll let us eliminate some pretty gnarly inserts while ZIP1Q/UZP1Q/etc are still unavailable. --- FEXCore/Source/Interface/Core/CPUBackend.cpp | 2 + FEXCore/Source/Interface/IR/IRDumper.cpp | 4 + FEXCore/include/FEXCore/IR/IR.h | 6 ++ unittests/InstructionCountCI/AVX128/FMA4.json | 60 +++++------ .../InstructionCountCI/AVX128/VEX_map1.json | 64 +++++------ .../InstructionCountCI/AVX128/VEX_map2.json | 50 ++++----- .../AVX128/VEX_map2_SVE128.json | 48 ++++----- .../InstructionCountCI/AVX128/VEX_map3.json | 16 +-- .../InstructionCountCI/Crypto/H0F38.json | 2 +- .../InstructionCountCI/Crypto/H0F3A.json | 20 ++-- .../InstructionCountCI/FlagM/Secondary.json | 2 +- .../FlagM/Secondary_OpSize.json | 2 +- .../InstructionCountCI/FlagM/VEX_map1.json | 2 +- .../FlagM/x87-HalfLife.json | 12 +-- .../FlagM/x87-Oblivion.json | 74 ++++++------- .../FlagM/x87-Psychonauts.json | 22 ++-- unittests/InstructionCountCI/FlagM/x87.json | 18 ++-- .../InstructionCountCI/FlagM/x87_f64.json | 24 ++--- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 14 +-- .../InstructionCountCI/PrimaryGroup.json | 4 +- unittests/InstructionCountCI/Secondary.json | 12 +-- .../InstructionCountCI/Secondary_OpSize.json | 10 +- .../InstructionCountCI/Secondary_REP.json | 24 ++--- .../InstructionCountCI/Secondary_REPNE.json | 6 +- unittests/InstructionCountCI/VEX_map1.json | 102 +++++++++--------- .../InstructionCountCI/VEX_map1_FRINTTS.json | 16 +-- unittests/InstructionCountCI/VEX_map2.json | 26 ++--- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 18 ++-- unittests/InstructionCountCI/x87_f64.json | 24 ++--- 31 files changed, 351 insertions(+), 339 deletions(-) diff --git a/FEXCore/Source/Interface/Core/CPUBackend.cpp b/FEXCore/Source/Interface/Core/CPUBackend.cpp index 1b1fc105d..7a18d998d 100644 --- a/FEXCore/Source/Interface/Core/CPUBackend.cpp +++ b/FEXCore/Source/Interface/Core/CPUBackend.cpp @@ -43,6 +43,8 @@ namespace CPU { {0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER + {0x0706'0504'0302'0100ULL, 0x1716'1514'1312'1110ULL}, // NAMED_VECTOR_256_MID_ELEMENT_SWAP + {0x0F0E'0D0C'0B0A'0908ULL, 0x1F1E'1D1C'1B1A'1918ULL}, // NAMED_VECTOR_256_MID_ELEMENT_SWAP_UPPER {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_ONE {0xD49A'784B'CD1B'8AFEULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_LOG2_10 {0xB8AA'3B29'5C17'F0BCULL, 0x0000'0000'0000'3FFFULL}, // NAMED_VECTOR_X87_LOG2_E diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp index 11daa1929..53d78b0d8 100644 --- a/FEXCore/Source/Interface/IR/IRDumper.cpp +++ b/FEXCore/Source/Interface/IR/IRDumper.cpp @@ -208,6 +208,10 @@ static void PrintArg(fextl::stringstream* out, const IRListView*, NamedVectorCon return "movmaskb"; case NamedVectorConstant::NAMED_VECTOR_MOVMASKB_UPPER: return "movmaskb_upper"; + case NamedVectorConstant::NAMED_VECTOR_256_MID_ELEMENT_SWAP: + return "v256_mid_element_swap"; + case NamedVectorConstant::NAMED_VECTOR_256_MID_ELEMENT_SWAP_UPPER: + return "v256_mid_element_swap_upper"; case NamedVectorConstant::NAMED_VECTOR_ZERO: return "vectorzero"; case NamedVectorConstant::NAMED_VECTOR_X87_ONE: diff --git a/FEXCore/include/FEXCore/IR/IR.h b/FEXCore/include/FEXCore/IR/IR.h index 608754b43..ca43d18ed 100644 --- a/FEXCore/include/FEXCore/IR/IR.h +++ b/FEXCore/include/FEXCore/IR/IR.h @@ -34,6 +34,12 @@ enum NamedVectorConstant : uint8_t { NAMED_VECTOR_MOVMASKB, NAMED_VECTOR_MOVMASKB_UPPER, + // Used to swap [0, 1, 2, 3] into [0, 2, 1, 3] in lieu + // of Q operations introduced in SVE2.1. Can be removed when + // such operations become available. + NAMED_VECTOR_256_MID_ELEMENT_SWAP, + NAMED_VECTOR_256_MID_ELEMENT_SWAP_UPPER, + NAMED_VECTOR_X87_ONE, NAMED_VECTOR_X87_LOG2_10, NAMED_VECTOR_X87_LOG2_E, diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index c6c03db35..7d7c78312 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -19,7 +19,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -33,7 +33,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -47,7 +47,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -61,7 +61,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -75,7 +75,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -89,7 +89,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -103,7 +103,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -117,7 +117,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -131,7 +131,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -145,7 +145,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -159,7 +159,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -173,7 +173,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -187,7 +187,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -201,7 +201,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -215,7 +215,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -229,7 +229,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -243,7 +243,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -257,7 +257,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -271,7 +271,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -285,7 +285,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -299,7 +299,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -313,7 +313,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -327,7 +327,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -341,7 +341,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -355,7 +355,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -369,7 +369,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -383,7 +383,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -397,7 +397,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -411,7 +411,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] }, @@ -425,7 +425,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2952]", + "ldr x0, [x28, #2968]", "br x0" ] } diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index ca0aa04fb..0dbaeca1e 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -485,7 +485,7 @@ ], "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3264]", + "ldr q3, [x28, #3280]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -499,7 +499,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #192]", "ushr v3.4s, v16.4s, #31", - "ldr q4, [x28, #3264]", + "ldr q4, [x28, #3280]", "ushl v3.4s, v3.4s, v4.4s", "addv s3, v3.4s", "mov w20, v3.s[0]", @@ -1122,7 +1122,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1134,7 +1134,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1146,7 +1146,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1171,7 +1171,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1185,7 +1185,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1199,7 +1199,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1223,7 +1223,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1235,7 +1235,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1247,7 +1247,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1274,7 +1274,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1288,7 +1288,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1302,7 +1302,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1326,7 +1326,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1338,7 +1338,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1350,7 +1350,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1377,7 +1377,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1391,7 +1391,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1405,7 +1405,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -2289,7 +2289,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2303,7 +2303,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2316,7 +2316,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2330,7 +2330,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2343,7 +2343,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2357,7 +2357,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -3942,7 +3942,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d", "stp xzr, xzr, [x28, #192]" @@ -3956,7 +3956,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3168]", + "ldr q4, [x28, #3184]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.2d, v17.2d, v5.2d", "eor v3.16b, v3.16b, v4.16b", @@ -3970,7 +3970,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s", "stp xzr, xzr, [x28, #192]" @@ -3984,7 +3984,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3136]", + "ldr q4, [x28, #3152]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.4s, v17.4s, v5.4s", "eor v3.16b, v3.16b, v4.16b", @@ -4155,7 +4155,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3408]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4171,7 +4171,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #192]", - "ldr q3, [x28, #3392]", + "ldr q3, [x28, #3408]", "cmlt v4.16b, v16.16b, #0", "and v4.16b, v4.16b, v3.16b", "addp v4.16b, v4.16b, v4.16b", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 42993f2c1..02b68a6b5 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -1917,7 +1917,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3104]", + "ldr q2, [x28, #3120]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -4485,7 +4485,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4502,7 +4502,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4518,7 +4518,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4535,7 +4535,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4551,7 +4551,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4568,7 +4568,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4584,7 +4584,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4601,7 +4601,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -5541,7 +5541,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5558,7 +5558,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5574,7 +5574,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5591,7 +5591,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5607,7 +5607,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5624,7 +5624,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5640,7 +5640,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5657,7 +5657,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5673,7 +5673,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5689,7 +5689,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5704,7 +5704,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5720,7 +5720,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5735,7 +5735,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5751,7 +5751,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5766,7 +5766,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5782,7 +5782,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index b6e904f79..1084a9004 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -2843,7 +2843,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2860,7 +2860,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2876,7 +2876,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2893,7 +2893,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2909,7 +2909,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2926,7 +2926,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2942,7 +2942,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2959,7 +2959,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -3879,7 +3879,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3896,7 +3896,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3912,7 +3912,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3929,7 +3929,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3945,7 +3945,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3962,7 +3962,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3978,7 +3978,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3995,7 +3995,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4011,7 +4011,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4027,7 +4027,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3136]", + "ldr q5, [x28, #3152]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4042,7 +4042,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4058,7 +4058,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3184]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4073,7 +4073,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4089,7 +4089,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3216]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4104,7 +4104,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4120,7 +4120,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3248]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index 9aae1135c..5a8ef5dc0 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -337,7 +337,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3296]", + "ldr q2, [x28, #3312]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -348,7 +348,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3328]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -369,7 +369,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3344]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -391,7 +391,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -412,7 +412,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3360]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -423,7 +423,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3392]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -3493,7 +3493,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3280]", + "ldr q3, [x28, #3296]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", @@ -3507,7 +3507,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3280]", + "ldr q3, [x28, #3296]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index c37ffaa84..fda61cdb1 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -31,7 +31,7 @@ "0x66 0x0f 0x38 0xca" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #432]", "tbl v3.16b, {v16.16b}, v2.16b", "tbl v4.16b, {v17.16b}, v2.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 207cc5c0a..338bf2c0e 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3296]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3296]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -84,9 +84,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3664]", + "ldr q2, [x28, #3712]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -101,9 +101,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3680]", + "ldr q2, [x28, #3728]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -118,9 +118,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3696]", + "ldr q2, [x28, #3744]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -135,9 +135,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3760]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 4e3aa8267..69a5cfd84 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1608,7 +1608,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3392]", + "ldr d3, [x28, #3408]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 16bcda967..84a57a079 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -37,7 +37,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3408]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 188cc5044..ae2ebad20 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -68,7 +68,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3408]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 9b98b98d7..cbd9c7c86 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -557,7 +557,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4]", "str x30, [sp, #-16]!", @@ -567,7 +567,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q4, [x28, #3648]", + "ldr q4, [x28, #3696]", "bic v3.16b, v3.16b, v4.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", @@ -598,7 +598,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #4]", "str x30, [sp, #-16]!", @@ -608,7 +608,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "bic v3.16b, v3.16b, v5.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", @@ -639,7 +639,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #8]", "str x30, [sp, #-16]!", @@ -649,7 +649,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "bic v3.16b, v3.16b, v6.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 5ea94aa08..cbe42e906 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -3789,7 +3789,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -3839,7 +3839,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #28]", "str x30, [sp, #-16]!", @@ -4002,7 +4002,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4052,7 +4052,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #60]", "str x30, [sp, #-16]!", @@ -4238,7 +4238,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4259,7 +4259,7 @@ "ldr x30, [sp], #16", "mov v9.16b, v0.16b", "str s2, [x8, #176]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v9.16b, v2.16b", "ldr s9, [x8, #8]", "str x30, [sp, #-16]!", @@ -7530,7 +7530,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q10, [x28, #3648]", + "ldr q10, [x28, #3696]", "eor v8.16b, v8.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7621,7 +7621,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3648]", + "ldr q11, [x28, #3696]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7679,7 +7679,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3648]", + "ldr q11, [x28, #3696]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7952,7 +7952,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v7.16b, v7.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -8112,7 +8112,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1024]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v3.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8130,7 +8130,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8141,7 +8141,7 @@ "fmov s2, s0", "str s2, [x4, #1152]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v6.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8159,7 +8159,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8177,7 +8177,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8188,7 +8188,7 @@ "fmov s2, s0", "str s2, [x4, #1344]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v11.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8206,7 +8206,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8217,7 +8217,7 @@ "fmov s2, s0", "str s2, [x4, #1472]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v10.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8228,7 +8228,7 @@ "fmov s2, s0", "str s2, [x4, #1536]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v9.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8239,7 +8239,7 @@ "fmov s2, s0", "str s2, [x4, #1600]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v8.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8249,7 +8249,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1664]", - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "eor v2.16b, v7.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -12538,7 +12538,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v3.16b, v2.16b, v3.16b", "ldr s4, [x4]", "str x30, [sp, #-16]!", @@ -12580,7 +12580,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "eor v5.16b, v4.16b, v5.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12615,7 +12615,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v6.16b, v5.16b, v6.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12650,7 +12650,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3648]", + "ldr q7, [x28, #3696]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12685,7 +12685,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q8, [x28, #3648]", + "ldr q8, [x28, #3696]", "eor v8.16b, v7.16b, v8.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12720,7 +12720,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q9, [x28, #3648]", + "ldr q9, [x28, #3696]", "eor v9.16b, v8.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12755,7 +12755,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3648]", + "ldr q10, [x28, #3696]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12789,7 +12789,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3648]", + "ldr q10, [x28, #3696]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12823,7 +12823,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3648]", + "ldr q10, [x28, #3696]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -20012,7 +20012,7 @@ "mov x8, x26", "str s2, [x8, #16]", "uxtb w7, w4", - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3472]", "str w7, [x8, #56]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -21708,7 +21708,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "add x14, x28, x20, lsl #4", "ldr q3, [x14, #1056]", @@ -21763,7 +21763,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "eor v2.16b, v2.16b, v5.16b", "mov w14, #0x7b90", "movk w14, #0xa7, lsl #16", @@ -21827,7 +21827,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v2.16b, v2.16b, v6.16b", "mov w15, #0x7b80", "movk w15, #0xa7, lsl #16", @@ -21955,7 +21955,7 @@ "fmov s7, s0", "str s7, [x8, #64]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3648]", + "ldr q7, [x28, #3696]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -21979,7 +21979,7 @@ "fmov s7, s0", "str s7, [x8, #68]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3648]", + "ldr q7, [x28, #3696]", "eor v2.16b, v2.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -22005,7 +22005,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "eor v5.16b, v2.16b, v5.16b", "ldr d7, [x15]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index 0da094095..f3d4c10c6 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10858,7 +10858,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3648]", + "ldr q4, [x28, #3696]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -10903,7 +10903,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x12, x28, x22, lsl #4", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "eor v4.16b, v4.16b, v5.16b", "ldur s5, [x5, #-4]", "str x30, [sp, #-16]!", @@ -11028,7 +11028,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x5, #4]", "str x30, [sp, #-16]!", @@ -12174,7 +12174,7 @@ "ldr x30, [sp], #16", "mov v4.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q5, [x28, #3648]", + "ldr q5, [x28, #3696]", "eor v4.16b, v4.16b, v5.16b", "ldr s5, [x9, #12]", "str x30, [sp, #-16]!", @@ -12302,7 +12302,7 @@ "ldr x30, [sp], #16", "mov v5.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x9, #4]", "str x30, [sp, #-16]!", @@ -14021,7 +14021,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3648]", + "ldr q4, [x28, #3696]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -22326,7 +22326,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x13, x28, x22, lsl #4", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v5.16b, v5.16b, v6.16b", "add w14, w4, w10, lsl #2", "ldur s6, [x14, #-4]", @@ -22927,7 +22927,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #4]", @@ -23397,7 +23397,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3648]", + "ldr q7, [x28, #3696]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -23485,7 +23485,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3648]", + "ldr q6, [x28, #3696]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #12]", @@ -25586,7 +25586,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3648]", + "ldr q7, [x28, #3696]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index e600dd398..56b818a1a 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -2468,7 +2468,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2482,7 +2482,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2548,7 +2548,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3472]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2568,7 +2568,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3440]", + "ldr q2, [x28, #3488]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2588,7 +2588,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3456]", + "ldr q2, [x28, #3504]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2608,7 +2608,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3472]", + "ldr q2, [x28, #3520]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2628,7 +2628,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3488]", + "ldr q2, [x28, #3536]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2648,7 +2648,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3504]", + "ldr q2, [x28, #3552]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2742,7 +2742,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3424]", + "ldr q3, [x28, #3472]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 2d87d3606..51d0a935d 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -2151,7 +2151,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3040]", + "ldr x0, [x28, #3056]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2174,7 +2174,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2193,7 +2193,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3032]", + "ldr x0, [x28, #3048]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2229,7 +2229,7 @@ "ldr d3, [x21, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2301,7 +2301,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3088]", + "ldr x0, [x28, #3104]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2349,7 +2349,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3080]", + "ldr x0, [x28, #3096]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2373,7 +2373,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3072]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2405,13 +2405,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2458,7 +2458,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3048]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2476,7 +2476,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2495,7 +2495,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index bd7bbcc1d..44d1defdc 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -685,7 +685,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3104]", + "ldr q2, [x28, #3120]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 78219eede..03a7c1c7a 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -327,7 +327,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3296]", + "ldr q2, [x28, #3312]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -337,7 +337,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3328]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -356,7 +356,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3344]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -376,7 +376,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -395,7 +395,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3360]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -405,7 +405,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3392]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -474,7 +474,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2768]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index c220512fe..6405a2771 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -2786,7 +2786,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #3000]", + "ldr x3, [x28, #3016]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2837,7 +2837,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #3008]", + "ldr x3, [x28, #3024]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 4543a411c..717aede37 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -651,7 +651,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3264]", + "ldr q3, [x28, #3280]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -662,7 +662,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3264]", + "ldr q3, [x28, #3280]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -3546,7 +3546,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3555,7 +3555,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3567,7 +3567,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3695,7 +3695,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3392]", + "ldr d3, [x28, #3408]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 27341f77f..bd99ed273 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -525,7 +525,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -539,7 +539,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -677,7 +677,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #2480]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1259,7 +1259,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] @@ -1315,7 +1315,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3408]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 522cf621a..4720f0679 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -118,7 +118,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3520]", + "ldr s2, [x28, #3568]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -132,7 +132,7 @@ "ldr s2, [x6]", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3520]", + "ldr s3, [x28, #3568]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -145,7 +145,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3552]", + "ldr s2, [x28, #3600]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -159,7 +159,7 @@ "ldr s2, [x6]", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3552]", + "ldr s3, [x28, #3600]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -173,7 +173,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3520]", + "ldr s3, [x28, #3568]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -188,7 +188,7 @@ "frinti s2, s2", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3520]", + "ldr s3, [x28, #3568]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -202,7 +202,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3552]", + "ldr s3, [x28, #3600]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -217,7 +217,7 @@ "frinti s2, s2", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3552]", + "ldr s3, [x28, #3600]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -296,8 +296,8 @@ "ExpectedInstructionCount": 6, "Comment": "0xf3 0x0f 0x5b", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3616]", - "ldr q3, [x28, #3520]", + "ldr q2, [x28, #3664]", + "ldr q3, [x28, #3568]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -397,7 +397,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -410,7 +410,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index ab2eb0678..7a211f2ce 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -290,7 +290,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -303,7 +303,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -503,7 +503,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 176f5f94b..97b63babf 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -1064,7 +1064,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1075,7 +1075,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1086,7 +1086,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1122,7 +1122,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1139,7 +1139,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1156,7 +1156,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1195,7 +1195,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1206,7 +1206,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1217,7 +1217,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1255,7 +1255,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1272,7 +1272,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1289,7 +1289,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2712]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1328,7 +1328,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1339,7 +1339,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1350,7 +1350,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1388,7 +1388,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1405,7 +1405,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1422,7 +1422,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2704]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -2223,7 +2223,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2234,7 +2234,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2245,7 +2245,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2300,7 +2300,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #16]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2318,7 +2318,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #32]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2336,7 +2336,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2744]", "ldr q4, [x0, #48]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2865,7 +2865,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3520]", + "ldr s2, [x28, #3568]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -2880,7 +2880,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3552]", + "ldr s2, [x28, #3600]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -2895,7 +2895,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #3568]", + "ldr d2, [x28, #3616]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -2910,7 +2910,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #3600]", + "ldr d2, [x28, #3648]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -2926,7 +2926,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3520]", + "ldr s3, [x28, #3568]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -2942,7 +2942,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3552]", + "ldr s3, [x28, #3600]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -2958,7 +2958,7 @@ "frinti d2, d16", "fcvtzs w20, d2", "mov w21, #0x80000000", - "ldr d3, [x28, #3568]", + "ldr d3, [x28, #3616]", "mrs x22, nzcv", "fcmp d3, d2", "csel w4, w20, w21, gt", @@ -2974,7 +2974,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #3600]", + "ldr d3, [x28, #3648]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3323,8 +3323,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #3616]", - "ldr q4, [x28, #3520]", + "ldr q3, [x28, #3664]", + "ldr q4, [x28, #3568]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -3338,9 +3338,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2648]", + "ldr x0, [x28, #2664]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2600]", + "ldr x0, [x28, #2616]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -3358,8 +3358,8 @@ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3616]", - "ldr q3, [x28, #3520]", + "ldr q2, [x28, #3664]", + "ldr q3, [x28, #3568]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -3372,9 +3372,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2648]", + "ldr x0, [x28, #2664]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2600]", + "ldr x0, [x28, #2616]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -4109,7 +4109,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4132,7 +4132,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4269,7 +4269,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3408]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4661,8 +4661,8 @@ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #3616]", - "ldr q3, [x28, #3568]", + "ldr d2, [x28, #3664]", + "ldr q3, [x28, #3616]", "fcvtzs z4.s, p6/m, z17.d", "uzp1 z4.s, z4.s, z4.s", "mov v4.8b, v4.8b", @@ -4678,8 +4678,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3616]", - "ldr x0, [x28, #2624]", + "ldr q2, [x28, #3664]", + "ldr x0, [x28, #2640]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -4722,8 +4722,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #3616]", - "ldr q4, [x28, #3568]", + "ldr d3, [x28, #3664]", + "ldr q4, [x28, #3616]", "fcvtzs z5.s, p6/m, z2.d", "uzp1 z5.s, z5.s, z5.s", "mov v5.8b, v5.8b", @@ -4740,8 +4740,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3616]", - "ldr x0, [x28, #2624]", + "ldr q3, [x28, #3664]", + "ldr x0, [x28, #2640]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index cb3dcc854..b0d859ca0 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -112,9 +112,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2648]", + "ldr x0, [x28, #2664]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2600]", + "ldr x0, [x28, #2616]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -142,9 +142,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2648]", + "ldr x0, [x28, #2664]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2600]", + "ldr x0, [x28, #2616]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -173,8 +173,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3616]", - "ldr x0, [x28, #2624]", + "ldr q2, [x28, #3664]", + "ldr x0, [x28, #2640]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -208,8 +208,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3616]", - "ldr x0, [x28, #2624]", + "ldr q3, [x28, #3664]", + "ldr x0, [x28, #2640]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index b77149139..5785614ef 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1601,7 +1601,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3104]", + "ldr q2, [x28, #3120]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3655,7 +3655,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3681,7 +3681,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3707,7 +3707,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3733,7 +3733,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4607,7 +4607,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4633,7 +4633,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4659,7 +4659,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4685,7 +4685,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4711,7 +4711,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4736,7 +4736,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4761,7 +4761,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3216]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4786,7 +4786,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3248]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 18385ecf2..016890c09 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -4582,7 +4582,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3296]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -4595,7 +4595,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3296]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index f99f52979..54366338a 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -2467,7 +2467,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2481,7 +2481,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3648]", + "ldr q3, [x28, #3696]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2547,7 +2547,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3472]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2567,7 +2567,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3440]", + "ldr q2, [x28, #3488]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2587,7 +2587,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3456]", + "ldr q2, [x28, #3504]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2607,7 +2607,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3472]", + "ldr q2, [x28, #3520]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2627,7 +2627,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3488]", + "ldr q2, [x28, #3536]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2647,7 +2647,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3504]", + "ldr q2, [x28, #3552]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2741,7 +2741,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3424]", + "ldr q3, [x28, #3472]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 956109968..eaf88d58d 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -2169,7 +2169,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3040]", + "ldr x0, [x28, #3056]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2192,7 +2192,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2211,7 +2211,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3032]", + "ldr x0, [x28, #3048]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2247,7 +2247,7 @@ "ldr d3, [x21, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2319,7 +2319,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3088]", + "ldr x0, [x28, #3104]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2367,7 +2367,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3080]", + "ldr x0, [x28, #3096]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2391,7 +2391,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3072]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2423,13 +2423,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2476,7 +2476,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3048]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2494,7 +2494,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2513,7 +2513,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16",