diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 50fe29f09..baed30539 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5863,6 +5863,11 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b10, 0x58), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFADD, 4>},
     {OPD(1, 0b11, 0x58), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFADD, 8>},
 
+    {OPD(1, 0b00, 0x59), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMUL, 4>},
+    {OPD(1, 0b01, 0x59), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMUL, 8>},
+    {OPD(1, 0b10, 0x59), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMUL, 4>},
+    {OPD(1, 0b11, 0x59), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMUL, 8>},
+
     {OPD(1, 0b00, 0x5C), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFSUB, 4>},
     {OPD(1, 0b01, 0x5C), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFSUB, 8>},
     {OPD(1, 0b10, 0x5C), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFSUB, 4>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index 22c10dd47..cd84575e6 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -451,6 +451,10 @@ void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMIN, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMIN, 8>(OpcodeArgs);
 template
+void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMUL, 4>(OpcodeArgs);
+template
+void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMUL, 8>(OpcodeArgs);
+template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFSUB, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFSUB, 8>(OpcodeArgs);
@@ -572,6 +576,10 @@ void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMIN, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMIN, 8>(OpcodeArgs);
 template
+void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMUL, 4>(OpcodeArgs);
+template
+void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMUL, 8>(OpcodeArgs);
+template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFSUB, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFSUB, 8>(OpcodeArgs);
diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
index cfa869ae1..4c68e5b49 100644
--- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
+++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -141,10 +141,10 @@ void InitializeVEXTables() {
     {OPD(1, 0b10, 0x58), 1, X86InstInfo{"VADDSS",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b11, 0x58), 1, X86InstInfo{"VADDSD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(1, 0b00, 0x59), 1, X86InstInfo{"VMULPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x59), 1, X86InstInfo{"VMULPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b10, 0x59), 1, X86InstInfo{"VMULSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b11, 0x59), 1, X86InstInfo{"VMULSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b00, 0x59), 1, X86InstInfo{"VMULPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0x59), 1, X86InstInfo{"VMULPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b10, 0x59), 1, X86InstInfo{"VMULSS",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b11, 0x59), 1, X86InstInfo{"VMULSD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(1, 0b00, 0x5B), 1, X86InstInfo{"VCVTDQ2PS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0x5B), 1, X86InstInfo{"VCVTPS2DQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
diff --git a/unittests/ASM/VEX/vmulpd.asm b/unittests/ASM/VEX/vmulpd.asm
new file mode 100644
index 000000000..14912de66
--- /dev/null
+++ b/unittests/ASM/VEX/vmulpd.asm
@@ -0,0 +1,43 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4008000000000000", "0x4008000000000000", "0x4008000000000000", "0x4008000000000000"],
+    "XMM1": ["0x4000000000000000", "0x4000000000000000", "0x4000000000000000", "0x4000000000000000"],
+    "XMM2": ["0x4018000000000000", "0x4018000000000000", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4018000000000000", "0x4018000000000000", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0x4018000000000000", "0x4018000000000000", "0x4018000000000000", "0x4018000000000000"],
+    "XMM5": ["0x4018000000000000", "0x4018000000000000", "0x4018000000000000", "0x4018000000000000"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rdx + 32]
+
+; Memory operand
+vmulpd xmm2, xmm0, [rdx + 32]
+vmulpd ymm4, ymm0, [rdx + 32]
+
+; Register only
+vmulpd xmm3, xmm0, xmm1
+vmulpd ymm5, ymm1, ymm0
+
+hlt
+
+align 32
+.data:
+dq 0x4008000000000000
+dq 0x4008000000000000
+dq 0x4008000000000000
+dq 0x4008000000000000
+
+dq 0x4000000000000000
+dq 0x4000000000000000
+dq 0x4000000000000000
+dq 0x4000000000000000
diff --git a/unittests/ASM/VEX/vmulps.asm b/unittests/ASM/VEX/vmulps.asm
new file mode 100644
index 000000000..085e80d5b
--- /dev/null
+++ b/unittests/ASM/VEX/vmulps.asm
@@ -0,0 +1,43 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"],
+    "XMM1": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"],
+    "XMM2": ["0x4140000040A00000", "0x4200000041A80000", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4140000040A00000", "0x4200000041A80000", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0x4140000040A00000", "0x4200000041A80000", "0x4140000040A00000", "0x4200000041A80000"],
+    "XMM5": ["0x4140000040A00000", "0x4200000041A80000", "0x4140000040A00000", "0x4200000041A80000"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rdx + 32]
+
+; Memory operand
+vmulps xmm2, xmm0, [rdx + 32]
+vmulps ymm4, ymm0, [rdx + 32]
+
+; Register only
+vmulps xmm3, xmm0, xmm1
+vmulps ymm5, ymm1, ymm0
+
+hlt
+
+align 32
+.data:
+dq 0x400000003F800000 ; 2, 1
+dq 0x4080000040400000 ; 4, 3
+dq 0x400000003F800000 ; 2, 1
+dq 0x4080000040400000 ; 4, 3
+
+dq 0x40C0000040A00000 ; 6, 5
+dq 0x4100000040E00000 ; 8, 7
+dq 0x40C0000040A00000 ; 6, 5
+dq 0x4100000040E00000 ; 8, 7
diff --git a/unittests/ASM/VEX/vmulsd.asm b/unittests/ASM/VEX/vmulsd.asm
new file mode 100644
index 000000000..72751f445
--- /dev/null
+++ b/unittests/ASM/VEX/vmulsd.asm
@@ -0,0 +1,70 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4010000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM1": ["0x4010000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM2": ["0x4062000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM4": ["0x4039000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5": ["0x4059000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM7": ["0x4079000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM8": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM9": ["0x4039000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx + 32 * 0]
+vmovapd ymm1, [rdx + 32 * 1]
+vmovapd ymm2, [rdx + 32 * 2]
+vmovapd ymm3, [rdx + 32 * 3]
+vmovapd ymm4, [rdx + 32 * 4]
+
+; Register only
+vmulsd xmm0, xmm0, xmm1
+vmulsd xmm2, xmm2, xmm3
+
+; Memory operand
+vmulsd xmm5, xmm4, [rdx + 32 * 1]
+vmulsd xmm4, xmm4, [rdx + 32 * 0]
+
+; Merging different src into destination
+vpxor xmm7, xmm7, xmm7
+vmovapd ymm8, [rdx + 32 * 3]
+vmovapd ymm9, [rdx + 32 * 4]
+vmulsd xmm7, xmm8, xmm9
+
+hlt
+
+align 32
+.data:
+dq 0x3FF0000000000000 ; 1.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4010000000000000 ; 4.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4022000000000000 ; 9.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4030000000000000 ; 16.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4039000000000000 ; 25.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
diff --git a/unittests/ASM/VEX/vmulss.asm b/unittests/ASM/VEX/vmulss.asm
new file mode 100644
index 000000000..c7f7091e7
--- /dev/null
+++ b/unittests/ASM/VEX/vmulss.asm
@@ -0,0 +1,70 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4142434440800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM1": ["0x4142434440800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM2": ["0x4142434443100000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM4": ["0x4142434441C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5": ["0x4142434442C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM7": ["0x4142434443C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM8": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM9": ["0x4142434441C80000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx + 32 * 0]
+vmovapd ymm1, [rdx + 32 * 1]
+vmovapd ymm2, [rdx + 32 * 2]
+vmovapd ymm3, [rdx + 32 * 3]
+vmovapd ymm4, [rdx + 32 * 4]
+
+; Register only
+vmulss xmm0, xmm0, xmm1
+vmulss xmm2, xmm2, xmm3
+
+; Memory operand
+vmulss xmm5, xmm4, [rdx + 32 * 1]
+vmulss xmm4, xmm4, [rdx + 32 * 0]
+
+; Merging different src into destination
+vpxor xmm7, xmm7, xmm7
+vmovapd ymm8, [rdx + 32 * 3]
+vmovapd ymm9, [rdx + 32 * 4]
+vmulss xmm7, xmm8, xmm9
+
+hlt
+
+align 32
+.data:
+dq 0x414243443F800000 ; 1.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434440800000 ; 4.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441100000 ; 9.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441800000 ; 16.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441C80000 ; 25.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758