From ecb1cc4ed4cf6ccedce7886039adeba4e4adfce7 Mon Sep 17 00:00:00 2001
From: lioncash <mathew1800@gmail.com>
Date: Thu, 15 Sep 2022 16:11:53 +0000
Subject: [PATCH] Interpreter: Handle 256-bit VBic

---
 .../Interface/Core/Interpreter/VectorOps.cpp  | 24 +++++++++++++++----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
index 5a23293e9..a13a8adad 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp
@@ -95,12 +95,26 @@ DEF_OP(VAnd) {
 }
 
 DEF_OP(VBic) {
-  auto Op = IROp->C<IR::IROp_VBic>();
-  const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector1);
-  const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector2);
+  const auto Op = IROp->C<IR::IROp_VBic>();
+  const auto OpSize = IROp->Size;
 
-  const auto Dst = Src1 & ~Src2;
-  memcpy(GDP, &Dst, 16);
+  if (OpSize == 32) {
+    const auto Src1 = *GetSrc<InterpVector256*>(Data->SSAData, Op->Vector1);
+    const auto Src2 = *GetSrc<InterpVector256*>(Data->SSAData, Op->Vector2);
+
+    const auto Dst = InterpVector256{
+      .Lower = Src1.Lower & ~Src2.Lower,
+      .Upper = Src1.Upper & ~Src2.Upper,
+    };
+
+    memcpy(GDP, &Dst, sizeof(Dst));
+  } else {
+    const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector1);
+    const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector2);
+
+    const auto Dst = Src1 & ~Src2;
+    memcpy(GDP, &Dst, sizeof(Dst));
+  }
 }
 
 DEF_OP(VOr) {