diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index c58a949bc..9273f9302 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1974,7 +1974,7 @@ void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) { } else { // 32-bit and 64-bit SHLD behaves like an EXTR where the lower bits are filled from the source. - Res = _Extr(Dest, Src, Size - Shift); + Res = _Extr(IR::SizeToOpSize(GetSrcSize(Op)), Dest, Src, Size - Shift); } StoreResult(GPRClass, Op, Res, -1); @@ -2075,7 +2075,7 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) { } else { // 32-bit and 64-bit SHRD behaves like an EXTR where the upper bits are filled from the source. - Res = _Extr(Src, Dest, Shift); + Res = _Extr(IR::SizeToOpSize(GetSrcSize(Op)), Src, Dest, Shift); } StoreResult(GPRClass, Op, Res, -1); @@ -2524,7 +2524,7 @@ void OpDispatchBuilder::RCROp1Bit(OpcodeArgs) { if (Size == 32 || Size == 64) { // Rotate and insert CF in the upper bit - auto Res = _Extr(CF, Dest, Shift); + auto Res = _Extr(IR::SizeToOpSize(GetSrcSize(Op)), CF, Dest, Shift); // Our new CF will be bit (Shift - 1) of the source auto NewCF = _Bfe(1, Shift - 1, Dest); diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h index da970b126..1a71a0e93 100644 --- a/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/FEXCore/include/FEXCore/IR/IREmitter.h @@ -260,9 +260,6 @@ friend class FEXCore::IR::PassManager; IRPair _Sbfe(uint8_t _Width, uint8_t _lsb, OrderedNode *_Src) { return _Sbfe(OpSize::i64Bit, _Width, _lsb, _Src); } - IRPair _Extr(OrderedNode *_Upper, OrderedNode *_Lower, uint8_t _LSB) { - return _Extr(static_cast(std::max(GetOpSize(_Upper), GetOpSize(_Lower))), _Upper, _Lower, _LSB); - } // End of Temporary naughty implicit IR operation handlers void AddPhiValue(IR::IROp_Phi *Phi, OrderedNode *Value) {