From ea6d068cc5cccf207aa9ae18e689c0926b91789f Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 27 Aug 2023 21:44:41 -0700 Subject: [PATCH] IR: Removes implicit sized LDIV/LREM --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 12 ++++++------ FEXCore/include/FEXCore/IR/IREmitter.h | 6 ------ 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 9f8758c64..b6f70e15a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4426,8 +4426,8 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { else if (Size == 2) { OrderedNode *Src1 = LoadGPRRegister(X86State::REG_RAX, Size); OrderedNode *Src2 = LoadGPRRegister(X86State::REG_RDX, Size); - auto UDivOp = _LDiv(Src1, Src2, Divisor); - auto URemOp = _LRem(Src1, Src2, Divisor); + auto UDivOp = _LDiv(OpSize::i16Bit, Src1, Src2, Divisor); + auto URemOp = _LRem(OpSize::i16Bit, Src1, Src2, Divisor); StoreGPRRegister(X86State::REG_RAX, UDivOp, Size); StoreGPRRegister(X86State::REG_RDX, URemOp, Size); @@ -4436,8 +4436,8 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { OrderedNode *Src1 = LoadGPRRegister(X86State::REG_RAX, Size); OrderedNode *Src2 = LoadGPRRegister(X86State::REG_RDX, Size); - OrderedNode *UDivOp = _Bfe(Size * 8, 0, _LDiv(Src1, Src2, Divisor)); - OrderedNode *URemOp = _Bfe(Size * 8, 0, _LRem(Src1, Src2, Divisor)); + OrderedNode *UDivOp = _Bfe(Size * 8, 0, _LDiv(OpSize::i32Bit, Src1, Src2, Divisor)); + OrderedNode *URemOp = _Bfe(Size * 8, 0, _LRem(OpSize::i32Bit, Src1, Src2, Divisor)); StoreGPRRegister(X86State::REG_RAX, UDivOp); StoreGPRRegister(X86State::REG_RDX, URemOp); @@ -4451,8 +4451,8 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) { OrderedNode *Src1 = LoadGPRRegister(X86State::REG_RAX); OrderedNode *Src2 = LoadGPRRegister(X86State::REG_RDX); - auto UDivOp = _LDiv(Src1, Src2, Divisor); - auto URemOp = _LRem(Src1, Src2, Divisor); + auto UDivOp = _LDiv(OpSize::i64Bit, Src1, Src2, Divisor); + auto URemOp = _LRem(OpSize::i64Bit, Src1, Src2, Divisor); StoreGPRRegister(X86State::REG_RAX, UDivOp); StoreGPRRegister(X86State::REG_RDX, URemOp); diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h index f37591507..419560811 100644 --- a/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/FEXCore/include/FEXCore/IR/IREmitter.h @@ -269,12 +269,6 @@ friend class FEXCore::IR::PassManager; IRPair _PExt(OrderedNode *_Input, OrderedNode *_Mask) { return _PExt(static_cast(std::max(GetOpSize(_Input), GetOpSize(_Mask))), _Input, _Mask); } - IRPair _LDiv(OrderedNode *_Lower, OrderedNode *_Upper, OrderedNode *_Divisor) { - return _LDiv(static_cast(std::max(GetOpSize(_Divisor), std::max(GetOpSize(_Upper), GetOpSize(_Lower)))), _Lower, _Upper, _Divisor); - } - IRPair _LRem(OrderedNode *_Lower, OrderedNode *_Upper, OrderedNode *_Divisor) { - return _LRem(static_cast(std::max(GetOpSize(_Divisor), std::max(GetOpSize(_Upper), GetOpSize(_Lower)))), _Lower, _Upper, _Divisor); - } // End of Temporary naughty implicit IR operation handlers void AddPhiValue(IR::IROp_Phi *Phi, OrderedNode *Value) {