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Merge pull request #4602 from Sonicadvance1/add_instcountci_tests
InstcountCI: Adds tests for instructions discovered by #4597
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@@ -434,6 +434,35 @@ public:
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private:
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private:
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fextl::vector<std::pair<std::string_view, std::string_view>> Env;
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fextl::vector<std::pair<std::string_view, std::string_view>> Env;
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};
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};
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class SimpleSyscallHandler : public FEXCore::HLE::SyscallHandler, public FEXCore::Allocator::FEXAllocOperators {
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public:
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SimpleSyscallHandler() {
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// Just claim to be linux 64-bit for simplicity.
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OSABI = FEXCore::HLE::SyscallOSABI::OS_LINUX64;
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}
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uint64_t HandleSyscall(FEXCore::Core::CpuStateFrame* Frame, FEXCore::HLE::SyscallArguments* Args) override {
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// Don't do anything
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return 0;
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}
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FEXCore::HLE::SyscallABI GetSyscallABI(uint64_t Syscall) override {
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if (Syscall == 0) {
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// Claim syscall 0 is simple for instcountci inline tests.
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return FEXCore::HLE::SyscallABI {
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.NumArgs = 0,
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.HasReturn = true,
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.HostSyscallNumber = 0, // Just map to host syscall zero, it isn't going to get called.
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};
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}
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return {0, false, -1};
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}
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// These are no-ops implementations of the SyscallHandler API
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FEXCore::HLE::AOTIRCacheEntryLookupResult LookupAOTIRCacheEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestAddr) override {
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return {0, 0};
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}
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};
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} // namespace
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} // namespace
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int main(int argc, char** argv, char** const envp) {
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int main(int argc, char** argv, char** const envp) {
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@@ -620,7 +649,7 @@ int main(int argc, char** argv, char** const envp) {
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}
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}
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auto SignalDelegation = FEX::DummyHandlers::CreateSignalDelegator();
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auto SignalDelegation = FEX::DummyHandlers::CreateSignalDelegator();
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auto SyscallHandler = FEX::DummyHandlers::CreateSyscallHandler();
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auto SyscallHandler = fextl::make_unique<SimpleSyscallHandler>();
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CTX->SetSignalDelegator(SignalDelegation.get());
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CTX->SetSignalDelegator(SignalDelegation.get());
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CTX->SetSyscallHandler(SyscallHandler.get());
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CTX->SetSyscallHandler(SyscallHandler.get());
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@@ -17,6 +17,345 @@
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"These are instruction combinations that could be more optimal if FEX optimized for them"
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"These are instruction combinations that could be more optimal if FEX optimized for them"
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],
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],
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"Instructions": {
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"Instructions": {
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"cpuid constant": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 57,
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"Comment": [
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"CPUID function call with constant function id"
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],
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"x86Insts": [
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"mov rax, 0",
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"cpuid"
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],
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"ExpectedArm64ASM": [
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"mov w4, #0x0",
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"isb",
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"mov x1, x4",
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"mov x2, x7",
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"sub sp, sp, #0xf0 (240)",
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"mov x3, sp",
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"st1 {v2.2d, v3.2d}, [x3], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x3], #64",
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"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x3], #64",
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"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
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"stp x18, x30, [x3], #16",
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"mrs x3, nzcv",
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"str w3, [x28, #1000]",
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"stp x4, x7, [x28, #288]",
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"stp x5, x6, [x28, #304]",
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"stp x8, x9, [x28, #320]",
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"stp x10, x11, [x28, #336]",
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"stp x12, x13, [x28, #352]",
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"stp x14, x15, [x28, #368]",
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"stp x16, x17, [x28, #384]",
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"stp x19, x29, [x28, #400]",
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"stp w26, w27, [x28, #16]",
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"add x3, x28, #0x1a0 (416)",
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"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
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"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
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"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
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"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
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"ldr x0, [x28, #1368]",
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"ldr x3, [x28, #1376]",
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"blr x3",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"add x4, x28, #0x1a0 (416)",
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"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
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"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
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"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
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"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
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"ldp x4, x7, [x28, #288]",
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"ldp x5, x6, [x28, #304]",
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"ldp x8, x9, [x28, #320]",
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"ldp x10, x11, [x28, #336]",
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"ldp x12, x13, [x28, #352]",
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"ldp x14, x15, [x28, #368]",
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"ldp x16, x17, [x28, #384]",
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"ldp x19, x29, [x28, #400]",
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"ldp w26, w27, [x28, #16]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
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"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
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"ldp x18, x30, [sp], #16",
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"mov w20, w0",
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"mov w21, w1",
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"lsr x6, x0, #32",
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"lsr x5, x1, #32",
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"mov x7, x21",
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"mov x4, x20"
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]
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},
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"xgetbv constant": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 51,
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"Comment": [
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"XGETBV function call with constant function id"
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],
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"x86Insts": [
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"mov rcx, 0",
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"xgetbv"
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],
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"ExpectedArm64ASM": [
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"mov w7, #0x0",
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"sub sp, sp, #0xf0 (240)",
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"mov x3, sp",
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"st1 {v2.2d, v3.2d}, [x3], #32",
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"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x3], #64",
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"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x3], #64",
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"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x3], #64",
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"stp x18, x30, [x3], #16",
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"mrs x3, nzcv",
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"str w3, [x28, #1000]",
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"stp x4, x7, [x28, #288]",
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"stp x5, x6, [x28, #304]",
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"stp x8, x9, [x28, #320]",
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"stp x10, x11, [x28, #336]",
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"stp x12, x13, [x28, #352]",
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"stp x14, x15, [x28, #368]",
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"stp x16, x17, [x28, #384]",
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"stp x19, x29, [x28, #400]",
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"stp w26, w27, [x28, #16]",
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"add x3, x28, #0x1a0 (416)",
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"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x3], #64",
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"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
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"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
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"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
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"mov w1, w7",
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"ldr x0, [x28, #1368]",
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"ldr x2, [x28, #1384]",
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"blr x2",
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"ldr w4, [x28, #1000]",
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"msr nzcv, x4",
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"add x4, x28, #0x1a0 (416)",
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"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
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"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
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"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
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"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
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"ldp x4, x7, [x28, #288]",
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"ldp x5, x6, [x28, #304]",
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"ldp x8, x9, [x28, #320]",
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"ldp x10, x11, [x28, #336]",
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"ldp x12, x13, [x28, #352]",
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"ldp x14, x15, [x28, #368]",
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"ldp x16, x17, [x28, #384]",
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"ldp x19, x29, [x28, #400]",
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"ldp w26, w27, [x28, #16]",
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"ld1 {v2.2d, v3.2d}, [sp], #32",
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"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
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"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
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"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
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"ldp x18, x30, [sp], #16",
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"mov w4, w0",
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"lsr x5, x0, #32"
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]
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},
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"signed div narrow": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 31,
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"Comment": [
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|
"div narrowing with known smaller sources",
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|
"dividend in rdx:rax"
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],
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"x86Insts": [
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|
"cdq",
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|
"idiv rcx"
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|
],
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"ExpectedArm64ASM": [
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"mov w20, w4",
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"sbfx x20, x20, #31, #1",
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"mov w5, w20",
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"asr x0, x4, #63",
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"eor x0, x0, x5",
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"cbz x0, #+0x28",
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"mov x0, x5",
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"mov x1, x4",
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"mov x2, x7",
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"ldr x3, [x28, #3400]",
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"str x30, [sp, #-16]!",
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"blr x3",
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"ldr x30, [sp], #16",
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"mov x20, x0",
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"b #+0x8",
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"sdiv x20, x4, x7",
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"asr x0, x4, #63",
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"eor x0, x0, x5",
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"cbz x0, #+0x28",
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|
"mov x0, x5",
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|
"mov x1, x4",
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|
"mov x2, x7",
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|
"ldr x3, [x28, #3416]",
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|
"str x30, [sp, #-16]!",
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||||||
|
"blr x3",
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||||||
|
"ldr x30, [sp], #16",
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||||||
|
"mov x5, x0",
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|
"b #+0xc",
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|
"sdiv x0, x4, x7",
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|
"msub x5, x0, x7, x4",
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||||||
|
"mov x4, x20"
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|
]
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|
},
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|
"unsigned div narrow": {
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||||||
|
"x86InstructionCount": 2,
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||||||
|
"ExpectedInstructionCount": 25,
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||||||
|
"Comment": [
|
||||||
|
"div narrowing with known smaller sources",
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||||||
|
"dividend in rdx:rax"
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||||||
|
],
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||||||
|
"x86Insts": [
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||||||
|
"mov rdx, 0",
|
||||||
|
"div rcx"
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||||||
|
],
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||||||
|
"ExpectedArm64ASM": [
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||||||
|
"mov w5, #0x0",
|
||||||
|
"cbz x5, #+0x28",
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||||||
|
"mov x0, x5",
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||||||
|
"mov x1, x4",
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||||||
|
"mov x2, x7",
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||||||
|
"ldr x3, [x28, #3392]",
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||||||
|
"str x30, [sp, #-16]!",
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||||||
|
"blr x3",
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||||||
|
"ldr x30, [sp], #16",
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||||||
|
"mov x20, x0",
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||||||
|
"b #+0x8",
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||||||
|
"udiv x20, x4, x7",
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||||||
|
"cbz x5, #+0x28",
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||||||
|
"mov x0, x5",
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||||||
|
"mov x1, x4",
|
||||||
|
"mov x2, x7",
|
||||||
|
"ldr x3, [x28, #3408]",
|
||||||
|
"str x30, [sp, #-16]!",
|
||||||
|
"blr x3",
|
||||||
|
"ldr x30, [sp], #16",
|
||||||
|
"mov x5, x0",
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||||||
|
"b #+0xc",
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||||||
|
"udiv x0, x4, x7",
|
||||||
|
"msub x5, x0, x7, x4",
|
||||||
|
"mov x4, x20"
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||||||
|
]
|
||||||
|
},
|
||||||
|
"inline syscall": {
|
||||||
|
"x86InstructionCount": 2,
|
||||||
|
"ExpectedInstructionCount": 106,
|
||||||
|
"Comment": [
|
||||||
|
"Simple inline syscall check",
|
||||||
|
"When the syscall number is a known constant that matches host semantics then it can be inlined",
|
||||||
|
"InstcountCI is setup that it claims to be a 64-bit Linux syscall handler"
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||||||
|
],
|
||||||
|
"x86Insts": [
|
||||||
|
"mov rax, 0",
|
||||||
|
"syscall"
|
||||||
|
],
|
||||||
|
"ExpectedArm64ASM": [
|
||||||
|
"mov w4, #0x0",
|
||||||
|
"mov w20, #0x5",
|
||||||
|
"movk w20, #0x1, lsl #16",
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||||||
|
"str x20, [x28, #24]",
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||||||
|
"cset w20, lo",
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||||||
|
"eor x21, x27, x26",
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||||||
|
"ubfx w21, w21, #4, #1",
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||||||
|
"orr x20, x20, x21, lsl #4",
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||||||
|
"ldrb w21, [x28, #984]",
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||||||
|
"orr x20, x20, x21, lsl #8",
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||||||
|
"ldrb w21, [x28, #985]",
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||||||
|
"orr x20, x20, x21, lsl #9",
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||||||
|
"ldrsb x21, [x28, #986]",
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||||||
|
"lsr x21, x21, #63",
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||||||
|
"orr x20, x20, x21, lsl #10",
|
||||||
|
"cset w21, vs",
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||||||
|
"orr x20, x20, x21, lsl #11",
|
||||||
|
"ldrb w21, [x28, #988]",
|
||||||
|
"orr x20, x20, x21, lsl #12",
|
||||||
|
"ldrb w21, [x28, #990]",
|
||||||
|
"orr x20, x20, x21, lsl #14",
|
||||||
|
"ldrb w21, [x28, #992]",
|
||||||
|
"orr x20, x20, x21, lsl #16",
|
||||||
|
"ldrb w21, [x28, #993]",
|
||||||
|
"orr x20, x20, x21, lsl #17",
|
||||||
|
"ldrb w21, [x28, #994]",
|
||||||
|
"orr x20, x20, x21, lsl #18",
|
||||||
|
"ldrb w21, [x28, #995]",
|
||||||
|
"orr x20, x20, x21, lsl #19",
|
||||||
|
"ldrb w21, [x28, #996]",
|
||||||
|
"orr x20, x20, x21, lsl #20",
|
||||||
|
"ldrb w21, [x28, #997]",
|
||||||
|
"orr x20, x20, x21, lsl #21",
|
||||||
|
"eor w0, w26, w26, lsr #4",
|
||||||
|
"eor w0, w0, w0, lsr #2",
|
||||||
|
"eor w21, w0, w0, lsr #1",
|
||||||
|
"orr x21, x21, #0xfffffffffffffffe",
|
||||||
|
"orn x20, x20, x21, ror #62",
|
||||||
|
"mrs x21, nzcv",
|
||||||
|
"and x21, x21, #0xc0000000",
|
||||||
|
"orr x20, x20, x21, lsr #24",
|
||||||
|
"orr x15, x20, #0x2",
|
||||||
|
"mov w7, #0x7",
|
||||||
|
"movk w7, #0x1, lsl #16",
|
||||||
|
"sub sp, sp, #0xf0 (240)",
|
||||||
|
"mov x0, sp",
|
||||||
|
"st1 {v2.2d, v3.2d}, [x0], #32",
|
||||||
|
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
|
||||||
|
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
|
||||||
|
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
|
||||||
|
"stp x18, x30, [x0], #16",
|
||||||
|
"mrs x0, nzcv",
|
||||||
|
"str w0, [x28, #1000]",
|
||||||
|
"stp x4, x7, [x28, #288]",
|
||||||
|
"stp x5, x6, [x28, #304]",
|
||||||
|
"stp x8, x9, [x28, #320]",
|
||||||
|
"stp x10, x11, [x28, #336]",
|
||||||
|
"stp x12, x13, [x28, #352]",
|
||||||
|
"stp x14, x15, [x28, #368]",
|
||||||
|
"stp x16, x17, [x28, #384]",
|
||||||
|
"stp x19, x29, [x28, #400]",
|
||||||
|
"stp w26, w27, [x28, #16]",
|
||||||
|
"add x0, x28, #0x1a0 (416)",
|
||||||
|
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
|
||||||
|
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
|
||||||
|
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
|
||||||
|
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
|
||||||
|
"mov w0, #0xffff",
|
||||||
|
"str x0, [x28, #1312]",
|
||||||
|
"sub sp, sp, #0x40 (64)",
|
||||||
|
"str x4, [sp]",
|
||||||
|
"str x11, [sp, #8]",
|
||||||
|
"str x10, [sp, #16]",
|
||||||
|
"str x5, [sp, #24]",
|
||||||
|
"str x14, [sp, #32]",
|
||||||
|
"str x12, [sp, #40]",
|
||||||
|
"str x13, [sp, #48]",
|
||||||
|
"ldr x0, [x28, #1392]",
|
||||||
|
"ldr x3, [x28, #1400]",
|
||||||
|
"mov x1, x28",
|
||||||
|
"mov x2, sp",
|
||||||
|
"blr x3",
|
||||||
|
"add sp, sp, #0x40 (64)",
|
||||||
|
"ldr w1, [x28, #1000]",
|
||||||
|
"msr nzcv, x1",
|
||||||
|
"add x1, x28, #0x1a0 (416)",
|
||||||
|
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x1], #64",
|
||||||
|
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x1], #64",
|
||||||
|
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x1], #64",
|
||||||
|
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64",
|
||||||
|
"ldp x4, x7, [x28, #288]",
|
||||||
|
"ldp x5, x6, [x28, #304]",
|
||||||
|
"ldp x8, x9, [x28, #320]",
|
||||||
|
"ldp x10, x11, [x28, #336]",
|
||||||
|
"ldp x12, x13, [x28, #352]",
|
||||||
|
"ldp x14, x15, [x28, #368]",
|
||||||
|
"ldp x16, x17, [x28, #384]",
|
||||||
|
"ldp x19, x29, [x28, #400]",
|
||||||
|
"ldp w26, w27, [x28, #16]",
|
||||||
|
"str xzr, [x28, #1312]",
|
||||||
|
"ld1 {v2.2d, v3.2d}, [sp], #32",
|
||||||
|
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
|
||||||
|
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||||
|
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||||
|
"ldp x18, x30, [sp], #16",
|
||||||
|
"mov x4, x0"
|
||||||
|
]
|
||||||
|
},
|
||||||
"push ax, bx": {
|
"push ax, bx": {
|
||||||
"x86InstructionCount": 2,
|
"x86InstructionCount": 2,
|
||||||
"ExpectedInstructionCount": 2,
|
"ExpectedInstructionCount": 2,
|
||||||
|
|||||||
Reference in new issue
Block a user