diff --git a/External/FEXCore/Source/Common/SoftFloat.h b/External/FEXCore/Source/Common/SoftFloat.h
index 33924f4bd..fbb1edac6 100644
--- a/External/FEXCore/Source/Common/SoftFloat.h
+++ b/External/FEXCore/Source/Common/SoftFloat.h
@@ -2,12 +2,12 @@
 
 #include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/string.h>
 
 #include <cmath>
 #include <cstring>
 #include <stdint.h>
-#include <sstream>
 
 extern "C" {
 #include "SoftFloat-3e/platform.h"
@@ -47,12 +47,12 @@ struct X80SoftFloat {
   }
 
   fextl::string str() const {
-    std::ostringstream string;
+    fextl::ostringstream string;
     string << std::hex << Sign;
     string << "_" << Exponent;
     string << "_" << (Significand >> 63);
     string << "_" << (Significand & ((1ULL << 63) - 1));
-    return string.str().c_str();
+    return string.str();
   }
 
   // Ops
diff --git a/External/FEXCore/Source/Interface/Core/Core.cpp b/External/FEXCore/Source/Interface/Core/Core.cpp
index f094f78de..af3d1003c 100644
--- a/External/FEXCore/Source/Interface/Core/Core.cpp
+++ b/External/FEXCore/Source/Interface/Core/Core.cpp
@@ -46,6 +46,7 @@ $end_info$
 #include <FEXCore/Utils/Threads.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/vector.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <FEXHeaderUtils/TodoDefines.h>
@@ -727,7 +728,7 @@ namespace FEXCore::Context {
     }
 
     if (f) {
-      std::stringstream out;
+      fextl::stringstream out;
       auto NewIR = IREmitter->ViewIR();
       FEXCore::IR::Dump(&out, &NewIR, RA);
       fmt::print(f,"IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
@@ -740,7 +741,7 @@ namespace FEXCore::Context {
 
   static void ValidateIR(ContextImpl *ctx, IR::IREmitter *IREmitter) {
     // Convert to text, Parse, Convert to text again and make sure the texts match
-    std::stringstream out;
+    fextl::stringstream out;
     static auto compaction = IR::CreateIRCompaction(ctx->OpDispatcherAllocator);
     compaction->Run(IREmitter);
     auto NewIR = IREmitter->ViewIR();
@@ -751,7 +752,7 @@ namespace FEXCore::Context {
     if (reparsed == nullptr) {
       LOGMAN_MSG_A_FMT("Failed to parse IR\n");
     } else {
-      std::stringstream out2;
+      fextl::stringstream out2;
       auto NewIR2 = reparsed->ViewIR();
       Dump(&out2, &NewIR2, nullptr);
       if (out.str() != out2.str()) {
diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
index ff272490e..46f097b17 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -28,6 +28,7 @@ $end_info$
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/sstream.h>
 
 #include <algorithm>
 #include <array>
@@ -705,7 +706,7 @@ CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]
       if (IROp->Op != IR::OP_BEGINBLOCK &&
           IROp->Op != IR::OP_CONDJUMP &&
           IROp->Op != IR::OP_JUMP) {
-        std::stringstream Inst;
+        fextl::stringstream Inst;
         auto Name = FEXCore::IR::GetName(IROp->Op);
 
         if (IROp->HasDest) {
diff --git a/External/FEXCore/Source/Interface/IR/IRDumper.cpp b/External/FEXCore/Source/Interface/IR/IRDumper.cpp
index a4945b2c2..fddaec77c 100644
--- a/External/FEXCore/Source/Interface/IR/IRDumper.cpp
+++ b/External/FEXCore/Source/Interface/IR/IRDumper.cpp
@@ -8,6 +8,7 @@ $end_info$
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/RegisterAllocationData.h>
+#include <FEXCore/fextl/sstream.h>
 
 #include <algorithm>
 #include <array>
@@ -27,22 +28,22 @@ namespace FEXCore::IR {
 
 #include <FEXCore/IR/IRDefines.inc>
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, const SHA256Sum &Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, const SHA256Sum &Arg) {
   *out << "sha256:";
   for(auto byte: Arg.data)
     *out << std::hex << std::setfill('0') << std::setw(2) << (unsigned int)byte;
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, uint64_t Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, uint64_t Arg) {
   *out << "#0x" << std::hex << Arg;
 }
 
 [[maybe_unused]]
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, const char* Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, const char* Arg) {
   *out <<  Arg;
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, CondClassType Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, CondClassType Arg) {
   static constexpr std::array<std::string_view, 22> CondNames = {
     "EQ",
     "NEQ",
@@ -71,7 +72,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   *out << CondNames[Arg];
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, MemOffsetType Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, MemOffsetType Arg) {
   static constexpr std::array<std::string_view, 3> Names = {
     "SXTX",
     "UXTW",
@@ -81,7 +82,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   *out << Names[Arg];
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, RegisterClassType Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, RegisterClassType Arg) {
   if (Arg == GPRClass.Val)
     *out << "GPR";
   else if (Arg == GPRFixedClass.Val)
@@ -96,7 +97,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
     *out << "Unknown Registerclass " << Arg;
 }
 
-static void PrintArg(std::stringstream *out, IRListView const* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData *RAData) {
+static void PrintArg(fextl::stringstream *out, IRListView const* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData *RAData) {
   auto [CodeNode, IROp] = IR->at(Arg)();
   const auto ArgID = Arg.ID();
 
@@ -146,7 +147,7 @@ static void PrintArg(std::stringstream *out, IRListView const* IR, OrderedNodeWr
   }
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::FenceType Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::FenceType Arg) {
   if (Arg == IR::Fence_Load) {
     *out << "Loads";
   }
@@ -161,7 +162,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   }
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::RoundType Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::RoundType Arg) {
   switch (Arg) {
     case FEXCore::IR::Round_Nearest: *out << "Nearest"; break;
     case FEXCore::IR::Round_Negative_Infinity: *out << "-Inf"; break;
@@ -172,7 +173,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   }
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::SyscallFlags Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::SyscallFlags Arg) {
   switch (Arg) {
     case FEXCore::IR::SyscallFlags::DEFAULT: *out << "Default"; break;
     case FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH: *out << "Optimize Through"; break;
@@ -183,14 +184,14 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const*
   }
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::BreakDefinition Arg) {
+static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::BreakDefinition Arg) {
   *out << "{" << Arg.ErrorRegister << ".";
   *out << static_cast<uint32_t>(Arg.Signal) << ".";
   *out << static_cast<uint32_t>(Arg.TrapNumber) << ".";
   *out << static_cast<uint32_t>(Arg.si_code) << "}";
 }
 
-void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData) {
+void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData) {
   auto HeaderOp = IR->GetHeader();
 
   int8_t CurrentIndent = 0;
diff --git a/External/FEXCore/Source/Interface/IR/IRParser.cpp b/External/FEXCore/Source/Interface/IR/IRParser.cpp
index 8557c7ef7..10b3a87c8 100644
--- a/External/FEXCore/Source/Interface/IR/IRParser.cpp
+++ b/External/FEXCore/Source/Interface/IR/IRParser.cpp
@@ -11,6 +11,7 @@ $end_info$
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/unordered_map.h>
 #include <FEXCore/fextl/vector.h>
@@ -260,7 +261,7 @@ class IRParser: public FEXCore::IR::IREmitter {
   template<>
   std::pair<DecodeFailure, FEXCore::IR::BreakDefinition> DecodeValue(const fextl::string &Arg) {
     uint32_t tmp{};
-    std::stringstream ss{Arg};
+    fextl::stringstream ss{Arg};
     BreakDefinition Reason{};
 
     // Seek past '{'
diff --git a/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp
index 1e1f3da51..a97959ef4 100644
--- a/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp
+++ b/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp
@@ -15,13 +15,13 @@ $end_info$
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/vector.h>
 
 #include <cstdint>
 #include <memory>
 #include <stddef.h>
 #include <string>
-#include <sstream>
 #include <unordered_map>
 #include <utility>
 
@@ -38,8 +38,8 @@ bool IRValidation::Run(IREmitter *IREmit) {
   bool HadError = false;
   bool HadWarning = false;
 
-  std::ostringstream Errors;
-  std::ostringstream Warnings;
+  fextl::ostringstream Errors;
+  fextl::ostringstream Warnings;
 
   auto CurrentIR = IREmit->ViewIR();
 
@@ -250,7 +250,7 @@ bool IRValidation::Run(IREmitter *IREmit) {
 
   HadWarning = false;
   if (HadError || HadWarning) {
-    std::stringstream Out;
+    fextl::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, RAData);
 
     if (HadError) {
diff --git a/External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp
index 11c9c03da..b0a47b8e6 100644
--- a/External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp
+++ b/External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp
@@ -10,11 +10,11 @@ $end_info$
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/sstream.h>
 
 #include "Interface/IR/PassManager.h"
 
 #include <memory>
-#include <sstream>
 #include <string>
 
 namespace FEXCore::IR::Validation {
@@ -30,7 +30,7 @@ bool PhiValidation::Run(IREmitter *IREmit) {
   bool HadError = false;
   auto CurrentIR = IREmit->ViewIR();
 
-  std::ostringstream Errors;
+  fextl::ostringstream Errors;
 
   // Walk the list and calculate the control flow
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
@@ -62,7 +62,7 @@ bool PhiValidation::Run(IREmitter *IREmit) {
   }
 
   if (HadError) {
-    std::stringstream Out;
+    fextl::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
     Out << "Errors:" << std::endl << Errors.str() << std::endl;
     LogMan::Msg::EFmt("{}", Out.str());
diff --git a/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp
index 91b9d0554..351b26422 100644
--- a/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp
+++ b/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp
@@ -8,6 +8,7 @@
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/deque.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/unordered_map.h>
 
 #include <algorithm>
@@ -207,7 +208,7 @@ bool RAValidation::Run(IREmitter *IREmit) {
   BlocksToVisit.push_front(ValidationPass->EntryBlock); // Currently only a single entry point
 
   bool HadError = false;
-  std::ostringstream Errors;
+  fextl::ostringstream Errors;
 
   auto CurrentIR = IREmit->ViewIR();
   uint32_t CurrentVersion = 1; // Incremented every backwards edge
@@ -439,7 +440,7 @@ bool RAValidation::Run(IREmitter *IREmit) {
   }
 
   if (HadError) {
-    std::stringstream IrDump;
+    fextl::stringstream IrDump;
     FEXCore::IR::Dump(&IrDump, &CurrentIR, RAData);
 
     LogMan::Msg::EFmt("RA Validation Error\n{}\nErrors:\n{}\n", IrDump.str(), Errors.str());
diff --git a/External/FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp
index ca3985f82..a47daf17d 100644
--- a/External/FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp
+++ b/External/FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp
@@ -13,6 +13,7 @@ $end_info$
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/unordered_map.h>
 #include <FEXCore/fextl/vector.h>
 
@@ -20,7 +21,6 @@ $end_info$
 #include <memory>
 #include <stdint.h>
 #include <string>
-#include <sstream>
 #include <utility>
 
 namespace {
@@ -42,7 +42,7 @@ bool ValueDominanceValidation::Run(IREmitter *IREmit) {
   bool HadError = false;
   auto CurrentIR = IREmit->ViewIR();
 
-  std::ostringstream Errors;
+  fextl::ostringstream Errors;
   fextl::unordered_map<IR::NodeID, BlockInfo> OffsetToBlockMap;
 
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
@@ -198,7 +198,7 @@ bool ValueDominanceValidation::Run(IREmitter *IREmit) {
   }
 
   if (HadError) {
-    std::stringstream Out;
+    fextl::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
     Out << "Errors:" << std::endl << Errors.str() << std::endl;
     LogMan::Msg::EFmt("{}", Out.str());
diff --git a/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp b/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp
index d1bb4d915..cc42f8c30 100644
--- a/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp
+++ b/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp
@@ -4,6 +4,7 @@
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXHeaderUtils/ScopedSignalMask.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <FEXHeaderUtils/TypeDefines.h>
@@ -19,7 +20,6 @@
 #include <memory>
 #include <mutex>
 #include <new>
-#include <sstream>
 #include <sys/mman.h>
 #include <sys/utsname.h>
 #include <sys/user.h>
@@ -494,7 +494,7 @@ fextl::vector<FEXCore::Allocator::MemoryRegion> OSAllocator_64Bit::Steal32BitIfO
   int32_t Minor{};
   int32_t Patch{};
   char Tmp{};
-  std::istringstream ss{buf.release};
+  fextl::istringstream ss{buf.release};
   ss >> Major;
   ss.read(&Tmp, 1);
   ss >> Minor;
diff --git a/External/FEXCore/include/FEXCore/IR/IR.h b/External/FEXCore/include/FEXCore/IR/IR.h
index 017c60de5..a2954e1e8 100644
--- a/External/FEXCore/include/FEXCore/IR/IR.h
+++ b/External/FEXCore/include/FEXCore/IR/IR.h
@@ -2,6 +2,7 @@
 
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/ThreadPoolAllocator.h>
+#include <FEXCore/fextl/sstream.h>
 #include <FEXHeaderUtils/EnumOperators.h>
 
 #include <array>
@@ -10,7 +11,6 @@
 #include <cstring>
 #include <functional>
 #include <memory>
-#include <sstream>
 #include <tuple>
 
 #include <fmt/format.h>
@@ -564,7 +564,7 @@ public:
 class IRListView;
 class IREmitter;
 
-FEX_DEFAULT_VISIBILITY void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData);
+FEX_DEFAULT_VISIBILITY void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData);
 FEX_DEFAULT_VISIBILITY std::unique_ptr<IREmitter> Parse(FEXCore::Utils::IntrusivePooledAllocator &ThreadAllocator, std::istream *in);
 
 template<typename Type>