diff --git a/FEXCore/Scripts/json_ir_generator.py b/FEXCore/Scripts/json_ir_generator.py index 291eedceb..c7e5979ea 100755 --- a/FEXCore/Scripts/json_ir_generator.py +++ b/FEXCore/Scripts/json_ir_generator.py @@ -46,6 +46,7 @@ class OpDefinition: NumElements: str OpClass: str HasSideEffects: bool + ImplicitFlagClobber: bool RAOverride: int SwitchGen: bool ArgPrinter: bool @@ -67,6 +68,7 @@ class OpDefinition: self.OpClass = None self.OpSize = 0 self.HasSideEffects = False + self.ImplicitFlagClobber = False self.RAOverride = -1 self.SwitchGen = True self.ArgPrinter = True @@ -219,6 +221,9 @@ def parse_ops(ops): if "HasSideEffects" in op_val: OpDef.HasSideEffects = bool(op_val["HasSideEffects"]) + if "ImplicitFlagClobber" in op_val: + OpDef.ImplicitFlagClobber = bool(op_val["ImplicitFlagClobber"]) + if "ArgPrinter" in op_val: OpDef.ArgPrinter = bool(op_val["ArgPrinter"]) @@ -372,6 +377,7 @@ def print_ir_sizes(): output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n") output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n") output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n") + output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool ImplicitFlagClobber(IROps Op);\n") output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n") output_file.write("#undef IROP_SIZES\n") @@ -465,15 +471,17 @@ def print_ir_getraargs(): def print_ir_hassideeffects(): output_file.write("#ifdef IROP_HASSIDEEFFECTS_IMPL\n") - output_file.write("constexpr std::array SideEffects = {\n") - for op in IROps: - output_file.write("\t{},\n".format(("true" if op.HasSideEffects else "false"))) + for array, prop in [("SideEffects", "HasSideEffects"), + ("ImplicitFlagClobbers", "ImplicitFlagClobber")]: + output_file.write(f"constexpr std::array {array} = {{\n") + for op in IROps: + output_file.write("\t{},\n".format(("true" if getattr(op, prop) else "false"))) - output_file.write("};\n\n") + output_file.write("};\n\n") - output_file.write("bool HasSideEffects(IROps Op) {\n") - output_file.write(" return SideEffects[Op];\n") - output_file.write("}\n") + output_file.write(f"bool {prop}(IROps Op) {{\n") + output_file.write(f" return {array}[Op];\n") + output_file.write("}\n") output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n") output_file.write("#endif\n\n") @@ -642,6 +650,10 @@ def print_ir_allocator_helpers(): output_file.write(") {\n") + # Save NZCV if needed before clobbering NZCV + if op.ImplicitFlagClobber: + output_file.write("\t\tSaveNZCV();") + output_file.write("\t\tauto Op = AllocateOp();\n".format(op.Name, op.Name.upper())) if op.SSAArgNum != 0: diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp index 6338b6c45..472e5c666 100644 --- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp +++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp @@ -121,8 +121,8 @@ void Dispatcher::EmitDispatcher() { and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), LookupCache::L1_ENTRIES_MASK); add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ARMEmitter::Reg::r0, ARMEmitter::Reg::r3, ARMEmitter::ShiftType::LSL , 4); ldp(ARMEmitter::XReg::x3, ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, 0); - cmp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, RipReg.R()); - b(ARMEmitter::Condition::CC_NE, &FullLookup); + sub(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, RipReg); + cbnz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, &FullLookup); br(ARMEmitter::Reg::r3); @@ -167,8 +167,8 @@ void Dispatcher::EmitDispatcher() { ldp(ARMEmitter::XReg::x3, ARMEmitter::XReg::x1, ARMEmitter::Reg::r0, 0); // If the guest address doesn't match, Compile the block. - cmp(ARMEmitter::XReg::x1, RipReg); - b(ARMEmitter::Condition::CC_NE, &NoBlock); + sub(ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, RipReg); + cbnz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, &NoBlock); // Check the host address to see if it matches, else compile the block. cbz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, &NoBlock); @@ -225,7 +225,7 @@ void Dispatcher::EmitDispatcher() { FillStaticRegs(); ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)); - subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1); + sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1); str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)); // Trigger segfault if any deferred signals are pending @@ -262,7 +262,7 @@ void Dispatcher::EmitDispatcher() { FillStaticRegs(); ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)); - subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1); + sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1); str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)); // Trigger segfault if any deferred signals are pending diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp index 066ca099a..85ed85bb3 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp @@ -3694,9 +3694,16 @@ DEF_OP(VInsElement) { } else { const auto UpperBound = 16 >> FEXCore::ilog2(ElementSize); const auto TargetElement = static_cast(DestIdx) - UpperBound; + + // FIXME: We should rework this op to avoid the NZCV spill/fill dance. + mrs(TMP1, ARMEmitter::SystemRegister::NZCV); + index(SubRegSize, VTMP1.Z(), -UpperBound, 1); cmpeq(SubRegSize, Predicate, PRED_TMP_32B.Zeroing(), VTMP1.Z(), TargetElement); mov(SubRegSize, Dst.Z(), Predicate.Merging(), VTMP2.Z()); + + // Restore NZCV + msr(ARMEmitter::SystemRegister::NZCV, TMP1); } } else { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 16e15f32b..b6e26f661 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1911,30 +1911,10 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) { StoreResult(GPRClass, Op, Res, -1); - auto CondJump = _CondJump(Shift, {COND_EQ}); - - auto CurrentBlock = GetCurrentBlock(); - - // Do nothing if shift count is zero - auto JumpTarget = CreateNewCodeBlockAfter(CurrentBlock); - SetFalseJumpTarget(CondJump, JumpTarget); - SetCurrentCodeBlock(JumpTarget); - StartNewBlock(); - if (Size != 64) { Res = _Bfe(OpSize::i64Bit, Size, 0, Res); } GenerateFlags_ShiftLeft(Op, Res, Dest, Shift); - - // Calculate flags early. - CalculateDeferredFlags(); - - auto Jump = _Jump(); - auto NextJumpTarget = CreateNewCodeBlockAfter(JumpTarget); - SetJumpTarget(Jump, NextJumpTarget); - SetTrueJumpTarget(CondJump, NextJumpTarget); - SetCurrentCodeBlock(NextJumpTarget); - StartNewBlock(); } void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) { @@ -2013,28 +1993,10 @@ void OpDispatchBuilder::SHRDOp(OpcodeArgs) { StoreResult(GPRClass, Op, Res, -1); - auto CondJump = _CondJump(Shift, {COND_EQ}); - - // Do not change flags if shift count is zero - auto JumpTarget = CreateNewCodeBlockAfter(GetCurrentBlock()); - SetFalseJumpTarget(CondJump, JumpTarget); - SetCurrentCodeBlock(JumpTarget); - StartNewBlock(); - if (Size != 64) { Res = _Bfe(OpSize::i64Bit, Size, 0, Res); } GenerateFlags_ShiftRight(Op, Res, Dest, Shift); - // Calculate deferred flags immediately. - // This block is ending so it needs to serialize - CalculateDeferredFlags(); - - auto Jump = _Jump(); - auto NextJumpTarget = CreateNewCodeBlockAfter(JumpTarget); - SetJumpTarget(Jump, NextJumpTarget); - SetTrueJumpTarget(CondJump, NextJumpTarget); - SetCurrentCodeBlock(NextJumpTarget); - StartNewBlock(); } void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 6b6c1e4e5..399222c07 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -894,6 +894,10 @@ public: } } +protected: + void SaveNZCV() override { + } + private: enum class SelectionFlag { Nothing, // must rely on x86 flags diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 0e2ff7a44..1ce60b909 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -202,6 +202,7 @@ "GPR = ValidateCode u64:$CodeOriginalLow, u64:$CodeOriginalhigh, i64:$Offset, u8:$CodeLength": { "HasSideEffects": true, "HasDest": true, + "ImplicitFlagClobber": true, "DestSize": "8" }, @@ -247,6 +248,7 @@ "The second GPR pair element is a bool if the number is valid", "RNG hardware is allowed to fail early and return. Software must always check this" ], + "ImplicitFlagClobber": true, "DestSize": "16", "NumElements": "2" }, @@ -499,6 +501,7 @@ "FPR = VLoadVectorMasked u8:#RegisterSize, u8:#ElementSize, FPR:$Mask, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": { "Desc": ["Does a masked load similar to VPMASKMOV/VMASKMOV where the upper bit of each element", "determines whether or not that element will be loaded from memory"], + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -506,6 +509,7 @@ "Desc": ["Does a masked store similar to VPMASKMOV/VMASKMOV where the upper bit of each element", "determines whether or not that element will be stored to memory"], "HasSideEffects": true, + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -597,6 +601,7 @@ ], "DestSize": "Size", + "ImplicitFlagClobber": true, "EmitValidation": [ "Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] @@ -611,6 +616,7 @@ ], "HasDest": true, "DestSize": "Size", + "ImplicitFlagClobber": true, "NumElements": "2", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i64Bit || Size == FEXCore::IR::OpSize::i128Bit" @@ -753,6 +759,7 @@ "Desc": ["Set Telemetry value if the passed in 32-bit value isn't zero.", "Only useful for 32-bit applications." ], + "ImplicitFlagClobber": true, "DestSize": "8" } }, @@ -830,6 +837,7 @@ "Will truncate to 64 or 32bits" ], "DestSize": "Size", + "ImplicitFlagClobber": true, "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] @@ -859,6 +867,7 @@ "In the case of zero returns ~0U" ], "DestSize": "Size", + "ImplicitFlagClobber": true, "EmitValidation": [ "Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] @@ -914,6 +923,7 @@ "GPR = AddNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Return NZCV for the sum of two GPRs"], "DestSize": "4", + "ImplicitFlagClobber": true, "EmitValidation": [ "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" ] @@ -921,6 +931,7 @@ "GPR = AdcNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2, GPR:$NZCV": { "Desc": ["Return NZCV for the sum of two GPRs and carry-in given as NZCV"], "DestSize": "4", + "ImplicitFlagClobber": true, "EmitValidation": [ "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" ] @@ -928,6 +939,7 @@ "GPR = SbbNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2, GPR:$NZCV": { "Desc": ["Return NZCV for the sum of two GPRs and carry-in given as NZCV"], "DestSize": "4", + "ImplicitFlagClobber": true, "EmitValidation": [ "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" ] @@ -946,6 +958,7 @@ "If InvertCarry is nonzero, carry flag uses x86 definition, inverted from arm64.", ""], "DestSize": "4", + "ImplicitFlagClobber": true, "EmitValidation": [ "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" ] @@ -1007,6 +1020,7 @@ }, "GPR = TestNZ u8:$Size, GPR:$Src1": { "Desc": ["Return NZCV for a GPR, setting N and Z accordingly and zeroing C and V"], + "ImplicitFlagClobber": true, "DestSize": "4" }, "GPR = Lshl OpSize:#Size, GPR:$Src1, GPR:$Src2": { @@ -1158,6 +1172,7 @@ "Dest = Cmp1 Cmp2 ? TrueVal : FalseVal" ], "DestSize": "ResultSize", + "ImplicitFlagClobber": true, "EmitValidation": [ "_CompareSize == FEXCore::IR::OpSize::i32Bit || _CompareSize == FEXCore::IR::OpSize::i64Bit || _CompareSize == FEXCore::IR::OpSize::i128Bit", "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit", @@ -1266,6 +1281,7 @@ "Desc": ["Does a scalar unordered compare and stores the asked for flags in to a GPR", "Ordering flag result is true if either float input is NaN" ], + "ImplicitFlagClobber": true, "DestSize": "4" } }, @@ -1520,6 +1536,7 @@ "NumElements": "RegisterSize / ElementSize" }, "FPR = VCMPEQZ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": { + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -1528,6 +1545,7 @@ "Each element is compared, if the result is true then the resulting element is ~0, else zero", "Compares the vector against zero" ], + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -1536,6 +1554,7 @@ "Each element is compared, if the result is true then the resulting element is ~0, else zero", "Compares the vector against zero" ], + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -1777,10 +1796,12 @@ }, "FPR = VFMin u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": { + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, "FPR = VFMax u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": { + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, @@ -1899,10 +1920,12 @@ "Each element is compared, if the result is true then the resulting element is ~0, else zero" ], + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, "FPR = VFCMPEQ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": { + "ImplicitFlagClobber": true, "DestSize": "RegisterSize", "NumElements": "RegisterSize / ElementSize" }, diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index c5fa2a28e..138823025 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -277,7 +277,8 @@ void ConstProp::CodeMotionAroundSelects(IREmitter *IREmit, const IRListView& Cur for (auto [BlockNode, BlockIROp] : CurrentIR.GetBlocks()) { auto BlockOp = BlockIROp->CW(); for (auto [UnaryOpNode, UnaryOpHdr] : CurrentIR.GetCode(BlockNode)) { - if (IR::GetArgs(UnaryOpHdr->Op) == 1 && !HasSideEffects(UnaryOpHdr->Op)) { + if (IR::GetArgs(UnaryOpHdr->Op) == 1 && !HasSideEffects(UnaryOpHdr->Op) + && !ImplicitFlagClobber(UnaryOpHdr->Op)) { // could be moved auto SelectOpNode = IREmit->UnwrapNode(UnaryOpHdr->Args[0]); auto SelectOpHdr = IREmit->GetOpHeader(UnaryOpHdr->Args[0]); diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h index 642b77c61..24277e956 100644 --- a/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/FEXCore/include/FEXCore/IR/IREmitter.h @@ -27,6 +27,8 @@ friend class FEXCore::IR::PassManager; ResetWorkingList(); } + virtual ~IREmitter() = default; + void ReownOrClaimBuffer() { DualListData.ReownOrClaimBuffer(); } @@ -332,6 +334,10 @@ friend class FEXCore::IR::PassManager; return Ptr; } + virtual void SaveNZCV() { + // Overriden by dispatcher, stubbed for IR tests + } + OrderedNode *CurrentWriteCursor = nullptr; // These could be combined with a little bit of work to be more efficient with memory usage. Isn't a big deal diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index da8e2dc9c..37fcab310 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1963,7 +1963,7 @@ ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 33, + "ExpectedInstructionCount": 31, "Optimal": "No", "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ @@ -1972,38 +1972,36 @@ "uxtb w22, w5", "and x22, x22, #0x1f", "mov w23, #0x10", - "sub x23, x23, x22", - "lsl x24, x21, x22", - "lsr w20, w20, w23", - "orr x20, x24, x20", + "sub x24, x23, x22", + "lsl x25, x21, x22", + "lsr w20, w20, w24", + "orr x20, x25, x20", "cmp x22, #0x0 (0)", "csel x20, x21, x20, eq", "bfxil x4, x20, #0, #16", - "cbz x22, #+0x54", "uxth x20, w20", - "ldr w23, [x28, #728]", - "lsl w24, w20, #16", - "tst w24, w24", - "mrs x24, nzcv", - "mov w25, #0x10", - "sub w25, w25, w22", - "lsr w25, w21, w25", - "ubfx w25, w25, #0, #1", - "orr w24, w24, w25, lsl #29", + "ldr w24, [x28, #728]", + "lsl w25, w20, #16", + "tst w25, w25", + "mrs x25, nzcv", + "sub w23, w23, w22", + "lsr w23, w21, w23", + "ubfx w23, w23, #0, #1", + "orr w23, w25, w23, lsl #29", "ldrb w25, [x28, #706]", "cmp x22, #0x0 (0)", "csel x25, x25, x20, eq", "strb w25, [x28, #706]", "eor w20, w21, w20", "ubfx w20, w20, #15, #1", - "orr w20, w24, w20, lsl #28", + "orr w20, w23, w20, lsl #28", "cmp x22, #0x0 (0)", - "csel w20, w23, w20, eq", + "csel w20, w24, w20, eq", "str w20, [x28, #728]" ] }, "shld eax, ebx, cl": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 30, "Optimal": "No", "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ @@ -2012,37 +2010,35 @@ "uxtb w22, w5", "and x22, x22, #0x1f", "mov w23, #0x20", - "sub x23, x23, x22", - "lsl x24, x21, x22", - "lsr w20, w20, w23", - "orr x20, x24, x20", + "sub x24, x23, x22", + "lsl x25, x21, x22", + "lsr w20, w20, w24", + "orr x20, x25, x20", "cmp x22, #0x0 (0)", "csel x20, x21, x20, eq", "mov w4, w20", - "cbz x22, #+0x50", "mov w20, w20", - "ldr w23, [x28, #728]", + "ldr w24, [x28, #728]", "tst w20, w20", - "mrs x24, nzcv", - "mov w25, #0x20", - "sub w25, w25, w22", - "lsr w25, w21, w25", - "ubfx w25, w25, #0, #1", - "orr w24, w24, w25, lsl #29", + "mrs x25, nzcv", + "sub w23, w23, w22", + "lsr w23, w21, w23", + "ubfx w23, w23, #0, #1", + "orr w23, w25, w23, lsl #29", "ldrb w25, [x28, #706]", "cmp x22, #0x0 (0)", "csel x25, x25, x20, eq", "strb w25, [x28, #706]", "eor w20, w21, w20", "lsr w20, w20, #31", - "orr w20, w24, w20, lsl #28", + "orr w20, w23, w20, lsl #28", "cmp x22, #0x0 (0)", - "csel w20, w23, w20, eq", + "csel w20, w24, w20, eq", "str w20, [x28, #728]" ] }, "shld rax, rbx, cl": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ @@ -2050,29 +2046,26 @@ "uxtb w21, w5", "and x21, x21, #0x3f", "mov w22, #0x40", - "sub x22, x22, x21", - "lsl x23, x20, x21", - "lsr x22, x7, x22", - "orr x22, x23, x22", + "sub x23, x22, x21", + "lsl x24, x20, x21", + "lsr x23, x7, x23", + "orr x23, x24, x23", "cmp x21, #0x0 (0)", - "csel x22, x20, x22, eq", - "mov x4, x22", - "cbz x21, #+0x4c", + "csel x4, x20, x23, eq", "ldr w23, [x28, #728]", - "tst x22, x22", + "tst x4, x4", "mrs x24, nzcv", - "mov w25, #0x40", - "sub x25, x25, x21", - "lsr x25, x20, x25", - "ubfx x25, x25, #0, #1", - "orr w24, w24, w25, lsl #29", - "ldrb w25, [x28, #706]", + "sub x22, x22, x21", + "lsr x22, x20, x22", + "ubfx x22, x22, #0, #1", + "orr w22, w24, w22, lsl #29", + "ldrb w24, [x28, #706]", "cmp x21, #0x0 (0)", - "csel x25, x25, x22, eq", - "strb w25, [x28, #706]", - "eor x20, x20, x22", + "csel x24, x24, x4, eq", + "strb w24, [x28, #706]", + "eor x20, x20, x4", "lsr x20, x20, #63", - "orr w20, w24, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "cmp x21, #0x0 (0)", "csel w20, w23, w20, eq", "str w20, [x28, #728]" diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 81b4c3f1e..d661ba9e4 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -1000,7 +1000,7 @@ ] }, "vpacksswb ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 1 0b01 0x63 256-bit" @@ -1013,14 +1013,18 @@ "splice z2.b, p6, z2.b, z1.b", "mov z1.d, z2.d[1]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[2]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpcmpgtb xmm0, xmm1, xmm2": { @@ -1104,7 +1108,7 @@ ] }, "vpackuswb ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 1 0b01 0x67 256-bit" @@ -1117,14 +1121,18 @@ "splice z2.b, p6, z2.b, z1.b", "mov z1.d, z2.d[1]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[2]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpshufd xmm0, xmm1, 00b": { @@ -1188,7 +1196,7 @@ ] }, "vpshufd ymm0, ymm1, 00b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" @@ -1196,42 +1204,58 @@ "ExpectedArm64ASM": [ "mov z1.s, s17", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpshufd ymm0, ymm1, 01b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" @@ -1239,42 +1263,58 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[1]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpshufd ymm0, ymm1, 10b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" @@ -1282,42 +1322,58 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[2]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpshufd ymm0, ymm1, 11b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" @@ -1325,38 +1381,54 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[3]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpshufhw xmm0, xmm1, 00b": { @@ -1420,7 +1492,7 @@ ] }, "vpshufhw ymm0, ymm1, 00b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" @@ -1428,42 +1500,58 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[4]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #7", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshufhw ymm0, ymm1, 01b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" @@ -1471,42 +1559,58 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[5]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[13]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #7", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshufhw ymm0, ymm1, 10b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" @@ -1514,42 +1618,58 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[6]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[14]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #7", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshufhw ymm0, ymm1, 11b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" @@ -1557,38 +1677,54 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[7]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[15]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #7", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshuflw xmm0, xmm1, 00b": { @@ -1652,7 +1788,7 @@ ] }, "vpshuflw ymm0, ymm1, 00b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" @@ -1660,42 +1796,58 @@ "ExpectedArm64ASM": [ "mov z1.h, h17", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-8", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #0", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-7", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #3", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshuflw ymm0, ymm1, 01b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" @@ -1703,42 +1855,58 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[1]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-8", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[9]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #0", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-7", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #3", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshuflw ymm0, ymm1, 10b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" @@ -1746,42 +1914,58 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[2]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-8", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[10]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #0", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-7", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #3", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpshuflw ymm0, ymm1, 11b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" @@ -1789,38 +1973,54 @@ "ExpectedArm64ASM": [ "mov z1.h, z17.h[3]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-8", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[11]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #0", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-7", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, h17", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[8]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #3", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpcmpeqb xmm0, xmm1, xmm2": { @@ -2659,7 +2859,7 @@ ] }, "vshufps ymm0, ymm1, ymm2, 00b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" @@ -2667,38 +2867,54 @@ "ExpectedArm64ASM": [ "mov z1.s, s17", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vshufps xmm0, xmm1, xmm2, 01b": { @@ -2714,7 +2930,7 @@ ] }, "vshufps ymm0, ymm1, ymm2, 01b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" @@ -2722,38 +2938,54 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[1]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vshufps xmm0, xmm1, xmm2, 10b": { @@ -2769,7 +3001,7 @@ ] }, "vshufps ymm0, ymm1, ymm2, 10b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" @@ -2777,38 +3009,54 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[2]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vshufps xmm0, xmm1, xmm2, 11b": { @@ -2824,7 +3072,7 @@ ] }, "vshufps ymm0, ymm1, ymm2, 11b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" @@ -2832,38 +3080,54 @@ "ExpectedArm64ASM": [ "mov z1.s, z17.s[3]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vshufpd xmm0, xmm1, xmm2, 0b": { @@ -2877,7 +3141,7 @@ ] }, "vshufpd ymm0, ymm1, ymm2, 0b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 256-bit" @@ -2885,22 +3149,30 @@ "ExpectedArm64ASM": [ "mov z1.d, d17", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vshufpd xmm0, xmm1, xmm2, 1b": { @@ -2914,7 +3186,7 @@ ] }, "vshufpd ymm0, ymm1, ymm2, 1b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 256-bit" @@ -2922,22 +3194,30 @@ "ExpectedArm64ASM": [ "mov z1.d, z17.d[1]", "mov z2.d, z17.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vmovaps xmm0, [rax]": { @@ -4028,7 +4308,7 @@ ] }, "vpackssdw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 1 0b01 0x6b 256-bit" @@ -4041,14 +4321,18 @@ "splice z2.h, p6, z2.h, z1.h", "mov z1.d, z2.d[1]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[2]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpunpcklqdq xmm0, xmm1, xmm2": { @@ -4171,7 +4455,7 @@ ] }, "vhaddpd ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 1 0b01 0x7c 256-bit" @@ -4184,14 +4468,18 @@ "splice z2.d, p6, z2.d, z1.d", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vhaddps xmm0, xmm1, xmm2": { @@ -4205,7 +4493,7 @@ ] }, "vhaddps ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 1 0b11 0x7c 256-bit" @@ -4218,14 +4506,18 @@ "splice z2.d, p6, z2.d, z1.d", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vhsubpd xmm0, xmm1, xmm2": { @@ -4241,7 +4533,7 @@ ] }, "vhsubpd ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 1 0b01 0x7d 256-bit" @@ -4252,14 +4544,18 @@ "fsub z2.d, z2.d, z3.d", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vhsubps xmm0, xmm1, xmm2": { @@ -4275,7 +4571,7 @@ ] }, "vhsubps ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 1 0b11 0x7d 256-bit" @@ -4286,14 +4582,18 @@ "fsub z2.s, z2.s, z3.s", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vmovd dword [rax], xmm0": { @@ -5437,7 +5737,7 @@ ] }, "vpsadbw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 37, "Optimal": "No", "Comment": [ "Map 1 0b01 0xf6 256-bit" @@ -5457,23 +5757,29 @@ "addv h2, v2.8h", "addv h3, v3.8h", "mov z1.d, d3", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.q, q2", "mov z2.d, z4.d", "not p0.b, p7/z, p6.b", "mov z2.b, p0/m, z1.b", "mov z1.d, z2.d[1]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[2]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vmaskmovdqu xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 6545a7654..dd187daf1 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -52,7 +52,7 @@ ] }, "vphaddw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 2 0b01 0x01 256-bit" @@ -65,14 +65,18 @@ "splice z2.d, p6, z2.d, z1.d", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vphaddd xmm0, xmm1, xmm2": { @@ -86,7 +90,7 @@ ] }, "vphaddd ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 2 0b01 0x02 256-bit" @@ -99,14 +103,18 @@ "splice z2.d, p6, z2.d, z1.d", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vphaddsw xmm0, xmm1, xmm2": { @@ -122,7 +130,7 @@ ] }, "vphaddsw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 2 0b01 0x03 256-bit" @@ -133,14 +141,18 @@ "sqadd z2.h, z2.h, z3.h", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpmaddubsw xmm0, xmm1, xmm2": { @@ -192,7 +204,7 @@ ] }, "vphsubw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 2 0b01 0x05 256-bit" @@ -203,14 +215,18 @@ "sub z2.h, z2.h, z3.h", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vphsubd xmm0, xmm1, xmm2": { @@ -226,7 +242,7 @@ ] }, "vphsubd ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 2 0b01 0x06 256-bit" @@ -237,14 +253,18 @@ "sub z2.s, z2.s, z3.s", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vphsubsw xmm0, xmm1, xmm2": { @@ -260,7 +280,7 @@ ] }, "vphsubsw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "Map 2 0b01 0x07 256-bit" @@ -271,14 +291,18 @@ "sqsub z2.h, z2.h, z3.h", "mov z1.d, z2.d[2]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[1]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpsignb xmm0, xmm1, xmm2": { @@ -1060,7 +1084,7 @@ ] }, "vpackusdw ymm0, ymm1, ymm2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "Map 2 0b01 0x2b 256-bit" @@ -1073,14 +1097,18 @@ "splice z2.h, p6, z2.h, z1.h", "mov z1.d, z2.d[1]", "mov z3.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z3.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z2.d[2]", "mov z16.d, z3.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vmaskmovps xmm0, xmm1, [rax]": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 0dff7ab78..bed794313 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -331,7 +331,7 @@ ] }, "vpblendd ymm0, ymm1, 01010101b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" @@ -339,42 +339,58 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[7]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpblendd ymm0, ymm1, 10101010b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" @@ -382,38 +398,54 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, s16", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z16.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpblendd ymm0, ymm1, 11111111b": { @@ -487,7 +519,7 @@ ] }, "vpermilps ymm0, ymm1, 00000000b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" @@ -495,42 +527,58 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s17", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpermilps ymm0, ymm1, 01010101b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" @@ -538,42 +586,58 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpermilps ymm0, ymm1, 10101010b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" @@ -581,42 +645,58 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpermilps ymm0, ymm1, 11111111b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" @@ -624,38 +704,54 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[7]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vpermilpd xmm0, xmm1, 00b": { @@ -711,7 +807,7 @@ ] }, "vpermilpd ymm0, ymm1, 0000b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -719,26 +815,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0001b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -746,26 +850,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0010b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -773,26 +885,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0011b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -800,26 +920,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0100b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -827,26 +955,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0101b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -854,26 +990,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0110b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -881,26 +1025,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 0111b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -908,26 +1060,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1000b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -935,26 +1095,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1001b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -962,26 +1130,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1010b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -989,26 +1165,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1011b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -1016,26 +1200,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1100b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -1043,26 +1235,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1101b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -1070,26 +1270,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1110b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -1097,26 +1305,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vpermilpd ymm0, ymm1, 1111b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" @@ -1124,22 +1340,30 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vperm2f128 ymm0, ymm1, ymm2, 00000000b": { @@ -1912,7 +2136,7 @@ ] }, "vblendps ymm0, ymm1, ymm2, 10000001b": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 50, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 256-bit" @@ -1920,38 +2144,54 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.s, s18", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[1]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[2]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[3]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[4]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[5]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z17.s[6]", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, z18.s[7]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vblendps ymm0, ymm1, ymm2, 11111111b": { @@ -2021,7 +2261,7 @@ ] }, "vblendpd ymm0, ymm1, ymm2, 0001b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2029,26 +2269,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0010b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2056,26 +2304,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0011b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2083,26 +2339,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0100b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2110,26 +2374,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0101b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2137,26 +2409,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0110b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2164,26 +2444,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 0111b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2191,26 +2479,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1000b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2218,26 +2514,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1001b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2245,26 +2549,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1010b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2272,26 +2584,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1011b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2299,26 +2619,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1100b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2326,26 +2654,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1101b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2353,26 +2689,34 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d18", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z17.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1110b": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" @@ -2380,22 +2724,30 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.d, d17", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-2", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[1]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #-1", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[2]", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #0", "mov z2.d, p0/m, z1.d", + "msr nzcv, x0", "mov z1.d, z18.d[3]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.d, #-2, #1", "cmpeq p0.d, p7/z, z0.d, #1", - "mov z16.d, p0/m, z1.d" + "mov z16.d, p0/m, z1.d", + "msr nzcv, x0" ] }, "vblendpd ymm0, ymm1, ymm2, 1111b": { @@ -2458,7 +2810,7 @@ ] }, "vpblendw ymm0, ymm1, ymm2, 00000001b": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 98, "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" @@ -2466,70 +2818,102 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "mov z1.h, h18", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-8", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[1]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-7", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[2]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[3]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[4]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[5]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[6]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[7]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #-1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z18.h[8]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #0", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[9]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #1", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[10]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #2", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[11]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #3", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[12]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #4", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[13]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #5", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[14]", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #6", "mov z2.h, p0/m, z1.h", + "msr nzcv, x0", "mov z1.h, z17.h[15]", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.h, #-8, #1", "cmpeq p0.h, p7/z, z0.h, #7", - "mov z16.h, p0/m, z1.h" + "mov z16.h, p0/m, z1.h", + "msr nzcv, x0" ] }, "vpblendw ymm0, ymm1, ymm2, 11111111b": { @@ -3196,7 +3580,7 @@ ] }, "vdpps ymm0, ymm1, ymm2, 00001111b": { - "ExpectedInstructionCount": 77, + "ExpectedInstructionCount": 109, "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" @@ -3205,37 +3589,53 @@ "movi v2.2d, #0x0", "fmul z3.s, z17.s, z18.s", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s2", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", "mov z3.s, p0/m, z1.s", + "msr nzcv, x0", "movprfx z0, z3", "faddp z0.s, p7/m, z0.s, z2.s", "uzp1 z3.s, z0.s, z0.s", @@ -3247,38 +3647,54 @@ "uzp2 z1.s, z0.s, z0.s", "splice z3.d, p6, z3.d, z1.d", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vdpps ymm0, ymm1, ymm2, 11110000b": { @@ -3292,7 +3708,7 @@ ] }, "vdpps ymm0, ymm1, ymm2, 11111111b": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 61, "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" @@ -3311,38 +3727,54 @@ "uzp2 z1.s, z0.s, z0.s", "splice z3.d, p6, z3.d, z1.d", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-4", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-3", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #-1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #0", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #1", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #2", "mov z2.s, p0/m, z1.s", + "msr nzcv, x0", "mov z1.s, s3", "mov z16.d, z2.d", + "mrs x0, nzcv", "index z0.s, #-4, #1", "cmpeq p0.s, p7/z, z0.s, #3", - "mov z16.s, p0/m, z1.s" + "mov z16.s, p0/m, z1.s", + "msr nzcv, x0" ] }, "vdppd xmm0, xmm1, xmm2, 00000000b": {