From d99bcbf01b741682253cedba4a12f91aac13cff9 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Wed, 23 Aug 2023 12:45:45 -0400 Subject: [PATCH] OpcodeDispatcher: Remove unnecessary moves from AVXExtendVectorElements Zero-extension will already occur if necessary upon storing. Also we can join the AVX and SSE implementations together and get rid of some template instantiations, now that the only differing behavior is removed. --- .../Interface/Core/OpcodeDispatcher.cpp | 24 ++++++------ .../Source/Interface/Core/OpcodeDispatcher.h | 3 -- .../Core/OpcodeDispatcher/Vector.cpp | 39 ------------------- unittests/InstructionCountCI/VEX_map2.json | 36 ++++++----------- 4 files changed, 24 insertions(+), 78 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 91b214c3c..8a653a72d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -6068,12 +6068,12 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x1D), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, {OPD(2, 0b01, 0x1E), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, - {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, - {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, - {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, - {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>}, - {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>}, - {OPD(2, 0b01, 0x25), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>}, + {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, true>}, + {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, true>}, + {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, true>}, + {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, true>}, + {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, true>}, + {OPD(2, 0b01, 0x25), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, true>}, {OPD(2, 0b01, 0x28), 1, &OpDispatchBuilder::VPMULLOp<4, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, @@ -6084,12 +6084,12 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x2E), 1, &OpDispatchBuilder::VMASKMOVOp<4, true>}, {OPD(2, 0b01, 0x2F), 1, &OpDispatchBuilder::VMASKMOVOp<8, true>}, - {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, - {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, - {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, - {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>}, - {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>}, - {OPD(2, 0b01, 0x35), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>}, + {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, false>}, + {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, false>}, + {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, false>}, + {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, false>}, + {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, false>}, + {OPD(2, 0b01, 0x35), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, false>}, {OPD(2, 0b01, 0x36), 1, &OpDispatchBuilder::VPERMDOp}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index edefb37c0..4cd54ac6a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -421,9 +421,6 @@ public: template void AVXVectorUnaryOp(OpcodeArgs); - template - void AVXExtendVectorElements(OpcodeArgs); - template void AVXVectorRound(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7d8052ef0..55c6f7487 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -3684,45 +3684,6 @@ void OpDispatchBuilder::ExtendVectorElements<2, 8, true>(OpcodeArgs); template void OpDispatchBuilder::ExtendVectorElements<4, 8, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements(OpcodeArgs) { - const auto DstSize = GetDstSize(Op); - const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE; - - OrderedNode *Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed); - - if (Is128Bit) { - Result = _VMov(16, Result); - } - StoreResult(FPRClass, Op, Result, -1); -} - -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>(OpcodeArgs); - -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>(OpcodeArgs); -template -void OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>(OpcodeArgs); - OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { const auto Size = GetDstSize(Op); diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 4e93d7b22..608eb40f6 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1011,7 +1011,7 @@ ] }, "vpmovsxbw xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x20 128-bit" @@ -1020,7 +1020,6 @@ "mov z4.d, p7/m, z17.d", "sxtl v4.8h, v4.8b", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1037,7 +1036,7 @@ ] }, "vpmovsxbd xmm0, xmm1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x21 128-bit" @@ -1047,7 +1046,6 @@ "sxtl v4.8h, v4.8b", "sxtl v4.4s, v4.4h", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1065,7 +1063,7 @@ ] }, "vpmovsxbq xmm0, xmm1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": [ "Map 2 0b01 0x22 128-bit" @@ -1076,7 +1074,6 @@ "sxtl v4.4s, v4.4h", "sxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1095,7 +1092,7 @@ ] }, "vpmovsxwd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x23 128-bit" @@ -1104,7 +1101,6 @@ "mov z4.d, p7/m, z17.d", "sxtl v4.4s, v4.4h", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1121,7 +1117,7 @@ ] }, "vpmovsxwq xmm0, xmm1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x24 128-bit" @@ -1131,7 +1127,6 @@ "sxtl v4.4s, v4.4h", "sxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1149,7 +1144,7 @@ ] }, "vpmovsxdq xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x25 128-bit" @@ -1158,7 +1153,6 @@ "mov z4.d, p7/m, z17.d", "sxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1413,7 +1407,7 @@ ] }, "vpmovzxbw xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x30 128-bit" @@ -1422,7 +1416,6 @@ "mov z4.d, p7/m, z17.d", "uxtl v4.8h, v4.8b", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1439,7 +1432,7 @@ ] }, "vpmovzxbd xmm0, xmm1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x31 128-bit" @@ -1449,7 +1442,6 @@ "uxtl v4.8h, v4.8b", "uxtl v4.4s, v4.4h", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1467,7 +1459,7 @@ ] }, "vpmovzxbq xmm0, xmm1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": [ "Map 2 0b01 0x32 128-bit" @@ -1478,7 +1470,6 @@ "uxtl v4.4s, v4.4h", "uxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1497,7 +1488,7 @@ ] }, "vpmovzxwd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x33 128-bit" @@ -1506,7 +1497,6 @@ "mov z4.d, p7/m, z17.d", "uxtl v4.4s, v4.4h", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1523,7 +1513,7 @@ ] }, "vpmovzxwq xmm0, xmm1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x34 128-bit" @@ -1533,7 +1523,6 @@ "uxtl v4.4s, v4.4h", "uxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, @@ -1551,7 +1540,7 @@ ] }, "vpmovzxdq xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 2 0b01 0x35 128-bit" @@ -1560,7 +1549,6 @@ "mov z4.d, p7/m, z17.d", "uxtl v4.2d, v4.2s", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] },