From fc3863f444f54b5e1b81d3e03ed4d305e031bc80 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Sat, 4 Feb 2023 00:48:52 -0500 Subject: [PATCH 1/3] ARMEmitter: Handle ADDVL --- .../Core/ArchHelpers/CodeEmitter/SVEOps.inl | 17 ++++++++++++++++- .../FEXCore/unittests/Emitter/SVE_Tests.cpp | 4 +++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index b7c30016b..7de3da683 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -1347,7 +1347,10 @@ public: // SVE Stack Allocation // SVE stack frame adjustment - // XXX: + void addvl(XRegister rd, XRegister rn, int32_t imm) { + SVEStackFrameOperation(0b00, rd, rn, imm); + } + // Streaming SVE stack frame adjustment // XXX: // SVE stack frame size @@ -4084,6 +4087,18 @@ private: dc32(Instr); } + void SVEStackFrameOperation(uint32_t opc, XRegister rd, XRegister rn, int32_t imm) { + LOGMAN_THROW_AA_FMT(imm >= -32 && imm <= 31, + "Stack frame operation immediate must be within -32 to 31"); + + uint32_t Instr = 0b0000'0100'0010'0000'0101'0000'0000'0000; + Instr |= opc << 22; + Instr |= rn.Idx() << 16; + Instr |= (static_cast(imm) & 0b111111) << 5; + Instr |= rd.Idx(); + dc32(Instr); + } + // SVE floating-point round to integral value void frintX(uint32_t opc, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { // opc = round mode diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index fc3662736..d244db794 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -889,7 +889,9 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE Index Generation") { // TODO: Implement in emitter. } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE stack frame adjustment") { - // TODO: Implement in emitter. + TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, -32), "addvl sp, sp, #-32"); + TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, 31), "addvl sp, sp, #31"); + TEST_SINGLE(addvl(XReg::x30, XReg::x29, 15), "addvl x30, x29, #15"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Streaming SVE stack frame adjustment") { // TODO: Implement in emitter. From 600e8749d7d8831ea954729ff08755f2e88a16c5 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Sat, 4 Feb 2023 01:04:00 -0500 Subject: [PATCH 2/3] ARMEmitter: Handle ADDPL --- .../Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 3 +++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 7de3da683..78d8ac2c9 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -1350,6 +1350,9 @@ public: void addvl(XRegister rd, XRegister rn, int32_t imm) { SVEStackFrameOperation(0b00, rd, rn, imm); } + void addpl(XRegister rd, XRegister rn, int32_t imm) { + SVEStackFrameOperation(0b01, rd, rn, imm); + } // Streaming SVE stack frame adjustment // XXX: diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index d244db794..e3d76c9ff 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -890,8 +890,12 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE Index Generation") { } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE stack frame adjustment") { TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, -32), "addvl sp, sp, #-32"); - TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, 31), "addvl sp, sp, #31"); - TEST_SINGLE(addvl(XReg::x30, XReg::x29, 15), "addvl x30, x29, #15"); + TEST_SINGLE(addvl(XReg::rsp, XReg::rsp, 31), "addvl sp, sp, #31"); + TEST_SINGLE(addvl(XReg::x30, XReg::x29, 15), "addvl x30, x29, #15"); + + TEST_SINGLE(addpl(XReg::rsp, XReg::rsp, -32), "addpl sp, sp, #-32"); + TEST_SINGLE(addpl(XReg::rsp, XReg::rsp, 31), "addpl sp, sp, #31"); + TEST_SINGLE(addpl(XReg::x30, XReg::x29, 15), "addpl x30, x29, #15"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Streaming SVE stack frame adjustment") { // TODO: Implement in emitter. From 75bc997ab75ab680a680bab7b0f56998e4091e46 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Sat, 4 Feb 2023 01:06:36 -0500 Subject: [PATCH 3/3] ARMEmitter: Handle RDVL --- .../Core/ArchHelpers/CodeEmitter/SVEOps.inl | 12 +++++++++--- External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 4 +++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 78d8ac2c9..a32a3aed8 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -1354,11 +1354,17 @@ public: SVEStackFrameOperation(0b01, rd, rn, imm); } - // Streaming SVE stack frame adjustment + // Streaming SVE stack frame adjustment (SME) // XXX: + // SVE stack frame size - // XXX: - // Streaming SVE stack frame size + void rdvl(XRegister rd, int32_t imm) { + // Would-be Rn field is just set to all 1's, which is the same + // as writing the encoding for the SP into it. + SVEStackFrameOperation(0b10, rd, XReg::rsp, imm); + } + + // Streaming SVE stack frame size (SME) // XXX: // SVE2 Integer Multiply - Unpredicated diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index e3d76c9ff..c398a812c 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -901,7 +901,9 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Streaming SVE stack frame adju // TODO: Implement in emitter. } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE stack frame size") { - // TODO: Implement in emitter. + TEST_SINGLE(rdvl(XReg::x30, -32), "rdvl x30, #-32"); + TEST_SINGLE(rdvl(XReg::x30, 31), "rdvl x30, #31"); + TEST_SINGLE(rdvl(XReg::x30, 15), "rdvl x30, #15"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Streaming SVE stack frame size") { // TODO: Implement in emitter.