From d7c2b8f513b0fb273bfef87d5d56cd19c9b4a666 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 7 Jan 2026 12:20:09 -0800 Subject: [PATCH] FEXCore: Cleanup pointers structure There's no longer a distinction between AArch64 and x86 and everything effectively falls under "Common" now. This means flattening the entire structure just cleans it up. NFC. (Although instcountCI will update because of a couple pointer offsets changing) --- FEXCore/Source/Interface/Core/CPUBackend.cpp | 22 ++-- FEXCore/Source/Interface/Core/Core.cpp | 4 +- .../Interface/Core/Dispatcher/Dispatcher.cpp | 46 ++++---- FEXCore/Source/Interface/Core/JIT/ALUOps.cpp | 4 +- .../Source/Interface/Core/JIT/AtomicOps.cpp | 2 +- .../Source/Interface/Core/JIT/BranchOps.cpp | 20 ++-- FEXCore/Source/Interface/Core/JIT/JIT.cpp | 102 +++++++++-------- FEXCore/Source/Interface/Core/JIT/MiscOps.cpp | 14 +-- .../Source/Interface/Core/JIT/VectorOps.cpp | 8 +- FEXCore/include/FEXCore/Core/CoreState.h | 103 +++++++----------- Source/Windows/ARM64EC/Module.cpp | 6 +- 11 files changed, 152 insertions(+), 179 deletions(-) diff --git a/FEXCore/Source/Interface/Core/CPUBackend.cpp b/FEXCore/Source/Interface/Core/CPUBackend.cpp index a5aa13f68..8450860a6 100644 --- a/FEXCore/Source/Interface/Core/CPUBackend.cpp +++ b/FEXCore/Source/Interface/Core/CPUBackend.cpp @@ -277,37 +277,37 @@ namespace CPU { : ThreadState(ThreadState) , CodeBuffers(CodeBuffers) { - auto& Common = ThreadState->CurrentFrame->Pointers.Common; + auto& Ptrs = ThreadState->CurrentFrame->Pointers; // Initialize named vector constants. for (size_t i = 0; i < FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX; ++i) { - Common.NamedVectorConstantPointers[i] = reinterpret_cast(NamedVectorConstants[i]); + Ptrs.NamedVectorConstantPointers[i] = reinterpret_cast(NamedVectorConstants[i]); } // Copy named vector constants. - memcpy(Common.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants)); + memcpy(Ptrs.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants)); // Initialize Indexed named vector constants. - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] = reinterpret_cast(PSHUFLW_LUT.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] = reinterpret_cast(PSHUFHW_LUT.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] = reinterpret_cast(PSHUFD_LUT.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] = reinterpret_cast(SHUFPS_LUT.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] = reinterpret_cast(DPPS_MASK.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] = reinterpret_cast(DPPD_MASK.data()); - Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] = + Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] = reinterpret_cast(PBLENDW_LUT.data()); #ifndef FEX_DISABLE_TELEMETRY // Fill in telemetry values for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) { auto& Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast(i)); - Common.TelemetryValueAddresses[i] = reinterpret_cast(&Telem); + Ptrs.TelemetryValueAddresses[i] = reinterpret_cast(&Telem); } #endif } diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index 21fdc83ef..012470665 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -364,7 +364,7 @@ void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState* Thread, uin void ContextImpl::ExecuteThread(FEXCore::Core::InternalThreadState* Thread) { // Update the thread pointer for Thunk return to the latest. - Thread->CurrentFrame->Pointers.AArch64.ThunkCallbackRet = SignalDelegation->GetThunkCallbackRET(); + Thread->CurrentFrame->Pointers.ThunkCallbackRet = SignalDelegation->GetThunkCallbackRET(); Dispatcher->ExecuteDispatch(Thread->CurrentFrame); @@ -382,7 +382,7 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread) Thread->CurrentFrame->State.L1Pointer = Thread->LookupCache->GetL1Pointer(); Thread->CurrentFrame->State.L1Mask = Thread->LookupCache->GetScaledL1PointerMask(); - Thread->CurrentFrame->Pointers.Common.L2Pointer = Thread->LookupCache->GetPagePointer(); + Thread->CurrentFrame->Pointers.L2Pointer = Thread->LookupCache->GetPagePointer(); Dispatcher->InitThreadPointers(Thread); diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp index e67fdd64d..5cf024c4f 100644 --- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp +++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp @@ -165,7 +165,7 @@ void Dispatcher::EmitDispatcher() { add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0); mov(EC_CALL_CHECKER_PC_REG, RipReg); - ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC)); + ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionEC)); br(TMP2); (void)Bind(&l_NotECCode); @@ -181,7 +181,7 @@ void Dispatcher::EmitDispatcher() { } else { // This is the block cache lookup routine // It matches what is going on it LookupCache.h::FindBlock - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.L2Pointer)); // Mask the address by the virtual address size so we can check for aliases uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize; @@ -291,7 +291,7 @@ void Dispatcher::EmitDispatcher() { mov(ARMEmitter::XReg::x0, STATE); mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink)); + ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionLink)); if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] { GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); } else { @@ -488,7 +488,7 @@ void Dispatcher::EmitDispatcher() { // Now push the callback return trampoline to the guest stack // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host - ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.AArch64.ThunkCallbackRet)); + ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.ThunkCallbackRet)); ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP])); sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, CTX->Config.Is64BitMode ? 16 : 12); @@ -544,8 +544,8 @@ void Dispatcher::EmitDispatcher() { return Address; }; - LUDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV)); - LDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV)); + LUDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.LUDIV)); + LDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.LDIV)); // Interpreter fallbacks { @@ -1086,27 +1086,25 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) { void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread) { // Setup dispatcher specific pointers that need to be accessed from JIT code { - auto& Common = Thread->CurrentFrame->Pointers.Common; + auto& Ptrs = Thread->CurrentFrame->Pointers; - Common.DispatcherLoopTop = AbsoluteLoopTopAddress; - Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA; - Common.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC; - Common.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA; - Common.ExitFunctionLinker = ExitFunctionLinkerAddress; - Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA; - Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA; - Common.GuestSignal_SIGILL = GuestSignal_SIGILL; - Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP; - Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV; - Common.SignalReturnHandler = SignalHandlerReturnAddress; - Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT; - - auto& AArch64 = Thread->CurrentFrame->Pointers.AArch64; - AArch64.LUDIVHandler = LUDIVHandlerAddress; - AArch64.LDIVHandler = LDIVHandlerAddress; + Ptrs.DispatcherLoopTop = AbsoluteLoopTopAddress; + Ptrs.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA; + Ptrs.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC; + Ptrs.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA; + Ptrs.ExitFunctionLinker = ExitFunctionLinkerAddress; + Ptrs.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA; + Ptrs.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA; + Ptrs.GuestSignal_SIGILL = GuestSignal_SIGILL; + Ptrs.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP; + Ptrs.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV; + Ptrs.SignalReturnHandler = SignalHandlerReturnAddress; + Ptrs.SignalReturnHandlerRT = SignalHandlerReturnAddressRT; + Ptrs.LUDIVHandler = LUDIVHandlerAddress; + Ptrs.LDIVHandler = LDIVHandlerAddress; // Fill in the fallback handlers - InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers, &ABIPointers[0]); + InterpreterOps::FillFallbackIndexPointers(Ptrs.FallbackHandlerPointers, &ABIPointers[0]); } } diff --git a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp index bb5dea401..93974b2d7 100644 --- a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp @@ -924,7 +924,7 @@ DEF_OP(Div) { mov(EmitSize, TMP2, Lower); mov(EmitSize, TMP3, Divisor); - ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler)); + ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.LDIVHandler)); str(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16); blr(TMP4); @@ -1007,7 +1007,7 @@ DEF_OP(UDiv) { mov(EmitSize, TMP2, Lower); mov(EmitSize, TMP3, Divisor); - ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler)); + ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.LUDIVHandler)); str(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16); blr(TMP4); diff --git a/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp index e819e8161..aec8ab63f 100644 --- a/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp @@ -329,7 +329,7 @@ DEF_OP(TelemetrySetValue) { auto Op = IROp->C(); auto Src = GetReg(Op->Value); - ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.TelemetryValueAddresses[Op->TelemetryValueIndex])); + ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.TelemetryValueAddresses[Op->TelemetryValueIndex])); // Cortex fuses cmp+cset. cmp(ARMEmitter::Size::i32Bit, Src, 0); diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp index 1882f3fa5..d8afba697 100644 --- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp @@ -61,7 +61,7 @@ DEF_OP(ExitFunction) { str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp)); add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0); InsertGuestRIPMove(EC_CALL_CHECKER_PC_REG, NewRIP); - ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC)); + ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionEC)); br(TMP2); } else { #endif @@ -152,7 +152,7 @@ DEF_OP(ExitFunction) { (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset); InsertGuestRIPMove(TMP1, NewRIP); str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); - ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)); + ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.DispatcherLoopTop)); blr(TMP2); (void)Bind(&TFUnset); } @@ -186,7 +186,7 @@ DEF_OP(ExitFunction) { // Note: sub+cbnz used over cmp+br to preserve flags. sub(TMP1, TMP1, RipReg.X()); (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup); - ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)); + ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.DispatcherLoopTop)); str(RipReg.X(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); (void)Bind(&SkipFullLookup); @@ -283,8 +283,8 @@ DEF_OP(Syscall) { str(GetReg(Op->Header.Args[i]).X(), ARMEmitter::Reg::rsp, i * 8); } - ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj)); - ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc)); + ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerObj)); + ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerFunc)); mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, STATE.R()); // SP supporting move @@ -400,7 +400,7 @@ DEF_OP(ThreadRemoveCodeEntry) { // TODO: Relocations don't seem to be wired up to this...? LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry, CPU::Arm64Emitter::PadType::AUTOPAD); - ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)); + ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.ThreadRemoveCodeEntryFromJIT)); if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] { GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); } else { @@ -425,8 +425,8 @@ DEF_OP(CPUID) { // x0 = CPUID Handler // x1 = CPUID Function // x2 = CPUID Leaf - ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)); - ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction)); + ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDObj)); + ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDFunction)); if (!TMP_ABIARGS) { mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, TMP2); @@ -466,8 +466,8 @@ DEF_OP(XGetBV) { // x0 = CPUID Handler // x1 = XCR Function - ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)); - ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction)); + ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDObj)); + ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.XCRFunction)); if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] { GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); } else { diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp index 0cba350de..cadf8104e 100644 --- a/FEXCore/Source/Interface/Core/JIT/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp @@ -133,8 +133,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); fmov(VTMP1.S(), Src1.S()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -151,8 +151,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); fmov(VTMP1.D(), Src1.D()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -176,8 +176,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { mov(ARMEmitter::Size::i32Bit, TMP2, Src1); } - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -194,8 +194,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -212,8 +212,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -230,8 +230,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); fmov(VTMP1.D(), Src1.D()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -254,8 +254,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { fmov(VTMP1.D(), Src1.D()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -276,8 +276,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { fmov(VTMP1.D(), Src1.D()); fmov(VTMP2.D(), Src2.D()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -294,8 +294,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -312,8 +312,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -330,8 +330,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -351,8 +351,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { mov(VTMP1.Q(), Src1.Q()); mov(VTMP2.Q(), Src2.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -369,8 +369,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { const auto Src1 = GetVReg(IROp->Args[0]); mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -394,8 +394,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { mov(VTMP1.Q(), Src1.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -416,8 +416,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { mov(VTMP1.Q(), Src1.Q()); mov(VTMP2.Q(), Src2.Q()); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP1); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -434,8 +434,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { // tmp2 (x1/x11): source 2 // tmp3 (x2/x12): source 3 const auto Op = IROp->C(); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); stp(TMP1, ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16); @@ -476,8 +476,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) { mov(VTMP2.Q(), Src2.Q()); movz(ARMEmitter::Size::i32Bit, TMP1, Control); - ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); - ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func)); + ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler)); + ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func)); blr(TMP2); ldr(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16); @@ -533,7 +533,7 @@ uint64_t Arm64JITCore::ExitFunctionLink(FEXCore::Core::CpuStateFrame* Frame, FEX if (TFSet) { // If TF is set, the cache must be skipped as different code needs to be generated. Frame->State.rip = GuestRip; - return Frame->Pointers.Common.DispatcherLoopTop; + return Frame->Pointers.DispatcherLoopTop; } else { { // Guard the LookupCache lock with the code invalidation mutex, to avoid issues with forking @@ -632,36 +632,32 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In // Set up pointers that the JIT needs to load // Common - auto& Common = ThreadState->CurrentFrame->Pointers.Common; + auto& Ptrs = ThreadState->CurrentFrame->Pointers; - Common.PrintValue = reinterpret_cast(PrintValue); - Common.PrintVectorValue = reinterpret_cast(PrintVectorValue); - Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit); - Common.MonoBackpatcherWrite = reinterpret_cast(&Context::ContextImpl::MonoBackpatcherWrite); - Common.CPUIDObj = reinterpret_cast(&CTX->CPUID); + Ptrs.PrintValue = reinterpret_cast(PrintValue); + Ptrs.PrintVectorValue = reinterpret_cast(PrintVectorValue); + Ptrs.ThreadRemoveCodeEntryFromJIT = reinterpret_cast(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit); + Ptrs.MonoBackpatcherWrite = reinterpret_cast(&Context::ContextImpl::MonoBackpatcherWrite); + Ptrs.CPUIDObj = reinterpret_cast(&CTX->CPUID); { FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction); - Common.CPUIDFunction = PMF.GetConvertedPointer(); + Ptrs.CPUIDFunction = PMF.GetConvertedPointer(); } { FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction); - Common.XCRFunction = PMF.GetConvertedPointer(); + Ptrs.XCRFunction = PMF.GetConvertedPointer(); } { FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::HLE::SyscallHandler::HandleSyscall); - Common.SyscallHandlerObj = reinterpret_cast(CTX->SyscallHandler); - Common.SyscallHandlerFunc = PMF.GetVTableEntry(CTX->SyscallHandler); + Ptrs.SyscallHandlerObj = reinterpret_cast(CTX->SyscallHandler); + Ptrs.SyscallHandlerFunc = PMF.GetVTableEntry(CTX->SyscallHandler); } - Common.ExitFunctionLink = reinterpret_cast(&Arm64JITCore::ExitFunctionLink); - - // Platform Specific - auto& AArch64 = ThreadState->CurrentFrame->Pointers.AArch64; - - AArch64.LUDIV = reinterpret_cast(LUDIV); - AArch64.LDIV = reinterpret_cast(LDIV); + Ptrs.ExitFunctionLink = reinterpret_cast(&Arm64JITCore::ExitFunctionLink); + Ptrs.LUDIV = reinterpret_cast(LUDIV); + Ptrs.LDIV = reinterpret_cast(LDIV); } CurrentCodeBuffer = CodeBuffers.GetLatest(); @@ -760,7 +756,7 @@ void Arm64JITCore::EmitTFCheck() { LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Constant); str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData)); - ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)); + ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP)); br(TMP1); (void)Bind(&l_TFBlocked); diff --git a/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp index c9e9eb299..b17de1906 100644 --- a/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp @@ -78,19 +78,19 @@ DEF_OP(Break) { switch (Op->Reason.Signal) { case Core::FAULT_SIGILL: - ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)); + ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGILL)); br(TMP1); break; case Core::FAULT_SIGTRAP: - ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)); + ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP)); br(TMP1); break; case Core::FAULT_SIGSEGV: - ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)); + ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGSEGV)); br(TMP1); break; default: - ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)); + ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP)); br(TMP1); break; } @@ -189,11 +189,11 @@ DEF_OP(Print) { if (IsGPR(Op->Value)) { mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetReg(Op->Value)); - ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue)); + ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.PrintValue)); } else { fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetVReg(Op->Value), false); fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, GetVReg(Op->Value), true); - ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue)); + ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.PrintVectorValue)); } if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] { @@ -311,7 +311,7 @@ DEF_OP(MonoBackpatcherWrite) { strb(TMP1.W(), TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET); #endif - ldr(ARMEmitter::XReg::x4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.MonoBackpatcherWrite)); + ldr(ARMEmitter::XReg::x4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.MonoBackpatcherWrite)); if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] { GenerateIndirectRuntimeCall(ARMEmitter::Reg::r4); } else { diff --git a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp index 9a2ef66e9..43831b993 100644 --- a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp @@ -977,7 +977,7 @@ DEF_OP(LoadNamedVectorConstant) { } // Load the pointer. auto GenerateMemOperand = [this](IR::OpSize OpSize, uint32_t NamedConstant, ARMEmitter::Register Base) { - const auto ConstantOffset = offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.NamedVectorConstants[NamedConstant]); + const auto ConstantOffset = offsetof(FEXCore::Core::CpuStateFrame, Pointers.NamedVectorConstants[NamedConstant]); if (ConstantOffset <= 255 || // Unscaled 9-bit signed ((ConstantOffset & (IR::OpSizeToSize(OpSize) - 1)) == 0 && @@ -985,13 +985,13 @@ DEF_OP(LoadNamedVectorConstant) { return ARMEmitter::ExtendedMemOperand(Base.X(), ARMEmitter::IndexType::OFFSET, ConstantOffset); } - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.NamedVectorConstantPointers[NamedConstant])); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.NamedVectorConstantPointers[NamedConstant])); return ARMEmitter::ExtendedMemOperand(TMP1, ARMEmitter::IndexType::OFFSET, 0); }; if (OpSize == IR::OpSize::i256Bit) { // Handle SVE 32-byte variant upfront. - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.NamedVectorConstantPointers[Op->Constant])); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.NamedVectorConstantPointers[Op->Constant])); ld1b(Dst.Z(), PRED_TMP_32B.Zeroing(), TMP1, 0); return; } @@ -1013,7 +1013,7 @@ DEF_OP(LoadNamedVectorIndexedConstant) { const auto Dst = GetVReg(Node); // Load the pointer. - ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.IndexedNamedVectorConstantPointers[Op->Constant])); + ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.IndexedNamedVectorConstantPointers[Op->Constant])); switch (OpSize) { case IR::OpSize::i8Bit: ldrb(Dst, TMP1, Op->Index); break; diff --git a/FEXCore/include/FEXCore/Core/CoreState.h b/FEXCore/include/FEXCore/Core/CoreState.h index 144ea9e1c..361b267a6 100644 --- a/FEXCore/include/FEXCore/Core/CoreState.h +++ b/FEXCore/include/FEXCore/Core/CoreState.h @@ -320,72 +320,51 @@ struct FallbackABIInfo { struct JITPointers { - struct { - // Process specific + // Process specific + uint64_t PrintValue {}; + uint64_t PrintVectorValue {}; + uint64_t ThreadRemoveCodeEntryFromJIT {}; + uint64_t CPUIDObj {}; + uint64_t CPUIDFunction {}; + uint64_t XCRFunction {}; + uint64_t SyscallHandlerObj {}; + uint64_t SyscallHandlerFunc {}; + uint64_t ExitFunctionLink {}; + uint64_t MonoBackpatcherWrite {}; + uint64_t LUDIV {}; + uint64_t LDIV {}; + uint64_t ThunkCallbackRet {}; - uint64_t PrintValue {}; - uint64_t PrintVectorValue {}; - uint64_t ThreadRemoveCodeEntryFromJIT {}; - uint64_t CPUIDObj {}; - uint64_t CPUIDFunction {}; - uint64_t XCRFunction {}; - uint64_t SyscallHandlerObj {}; - uint64_t SyscallHandlerFunc {}; - uint64_t ExitFunctionLink {}; - uint64_t MonoBackpatcherWrite {}; + // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3 + uint64_t ExitFunctionEC {}; - // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3 - uint64_t ExitFunctionEC {}; + FallbackABIInfo FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX]; + uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX]; + uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX]; + uint64_t TelemetryValueAddresses[FEXCore::Telemetry::TYPE_LAST]; - FallbackABIInfo FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX]; - uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX]; - uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX]; - uint64_t TelemetryValueAddresses[FEXCore::Telemetry::TYPE_LAST]; + /** + * @name Dispatcher pointers + * @{ */ + uint64_t DispatcherLoopTop {}; + uint64_t DispatcherLoopTopFillSRA {}; + uint64_t DispatcherLoopTopEnterEC {}; + uint64_t DispatcherLoopTopEnterECFillSRA {}; + uint64_t ExitFunctionLinker {}; + uint64_t ThreadStopHandlerSpillSRA {}; + uint64_t ThreadPauseHandlerSpillSRA {}; + uint64_t GuestSignal_SIGILL {}; + uint64_t GuestSignal_SIGTRAP {}; + uint64_t GuestSignal_SIGSEGV {}; + uint64_t SignalReturnHandler {}; + uint64_t SignalReturnHandlerRT {}; + uint64_t L2Pointer {}; + uint64_t LUDIVHandler {}; + uint64_t LDIVHandler {}; + /** @} */ - // Thread Specific - /** - * @name Dispatcher pointers - * @{ */ - uint64_t DispatcherLoopTop {}; - uint64_t DispatcherLoopTopFillSRA {}; - uint64_t DispatcherLoopTopEnterEC {}; - uint64_t DispatcherLoopTopEnterECFillSRA {}; - uint64_t ExitFunctionLinker {}; - uint64_t ThreadStopHandlerSpillSRA {}; - uint64_t ThreadPauseHandlerSpillSRA {}; - uint64_t GuestSignal_SIGILL {}; - uint64_t GuestSignal_SIGTRAP {}; - uint64_t GuestSignal_SIGSEGV {}; - uint64_t SignalReturnHandler {}; - uint64_t SignalReturnHandlerRT {}; - uint64_t L2Pointer {}; - /** @} */ - - // Copy of process-wide named vector constants data. - alignas(16) uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2]; - } Common; - - union { - struct { - // Process specific - uint64_t LUDIV {}; - uint64_t LDIV {}; - uint64_t ThunkCallbackRet {}; - - // Thread Specific - - /** - * @name Dispatcher pointers - * @{ */ - uint64_t LUDIVHandler {}; - uint64_t LDIVHandler {}; - /** @} */ - } AArch64; - - struct { - // None so far - } X86; - }; + // Copy of process-wide named vector constants data. + alignas(16) uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2]; }; // Each guest JIT frame has one of these diff --git a/Source/Windows/ARM64EC/Module.cpp b/Source/Windows/ARM64EC/Module.cpp index 9015a55c7..49d3f1bce 100644 --- a/Source/Windows/ARM64EC/Module.cpp +++ b/Source/Windows/ARM64EC/Module.cpp @@ -937,13 +937,13 @@ NTSTATUS ThreadInit() { Frame->State.cs_cached = FEXCore::Core::CPUState::CalculateGDTBase(GDT); FEX::Windows::CallRetStack::InitializeThread(Thread); - Thread->CurrentFrame->Pointers.Common.ExitFunctionEC = reinterpret_cast(&ExitFunctionEC); + Thread->CurrentFrame->Pointers.ExitFunctionEC = reinterpret_cast(&ExitFunctionEC); CPUArea.StateFrame() = Thread->CurrentFrame; - uint64_t EnterEC = Thread->CurrentFrame->Pointers.Common.DispatcherLoopTopEnterEC; + uint64_t EnterEC = Thread->CurrentFrame->Pointers.DispatcherLoopTopEnterEC; CPUArea.DispatcherLoopTopEnterEC() = EnterEC; - uint64_t EnterECFillSRA = Thread->CurrentFrame->Pointers.Common.DispatcherLoopTopEnterECFillSRA; + uint64_t EnterECFillSRA = Thread->CurrentFrame->Pointers.DispatcherLoopTopEnterECFillSRA; CPUArea.DispatcherLoopTopEnterECFillSRA() = EnterECFillSRA; CPUArea.ContextAmd64() = {.ContextFlags = CONTEXT_CONTROL | CONTEXT_SEGMENTS | CONTEXT_INTEGER | CONTEXT_FLOATING_POINT,