From d6f290f6d2cb3c8bdd2dbe0afd10531dde5095ce Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Mon, 22 Dec 2025 11:07:56 -0800
Subject: [PATCH] Arm64Emitter: Move NOP pads to before the move instructions

Recent CPUs do nop fusion with the following instruction, this gives the
CPU the best chance to do fusion with something that actually does work.

Very trivial, doesn't do this for the more complex handling below these
as counting the number of moves before nop emitting is messy.
---
 .../Interface/Core/ArchHelpers/Arm64Emitter.cpp    | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
index ed090adcf..24844c818 100644
--- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
@@ -438,13 +438,13 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
   LOGMAN_THROW_A_FMT(MaxBytes == 0 || (Constant >> (MaxBytes * 8)) == 0, "MaxBytes provided but data can't fit within provided range.");
 
   if (Is64Bit && ((~Constant) >> 16) == 0) {
-    movn(s, Reg, (~Constant) & 0xFFFF);
-
     if (NOPPad) {
       nop();
       nop();
       nop();
     }
+
+    movn(s, Reg, (~Constant) & 0xFFFF);
     return;
   }
 
@@ -456,13 +456,13 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
   }
 
   if (!Is64Bit && ((~Constant) & 0xFFFF0000) == 0) {
-    movn(s, Reg.W(), (~Constant) & 0xFFFF);
-
     if (NOPPad) {
       nop();
       nop();
       nop();
     }
+
+    movn(s, Reg.W(), (~Constant) & 0xFFFF);
     return;
   }
 
@@ -483,24 +483,24 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
     // `movz` is better than `orr` since hardware will rename or merge if possible when `movz` is used.
     const auto IsImm = ARMEmitter::Emitter::IsImmLogical(Constant, RegSizeInBits(s));
     if (IsImm) {
-      orr(s, Reg, ARMEmitter::Reg::zr, Constant);
       if (NOPPad) {
         nop();
         nop();
         nop();
       }
+      orr(s, Reg, ARMEmitter::Reg::zr, Constant);
       return;
     }
   }
 
   // If we can't handle negatives with the orr, try with movn+movk
   if (Is64Bit && ((~Constant) >> 32) == 0) {
-    movn(s, Reg, (~Constant) & 0xFFFF);
-    movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
     if (NOPPad) {
       nop();
       nop();
     }
+    movn(s, Reg, (~Constant) & 0xFFFF);
+    movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
     return;
   }