diff --git a/FEXCore/Source/Interface/Core/CPUBackend.cpp b/FEXCore/Source/Interface/Core/CPUBackend.cpp index b9ecca433..f4ce5bf52 100644 --- a/FEXCore/Source/Interface/Core/CPUBackend.cpp +++ b/FEXCore/Source/Interface/Core/CPUBackend.cpp @@ -39,6 +39,14 @@ namespace CPU { {0xC90F'DAA2'2168'C235ULL, 0x0000'0000'0000'4000ULL}, // NAMED_VECTOR_X87_PI {0x9A20'9A84'FBCF'F799ULL, 0x0000'0000'0000'3FFDULL}, // NAMED_VECTOR_X87_LOG10_2 {0xB172'17F7'D1CF'79ACULL, 0x0000'0000'0000'3FFEULL}, // NAMED_VECTOR_X87_LOG_2 + {0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32 + {0x4F00'0000'4F00'0000ULL, 0x4F00'0000'4F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I32_UPPER + {0x5F00'0000'5F00'0000ULL, 0x5F00'0000'5F00'0000ULL}, // NAMED_VECTOR_CVTMAX_F32_I64 + {0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32 + {0x41E0'0000'0000'0000ULL, 0x41E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I32_UPPER + {0x43E0'0000'0000'0000ULL, 0x43E0'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_F64_I64 + {0x8000'0000'8000'0000ULL, 0x8000'0000'8000'0000ULL}, // NAMED_VECTOR_CVTMAX_I32 + {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_CVTMAX_I64 }; constexpr static auto PSHUFLW_LUT {[]() consteval { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 24d875f4f..671e264dc 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5089,9 +5089,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b10, 0x5A), 1, &OpDispatchBuilder::AVXInsertScalar_CVT_Float_To_Float}, {OPD(1, 0b11, 0x5A), 1, &OpDispatchBuilder::AVXInsertScalar_CVT_Float_To_Float}, - {OPD(1, 0b00, 0x5B), 1, &OpDispatchBuilder::AVXVector_CVT_Int_To_Float}, - {OPD(1, 0b01, 0x5B), 1, &OpDispatchBuilder::AVXVector_CVT_Float_To_Int}, - {OPD(1, 0b10, 0x5B), 1, &OpDispatchBuilder::AVXVector_CVT_Float_To_Int}, + {OPD(1, 0b00, 0x5B), 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float}, + {OPD(1, 0b01, 0x5B), 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {OPD(1, 0b10, 0x5B), 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {OPD(1, 0b00, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVXVectorALUOp, IR::OP_VFSUB, OpSize::i32Bit>}, {OPD(1, 0b01, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVXVectorALUOp, IR::OP_VFSUB, OpSize::i64Bit>}, @@ -5191,9 +5191,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b01, 0xE4), 1, &OpDispatchBuilder::VPMULHWOp}, {OPD(1, 0b01, 0xE5), 1, &OpDispatchBuilder::VPMULHWOp}, - {OPD(1, 0b01, 0xE6), 1, &OpDispatchBuilder::AVXVector_CVT_Float_To_Int}, - {OPD(1, 0b10, 0xE6), 1, &OpDispatchBuilder::AVXVector_CVT_Int_To_Float}, - {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::AVXVector_CVT_Float_To_Int}, + {OPD(1, 0b01, 0xE6), 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {OPD(1, 0b10, 0xE6), 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float}, + {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::MOVVectorNTOp}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 2fee16280..4c88a19f8 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -469,10 +469,10 @@ public: template void Scalar_CVT_Float_To_Float(OpcodeArgs); void Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize, bool IsAVX); - template + template void Vector_CVT_Float_To_Int(OpcodeArgs); void MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs); - template + template void XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); void MASKMOVOp(OpcodeArgs); void MOVBetweenGPR_FPR(OpcodeArgs, VectorOpType VectorType); @@ -518,12 +518,6 @@ public: template void AVXScalar_CVT_Float_To_Float(OpcodeArgs); - template - void AVXVector_CVT_Float_To_Int(OpcodeArgs); - - template - void AVXVector_CVT_Int_To_Float(OpcodeArgs); - template void VectorScalarInsertALUOp(OpcodeArgs); template @@ -1032,7 +1026,7 @@ public: template void AVX128_Vector_CVT_Float_To_Float(OpcodeArgs); - template + template void AVX128_Vector_CVT_Float_To_Int(OpcodeArgs); template @@ -1471,7 +1465,10 @@ private: Ref Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize, const X86Tables::DecodedOperand& Src1Op, const X86Tables::DecodedOperand& Src2Op); - Ref Vector_CVT_Float_To_IntImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool Narrow, bool HostRoundingMode); + Ref CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSize SrcElementSize, bool HostRoundingMode); + + Ref Vector_CVT_Float_To_Int32Impl(OpcodeArgs, IR::OpSize DstSize, Ref Src, IR::OpSize SrcSize, IR::OpSize SrcElementSize, + bool HostRoundingMode, bool ZeroUpperHalf); Ref Vector_CVT_Int_To_FloatImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool Widen); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 5bcf58d12..f8f32c62a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -116,8 +116,8 @@ void OpDispatchBuilder::InstallAVX128Handlers() { {OPD(1, 0b11, 0x5A), 1, &OpDispatchBuilder::AVX128_InsertScalar_CVT_Float_To_Float}, {OPD(1, 0b00, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float}, - {OPD(1, 0b01, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, - {OPD(1, 0b10, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, + {OPD(1, 0b01, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, + {OPD(1, 0b10, 0x5B), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, {OPD(1, 0b00, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFSUB, OpSize::i32Bit>}, {OPD(1, 0b01, 0x5C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorALU, IR::OP_VFSUB, OpSize::i64Bit>}, @@ -217,9 +217,9 @@ void OpDispatchBuilder::InstallAVX128Handlers() { {OPD(1, 0b01, 0xE4), 1, &OpDispatchBuilder::AVX128_VPMULHW}, {OPD(1, 0b01, 0xE5), 1, &OpDispatchBuilder::AVX128_VPMULHW}, - {OPD(1, 0b01, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, + {OPD(1, 0b01, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, {OPD(1, 0b10, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Int_To_Float}, - {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, + {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int}, {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::AVX128_MOVVectorNT}, @@ -1058,18 +1058,8 @@ void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs) { Src.Low = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], OpSizeFromSrc(Op), Op->Flags); } - // GPR size is determined by REX.W - // Source Element size is determined by instruction - const auto GPRSize = OpSizeFromDst(Op); - - Ref Result {}; - if constexpr (HostRoundingMode) { - Result = _Float_ToGPR_S(GPRSize, SrcElementSize, Src.Low); - } else { - Result = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src.Low); - } - - StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, OpSize::iInvalid); + Ref Result = CVTFPR_To_GPRImpl(Op, Src.Low, SrcElementSize, HostRoundingMode); + StoreResult(GPRClass, Op, Result, OpSize::iInvalid); } void OpDispatchBuilder::AVX128_VANDN(OpcodeArgs) { @@ -1604,7 +1594,7 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Float(OpcodeArgs) { AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result); } -template +template void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs) { const auto SrcSize = GetSrcSize(Op); @@ -1614,46 +1604,20 @@ void OpDispatchBuilder::AVX128_Vector_CVT_Float_To_Int(OpcodeArgs) { auto Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, !Is128BitSrc); RefPair Result {}; - if (SrcElementSize == OpSize::i64Bit && Narrow) { - ///< Special case for VCVTPD2DQ/CVTTPD2DQ because it has weird rounding requirements. - Result.Low = _Vector_F64ToI32(OpSize::i128Bit, Src.Low, HostRoundingMode ? Round_Host : Round_Towards_Zero, Is128BitSrc); - - if (!Is128BitSrc) { - // Also convert the upper 128-bit lane - auto ResultHigh = _Vector_F64ToI32(OpSize::i128Bit, Src.High, HostRoundingMode ? Round_Host : Round_Towards_Zero, false); - - // Zip the two halves together in to the lower 128-bits - Result.Low = _VZip(OpSize::i128Bit, OpSize::i64Bit, Result.Low, ResultHigh); - } - } else { - auto Convert = [this](Ref Src) -> Ref { - auto ElementSize = SrcElementSize; - if (Narrow) { - ElementSize = ElementSize >> 1; - Src = _Vector_FToF(OpSize::i128Bit, ElementSize, Src, SrcElementSize); - } - - if (HostRoundingMode) { - return _Vector_FToS(OpSize::i128Bit, ElementSize, Src); - } else { - return _Vector_FToZS(OpSize::i128Bit, ElementSize, Src); - } - }; - - Result.Low = Convert(Src.Low); - - if (!Is128BitSrc) { - if (!Narrow) { - Result.High = Convert(Src.High); - } else { - Result.Low = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 1, 0, Result.Low, Convert(Src.High)); - } - } - } - - if (Narrow || Is128BitSrc) { + Result.Low = Vector_CVT_Float_To_Int32Impl(Op, OpSize::i128Bit, Src.Low, OpSize::i128Bit, SrcElementSize, HostRoundingMode, Is128BitSrc); + if (Is128BitSrc) { // Zero the upper 128-bit lane of the result. Result = AVX128_Zext(Result.Low); + } else { + Result.High = Vector_CVT_Float_To_Int32Impl(Op, OpSize::i128Bit, Src.High, OpSize::i128Bit, SrcElementSize, HostRoundingMode, false); + // Also convert the upper 128-bit lane + if (SrcElementSize == OpSize::i64Bit) { + // Zip the two halves together in to the lower 128-bits + Result.Low = _VZip(OpSize::i128Bit, OpSize::i64Bit, Result.Low, Result.High); + + // Zero the upper 128-bit lane of the result. + Result = AVX128_Zext(Result.Low); + } } AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h index 7f986b177..044d43403 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h @@ -7,7 +7,7 @@ constexpr std::tuple OpDisp {0x0C, 1, &OpDispatchBuilder::PI2FWOp}, {0x0D, 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float}, {0x1C, 1, &OpDispatchBuilder::PF2IWOp}, - {0x1D, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {0x1D, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {0x86, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRECP, OpSize::i32Bit>}, {0x87, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRSQRT, OpSize::i32Bit>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h index 7cb9978ff..ce0eb83dc 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h @@ -57,8 +57,8 @@ constexpr std::tuple OpDisp {0x28, 2, &OpDispatchBuilder::MOVVectorAlignedOp}, {0x2A, 1, &OpDispatchBuilder::InsertMMX_To_XMM_Vector_CVT_Int_To_Float}, {0x2B, 1, &OpDispatchBuilder::MOVVectorNTOp}, - {0x2C, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, - {0x2D, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, + {0x2C, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, + {0x2D, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, {0x2E, 2, &OpDispatchBuilder::UCOMISxOp}, {0x50, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVMSKOp, OpSize::i32Bit>}, {0x51, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFSQRT, OpSize::i32Bit>}, @@ -161,7 +161,7 @@ constexpr std::tuple OpDisp {0x58, 1, &OpDispatchBuilder::VectorScalarInsertALUOp}, {0x59, 1, &OpDispatchBuilder::VectorScalarInsertALUOp}, {0x5A, 1, &OpDispatchBuilder::InsertScalar_CVT_Float_To_Float}, - {0x5B, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {0x5B, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {0x5C, 1, &OpDispatchBuilder::VectorScalarInsertALUOp}, {0x5D, 1, &OpDispatchBuilder::VectorScalarInsertALUOp}, {0x5E, 1, &OpDispatchBuilder::VectorScalarInsertALUOp}, @@ -200,7 +200,7 @@ constexpr std::tuple OpDisp {0xD0, 1, &OpDispatchBuilder::ADDSUBPOp}, {0xD6, 1, &OpDispatchBuilder::MOVQ2DQ}, {0xC2, 1, &OpDispatchBuilder::InsertScalarFCMPOp}, - {0xE6, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {0xE6, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {0xF0, 1, &OpDispatchBuilder::MOVVectorUnalignedOp}, }; @@ -213,8 +213,8 @@ constexpr std::tuple OpDisp {0x28, 2, &OpDispatchBuilder::MOVVectorAlignedOp}, {0x2A, 1, &OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float}, {0x2B, 1, &OpDispatchBuilder::MOVVectorNTOp}, - {0x2C, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, - {0x2D, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, + {0x2C, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, + {0x2D, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int}, {0x2E, 2, &OpDispatchBuilder::UCOMISxOp}, {0x50, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVMSKOp, OpSize::i64Bit>}, @@ -226,7 +226,7 @@ constexpr std::tuple OpDisp {0x58, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADD, OpSize::i64Bit>}, {0x59, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMUL, OpSize::i64Bit>}, {0x5A, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::Vector_CVT_Float_To_Float, OpSize::i32Bit, OpSize::i64Bit, false>}, - {0x5B, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {0x5B, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {0x5C, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFSUB, OpSize::i64Bit>}, {0x5D, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMIN, OpSize::i64Bit>}, {0x5E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFDIV, OpSize::i64Bit>}, @@ -284,7 +284,7 @@ constexpr std::tuple OpDisp {0xE3, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VURAVG, OpSize::i16Bit>}, {0xE4, 1, &OpDispatchBuilder::PMULHW}, {0xE5, 1, &OpDispatchBuilder::PMULHW}, - {0xE6, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, + {0xE6, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int}, {0xE7, 1, &OpDispatchBuilder::MOVVectorNTOp}, {0xE8, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSQSUB, OpSize::i8Bit>}, {0xE9, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSQSUB, OpSize::i16Bit>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index b0a2ea53f..b2bdcdf9a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2067,6 +2067,24 @@ void OpDispatchBuilder::AVXCVTGPR_To_FPR(OpcodeArgs) { template void OpDispatchBuilder::AVXCVTGPR_To_FPR(OpcodeArgs); template void OpDispatchBuilder::AVXCVTGPR_To_FPR(OpcodeArgs); +Ref OpDispatchBuilder::CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSize SrcElementSize, bool HostRoundingMode) { + // GPR size is determined by REX.W + // Source Element size is determined by instruction + const auto GPRSize = OpSizeFromDst(Op); + + if (HostRoundingMode) { + Src = _Vector_FToI(SrcElementSize, SrcElementSize, Src, Round_Host); + } + Ref Converted = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src); + + bool Dst32 = GPRSize == OpSize::i32Bit; + Ref MaxI = Dst32 ? _Constant(0x80000000) : _Constant(0x8000000000000000); + Ref MaxF = LoadAndCacheNamedVectorConstant(SrcElementSize, (SrcElementSize == OpSize::i32Bit) ? + (Dst32 ? NAMED_VECTOR_CVTMAX_F32_I32 : NAMED_VECTOR_CVTMAX_F32_I64) : + (Dst32 ? NAMED_VECTOR_CVTMAX_F64_I32 : NAMED_VECTOR_CVTMAX_F64_I64)); + return _Select(GPRSize, SrcElementSize, CondClassType {FEXCore::IR::COND_FGT}, MaxF, Src, Converted, MaxI); +} + template void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) { // If loading a vector, use the full size, so we don't @@ -2074,18 +2092,8 @@ void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) { // memory, then we want to load the element size exactly. const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : OpSizeFromSrc(Op); Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags); - - // GPR size is determined by REX.W - // Source Element size is determined by instruction - const auto GPRSize = OpSizeFromDst(Op); - - if constexpr (HostRoundingMode) { - Src = _Float_ToGPR_S(GPRSize, SrcElementSize, Src); - } else { - Src = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src); - } - - StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Src, GPRSize, OpSize::iInvalid); + Ref Result = CVTFPR_To_GPRImpl(Op, Src, SrcElementSize, HostRoundingMode); + StoreResult(GPRClass, Op, Result, OpSize::iInvalid); } template void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs); @@ -2127,77 +2135,43 @@ void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs) { template void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs); template void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs); -template -void OpDispatchBuilder::AVXVector_CVT_Int_To_Float(OpcodeArgs) { - Ref Result = Vector_CVT_Int_To_FloatImpl(Op, SrcElementSize, Widen); - StoreResult(FPRClass, Op, Result, OpSize::iInvalid); -} - -template void OpDispatchBuilder::AVXVector_CVT_Int_To_Float(OpcodeArgs); -template void OpDispatchBuilder::AVXVector_CVT_Int_To_Float(OpcodeArgs); - -Ref OpDispatchBuilder::Vector_CVT_Float_To_IntImpl(OpcodeArgs, IR::OpSize SrcElementSize, bool Narrow, bool HostRoundingMode) { - const auto DstSize = OpSizeFromDst(Op); - auto ElementSize = SrcElementSize; - - Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - - if (Narrow) { - Src = _Vector_FToF(DstSize, SrcElementSize >> 1, Src, SrcElementSize); - ElementSize = ElementSize >> 1; - } - +Ref OpDispatchBuilder::Vector_CVT_Float_To_Int32Impl(OpcodeArgs, IR::OpSize DstSize, Ref Src, IR::OpSize SrcSize, IR::OpSize SrcElementSize, + bool HostRoundingMode, bool ZeroUpperHalf) { if (HostRoundingMode) { - return _Vector_FToS(DstSize, ElementSize, Src); - } else { - return _Vector_FToZS(DstSize, ElementSize, Src); + Src = _Vector_FToI(SrcSize, SrcElementSize, Src, Round_Host); } + + OpSize OverflowConstSize = ZeroUpperHalf && SrcElementSize == OpSize::i64Bit ? DstSize / 2 : DstSize; + Ref MaxI = LoadAndCacheNamedVectorConstant(OverflowConstSize, NAMED_VECTOR_CVTMAX_I32); + Ref Converted {}, Cmp {}; + if (SrcElementSize == OpSize::i64Bit) { + Ref MaxF = LoadAndCacheNamedVectorConstant(SrcSize, NAMED_VECTOR_CVTMAX_F64_I32); + Converted = _Vector_F64ToI32(DstSize, Src, Round_Towards_Zero, ZeroUpperHalf); + + Cmp = _VFCMPGT(SrcSize, OpSize::i64Bit, MaxF, Src); + Cmp = _VUShrNI(DstSize, OpSize::i64Bit, Cmp, 32); + } else { + Ref MaxF = LoadAndCacheNamedVectorConstant(DstSize, NAMED_VECTOR_CVTMAX_F32_I32); + Converted = _Vector_FToZS(DstSize, OpSize::i32Bit, Src); + Cmp = _VFCMPGT(DstSize, OpSize::i32Bit, MaxF, Src); + } + return _VBSL(DstSize, Cmp, Converted, MaxI); } -template +template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs) { const auto DstSize = OpSizeFromDst(Op); - Ref Result {}; - if (SrcElementSize == OpSize::i64Bit && Narrow) { - ///< Special case for CVTTPD2DQ because it has weird rounding requirements. - Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - Result = _Vector_F64ToI32(DstSize, Src, HostRoundingMode ? Round_Host : Round_Towards_Zero, true); - } else { - Result = Vector_CVT_Float_To_IntImpl(Op, SrcElementSize, Narrow, HostRoundingMode); - } - + Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, OpSizeFromSrc(Op), SrcElementSize, HostRoundingMode, true); StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, DstSize, OpSize::iInvalid); } -template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); - -template -void OpDispatchBuilder::AVXVector_CVT_Float_To_Int(OpcodeArgs) { - const auto DstSize = OpSizeFromDst(Op); - - Ref Result {}; - if (SrcElementSize == OpSize::i64Bit && Narrow) { - ///< Special case for CVTPD2DQ/CVTTPD2DQ because it has weird rounding requirements. - Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); - Result = _Vector_F64ToI32(DstSize, Src, HostRoundingMode ? Round_Host : Round_Towards_Zero, true); - } else { - Result = Vector_CVT_Float_To_IntImpl(Op, SrcElementSize, Narrow, HostRoundingMode); - } - - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, DstSize, OpSize::iInvalid); -} - -template void OpDispatchBuilder::AVXVector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::AVXVector_CVT_Float_To_Int(OpcodeArgs); - -template void OpDispatchBuilder::AVXVector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::AVXVector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs); Ref OpDispatchBuilder::Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::OpSize DstElementSize, IR::OpSize SrcElementSize, const X86Tables::DecodedOperand& Src1Op, const X86Tables::DecodedOperand& Src2Op) { @@ -2277,7 +2251,7 @@ void OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs) { StoreResult(FPRClass, Op, Src, OpSize::iInvalid); } -template +template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs) { // This function causes a change in MMX state from X87 to MMX if (MMXState == MMXState_X87) { @@ -2288,29 +2262,16 @@ void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs) { // unnecessarily zero extend the vector. Otherwise, if // memory, then we want to load the element size exactly. const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : OpSizeFromSrc(Op); + const auto DstSize = OpSizeFromDst(Op); Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags); - - auto ElementSize = SrcElementSize; - const auto Size = OpSizeFromDst(Op); - - if (Narrow) { - Src = _Vector_FToF(Size, SrcElementSize >> 1, Src, SrcElementSize); - ElementSize = ElementSize >> 1; - } - - if constexpr (HostRoundingMode) { - Src = _Vector_FToS(Size, ElementSize, Src); - } else { - Src = _Vector_FToZS(Size, ElementSize, Src); - } - - StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, Size, OpSize::iInvalid); + Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, SrcSize, SrcElementSize, HostRoundingMode, false /* TODO? */); + StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, DstSize, OpSize::iInvalid); } -template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); -template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); +template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs); void OpDispatchBuilder::MASKMOVOp(OpcodeArgs) { const auto Size = OpSizeFromSrc(Op); diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp index b4a94aa1b..f3e61aeae 100644 --- a/FEXCore/Source/Interface/IR/IRDumper.cpp +++ b/FEXCore/Source/Interface/IR/IRDumper.cpp @@ -209,6 +209,22 @@ static void PrintArg(fextl::stringstream* out, [[maybe_unused]] const IRListView return "x87_log10_2"; case NamedVectorConstant::NAMED_VECTOR_X87_LOG_2: return "x87_log2"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32: + return "cvtmax_f32_i32"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32_UPPER: + return "cvtmax_f32_i32_upper"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I64: + return "cvtmax_f32_i64"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32: + return "cvtmax_f64_i32"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32_UPPER: + return "cvtmax_f64_i32_upper"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I64: + return "cvtmax_f64_i64"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I32: + return "cvtmax_i32"; + case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I64: + return "cvtmax_i64"; default: return ""; } diff --git a/FEXCore/include/FEXCore/IR/IR.h b/FEXCore/include/FEXCore/IR/IR.h index 005b41883..febfcaba5 100644 --- a/FEXCore/include/FEXCore/IR/IR.h +++ b/FEXCore/include/FEXCore/IR/IR.h @@ -71,6 +71,15 @@ enum NamedVectorConstant : uint8_t { NAMED_VECTOR_X87_LOG10_2, NAMED_VECTOR_X87_LOG_2, + NAMED_VECTOR_CVTMAX_F32_I32, + NAMED_VECTOR_CVTMAX_F32_I32_UPPER, + NAMED_VECTOR_CVTMAX_F32_I64, + NAMED_VECTOR_CVTMAX_F64_I32, + NAMED_VECTOR_CVTMAX_F64_I32_UPPER, + NAMED_VECTOR_CVTMAX_F64_I64, + NAMED_VECTOR_CVTMAX_I32, + NAMED_VECTOR_CVTMAX_I64, + NAMED_VECTOR_CONST_POOL_MAX, // Beginning of named constants that don't have a constant pool backing. NAMED_VECTOR_ZERO = NAMED_VECTOR_CONST_POOL_MAX, diff --git a/unittests/ASM/OpSize/66_2D.asm b/unittests/ASM/OpSize/66_2D.asm index 9150e35de..08dc1b5c6 100644 --- a/unittests/ASM/OpSize/66_2D.asm +++ b/unittests/ASM/OpSize/66_2D.asm @@ -2,7 +2,9 @@ { "RegData": { "MM0": "0x0000000200000001", - "MM1": "0xFFFFFFFEFFFFFFFF" + "MM1": "0xFFFFFFFEFFFFFFFF", + "MM2": "0x8000000080000000", + "MM3": "0x8000000080000000" } } %endif @@ -29,6 +31,16 @@ mov [rdx + 8 * 4], rax mov rax, 0x5152535455565758 mov [rdx + 8 * 5], rax +mov rax, 0x7ff0000000000000 +mov [rdx + 8 * 6], rax +mov rax, 0xfff0000000000000 +mov [rdx + 8 * 7], rax + +mov rax, 0x7ff8000000000000 +mov [rdx + 8 * 8], rax +mov rax, 0x7fefffffffffffff +mov [rdx + 8 * 9], rax + movq mm0, [rdx + 8 * 4] movq mm1, [rdx + 8 * 4] @@ -36,5 +48,7 @@ movapd xmm2, [rdx + 8 * 0] cvtpd2pi mm0, xmm2 cvtpd2pi mm1, [rdx + 8 * 2] +cvtpd2pi mm2, [rdx + 8 * 6] +cvtpd2pi mm3, [rdx + 8 * 8] hlt diff --git a/unittests/ASM/OpSize/66_5A.asm b/unittests/ASM/OpSize/66_5A.asm index 787b05489..a67bf9b95 100644 --- a/unittests/ASM/OpSize/66_5A.asm +++ b/unittests/ASM/OpSize/66_5A.asm @@ -2,7 +2,9 @@ { "RegData": { "XMM0": ["0x404000003F800000", "0x0"], - "XMM1": ["0x3FF0000000000000", "0x4008000000000000"] + "XMM1": ["0x3FF0000000000000", "0x4008000000000000"], + "XMM2": ["0xff8000007f800000", "0x0000000000000000"], + "XMM3": ["0x7f8000007fc00000", "0x0000000000000000"] } } %endif @@ -19,9 +21,22 @@ mov [rdx + 8 * 2], rax mov rax, 0xFFFFFFFFFFFFFFFF mov [rdx + 8 * 3], rax +mov rax, 0x7ff0000000000000 +mov [rdx + 8 * 4], rax +mov rax, 0xfff0000000000000 +mov [rdx + 8 * 5], rax +mov rax, 0x7ff8000000000000 +mov [rdx + 8 * 6], rax +mov rax, 0x7fefffffffffffff +mov [rdx + 8 * 7], rax + movapd xmm0, [rdx + 8 * 2] movapd xmm1, [rdx] +movapd xmm2, [rdx + 8 * 4] +movapd xmm3, [rdx + 8 * 6] cvtpd2ps xmm0, xmm1 +cvtpd2ps xmm2, xmm2 +cvtpd2ps xmm3, xmm3 hlt diff --git a/unittests/ASM/OpSize/66_5B.asm b/unittests/ASM/OpSize/66_5B.asm index 5765e056a..fce53f505 100644 --- a/unittests/ASM/OpSize/66_5B.asm +++ b/unittests/ASM/OpSize/66_5B.asm @@ -2,7 +2,8 @@ { "RegData": { "XMM0": ["0x0000000100000001", "0x0000000200000002"], - "XMM1": ["0x0000000400000004", "0x0000000800000008"] + "XMM1": ["0x0000000400000004", "0x0000000800000008"], + "XMM2": ["0x8000000000000000", "0x8000000080000000"] } } %endif @@ -24,6 +25,11 @@ mov [rdx + 8 * 4], rax mov rax, 0x5152535455565758 mov [rdx + 8 * 5], rax +mov rax, 0x7fc000007f800000 +mov [rdx + 8 * 6], rax +mov rax, 0xff800000ff7fffee +mov [rdx + 8 * 7], rax + ; Set up MXCSR to truncate mov eax, 0x7F80 mov [rdx + 8 * 6], eax @@ -36,5 +42,6 @@ movapd xmm2, [rdx + 8 * 0] cvtps2dq xmm0, xmm2 cvtps2dq xmm1, [rdx + 8 * 2] +cvtps2dq xmm2, [rdx + 8 * 6] hlt diff --git a/unittests/ASM/REPNE/F2_2D.asm b/unittests/ASM/REPNE/F2_2D.asm index 38d7806d1..75d839828 100644 --- a/unittests/ASM/REPNE/F2_2D.asm +++ b/unittests/ASM/REPNE/F2_2D.asm @@ -4,7 +4,11 @@ "RAX": "0x1", "RBX": "0x2", "RCX": "0x3", - "RDX": "0x4" + "RDX": "0x4", + "R9": "0x8000000000000000", + "R10": "0x8000000000000000", + "R11": "0x8000000000000000", + "R12": "0x8000000000000000" } } %endif @@ -31,6 +35,16 @@ mov [rdx + 8 * 6], rax mov rax, 0x5152535455565758 mov [rdx + 8 * 7], rax +mov rax, 0x7ff0000000000000 +mov [rdx + 8 * 8], rax +mov rax, 0xfff0000000000000 +mov [rdx + 8 * 9], rax +mov rax, 0x7ff8000000000000 +mov [rdx + 8 * 10], rax +mov rax, 0x7fefffffffffffff +mov [rdx + 8 * 11], rax + + movapd xmm0, [rdx + 8 * 0] movapd xmm1, [rdx + 8 * 2] @@ -38,6 +52,10 @@ cvtsd2si eax, xmm0 cvtsd2si rbx, xmm1 cvtsd2si ecx, [rdx + 8 * 4] +cvtsd2si r9, [rdx + 8 * 8] +cvtsd2si r10, [rdx + 8 * 9] +cvtsd2si r11, [rdx + 8 * 10] +cvtsd2si r12, [rdx + 8 * 11] cvtsd2si rdx, [rdx + 8 * 6] hlt diff --git a/unittests/ASM/REPNE/F2_E6.asm b/unittests/ASM/REPNE/F2_E6.asm index da41da055..a7c5cfbfb 100644 --- a/unittests/ASM/REPNE/F2_E6.asm +++ b/unittests/ASM/REPNE/F2_E6.asm @@ -2,7 +2,9 @@ { "RegData": { "XMM0": ["0x0000000200000001", "0x0"], - "XMM1": ["0xFFFFFFFEFFFFFFFF", "0x0"] + "XMM1": ["0xFFFFFFFEFFFFFFFF", "0x0"], + "XMM2": ["0x8000000080000000", "0x0"], + "XMM3": ["0x8000000080000000", "0x0"] } } %endif @@ -24,6 +26,16 @@ mov [rdx + 8 * 4], rax mov rax, 0x5152535455565758 mov [rdx + 8 * 5], rax +mov rax, 0x7ff0000000000000 +mov [rdx + 8 * 6], rax +mov rax, 0xfff0000000000000 +mov [rdx + 8 * 7], rax + +mov rax, 0x7ff8000000000000 +mov [rdx + 8 * 8], rax +mov rax, 0x7fefffffffffffff +mov [rdx + 8 * 9], rax + movapd xmm0, [rdx + 8 * 4] movapd xmm1, [rdx + 8 * 4] @@ -31,5 +43,7 @@ movapd xmm2, [rdx + 8 * 0] cvtpd2dq xmm0, xmm2 cvtpd2dq xmm1, [rdx + 8 * 2] +cvtpd2dq xmm2, [rdx + 8 * 6] +cvtpd2dq xmm3, [rdx + 8 * 8] hlt diff --git a/unittests/ASM/VEX/vcvtpd2dq_inexact.asm b/unittests/ASM/VEX/vcvtpd2dq_inexact.asm index 762d49481..403e33d5a 100644 --- a/unittests/ASM/VEX/vcvtpd2dq_inexact.asm +++ b/unittests/ASM/VEX/vcvtpd2dq_inexact.asm @@ -5,7 +5,8 @@ "XMM0": ["0x0000000200000001", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"], "XMM1": ["0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"], "XMM3": ["0x0000000200000001", "0x0000000200000001", "0x0000000000000000", "0x0000000000000000"], - "XMM4": ["0xFFFFFFFEFFFFFFFF", "0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000"] + "XMM4": ["0xFFFFFFFEFFFFFFFF", "0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x8000000080000000", "0x8000000080000000", "0x0000000000000000", "0x0000000000000000"] } } %endif @@ -22,6 +23,8 @@ vcvtpd2dq xmm1, oword [rdx + 32 * 1] vcvtpd2dq xmm3, ymm2 vcvtpd2dq xmm4, yword [rdx + 32 * 1] +vcvtpd2dq xmm5, yword [rdx + 32 * 3] + hlt align 32 @@ -40,3 +43,8 @@ dq 0x4142434445464748 dq 0x5152535455565758 dq 0x4142434445464748 dq 0x5152535455565758 + +dq 0x7ff0000000000000 +dq 0xfff0000000000000 +dq 0x7ff8000000000000 +dq 0x7fefffffffffffff diff --git a/unittests/ASM/VEX/vcvtpd2ps.asm b/unittests/ASM/VEX/vcvtpd2ps.asm index 793edcee0..e324f77e4 100644 --- a/unittests/ASM/VEX/vcvtpd2ps.asm +++ b/unittests/ASM/VEX/vcvtpd2ps.asm @@ -11,7 +11,8 @@ "XMM10": ["0x4214ADB642B062C4", "0x41245B0E42461AA5", "0x0000000000000000", "0x0000000000000000"], "XMM11": ["0x41A1B712429B697F", "0x42252CF2411CE3BD", "0x0000000000000000", "0x0000000000000000"], "XMM12": ["0x42662BE34176837B", "0x425E2C0D4119C75A", "0x0000000000000000", "0x0000000000000000"], - "XMM13": ["0x409C30014253A13B", "0x4041495242910EC1", "0x0000000000000000", "0x0000000000000000"] + "XMM13": ["0x409C30014253A13B", "0x4041495242910EC1", "0x0000000000000000", "0x0000000000000000"], + "XMM14": ["0xff8000007f800000", "0x7f8000007fc00000", "0x0000000000000000", "0x0000000000000000"] } } %endif @@ -29,6 +30,7 @@ vcvtpd2ps xmm10, yword [rdx + 32 * 10] vcvtpd2ps xmm11, yword [rdx + 32 * 11] vcvtpd2ps xmm12, yword [rdx + 32 * 12] vcvtpd2ps xmm13, yword [rdx + 32 * 13] +vcvtpd2ps xmm14, yword [rdx + 32 * 14] hlt @@ -75,3 +77,6 @@ dq 9.61117, 55.54302 dq 52.90745, 4.88086 dq 72.52882, 3.0201 + +dq 0x7ff0000000000000, 0xfff0000000000000 +dq 0x7ff8000000000000, 0x7fefffffffffffff diff --git a/unittests/ASM/VEX/vcvtps2dq_inexact.asm b/unittests/ASM/VEX/vcvtps2dq_inexact.asm index a11bdd189..fa94dd862 100644 --- a/unittests/ASM/VEX/vcvtps2dq_inexact.asm +++ b/unittests/ASM/VEX/vcvtps2dq_inexact.asm @@ -5,7 +5,8 @@ "XMM0": ["0x0000000100000001", "0x0000000200000002", "0x0000000000000000", "0x0000000000000000"], "XMM1": ["0x0000000400000004", "0x0000000800000008", "0x0000000000000000", "0x0000000000000000"], "XMM3": ["0x0000000100000001", "0x0000000200000002", "0x0000000100000001", "0x0000000200000002"], - "XMM4": ["0x0000000400000004", "0x0000000800000008", "0x0000000400000004", "0x0000000800000008"] + "XMM4": ["0x0000000400000004", "0x0000000800000008", "0x0000000400000004", "0x0000000800000008"], + "XMM5": ["0x8000000080000000", "0x8000000080000000", "0x8000000080000000", "0x0000000000000000"] } } %endif @@ -24,6 +25,7 @@ vcvtps2dq xmm1, [rdx + 32 * 1] vcvtps2dq ymm3, ymm2 vcvtps2dq ymm4, [rdx + 32 * 1] +vcvtps2dq ymm5, [rdx + 32 * 3] hlt @@ -44,5 +46,10 @@ dq 0x5152535455565758 dq 0x4142434445464748 dq 0x5152535455565758 +dq 0x7fc000007f800000 +dq 0xff800000ff7fffee +dq 0x7bc097cefbc097ce +dq 0x0000000080000000 + .mxcsr: -dq 0x0000000000007F80 \ No newline at end of file +dq 0x0000000000007F80 diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 7f2416cf4..9dc1091bd 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -505,7 +505,7 @@ ], "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2448]", + "ldr q3, [x28, #2512]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -519,7 +519,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #16]", "ushr v3.4s, v16.4s, #31", - "ldr q4, [x28, #2448]", + "ldr q4, [x28, #2512]", "ushl v3.4s, v3.4s, v4.4s", "addv s3, v3.4s", "mov w20, v3.s[0]", @@ -1168,7 +1168,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1181,7 +1181,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1194,7 +1194,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1219,7 +1219,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1233,7 +1233,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1247,7 +1247,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1272,7 +1272,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1285,7 +1285,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1298,7 +1298,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1326,7 +1326,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1340,7 +1340,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1354,7 +1354,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1379,7 +1379,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1392,7 +1392,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1405,7 +1405,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1433,7 +1433,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1447,7 +1447,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1461,7 +1461,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -2384,7 +2384,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2399,7 +2399,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2412,7 +2412,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2427,7 +2427,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q4, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2440,7 +2440,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2455,7 +2455,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q4, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2725,79 +2725,127 @@ ] }, "vcvttss2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b10 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs w4, s16" + "fcvtzs w20, s16", + "mov w21, #0x80000000", + "ldr s2, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvttss2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b10 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs x4, s16" + "fcvtzs x20, s16", + "mov x21, #0x8000000000000000", + "ldr s2, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvttsd2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b11 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs w4, d16" + "fcvtzs w20, d16", + "mov w21, #0x80000000", + "ldr d2, [x28, #2816]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvttsd2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b11 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs x4, d16" + "fcvtzs x20, d16", + "mov x21, #0x8000000000000000", + "ldr d2, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtss2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b10 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs w4, s0" + "frinti s2, s16", + "fcvtzs w20, s2", + "mov w21, #0x80000000", + "ldr s3, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvtss2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b10 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs x4, s0" + "frinti s2, s16", + "fcvtzs x20, s2", + "mov x21, #0x8000000000000000", + "ldr s3, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtsd2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b11 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtsd2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b11 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vucomiss xmm0, xmm1": { @@ -3099,51 +3147,75 @@ ] }, "vcvtps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 9, "Comment": [ "Map 1 0b01 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "frinti v16.4s, v17.4s", - "fcvtzs v16.4s, v16.4s", + "frinti v2.4s, v17.4s", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2768]", + "fcvtzs v5.4s, v2.4s", + "fcmgt v2.4s, v4.4s, v2.4s", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" ] }, "vcvtps2dq ymm0, ymm1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 13, "Comment": [ "Map 1 0b01 0x5b 256-bit" ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "frinti v16.4s, v17.4s", - "fcvtzs v16.4s, v16.4s", + "frinti v3.4s, v17.4s", + "ldr q4, [x28, #2864]", + "ldr q5, [x28, #2768]", + "fcvtzs v6.4s, v3.4s", + "fcmgt v3.4s, v5.4s, v3.4s", + "mov v16.16b, v3.16b", + "bsl v16.16b, v6.16b, v4.16b", "frinti v2.4s, v2.4s", - "fcvtzs v2.4s, v2.4s", + "fcvtzs v3.4s, v2.4s", + "fcmgt v2.4s, v5.4s, v2.4s", + "bsl v2.16b, v3.16b, v4.16b", "str q2, [x28, #16]" ] }, "vcvttps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs v16.4s, v17.4s", + "ldr q2, [x28, #2864]", + "ldr q3, [x28, #2768]", + "fcvtzs v4.4s, v17.4s", + "fcmgt v3.4s, v3.4s, v17.4s", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" ] }, "vcvttps2dq ymm0, ymm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 11, "Comment": [ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "fcvtzs v16.4s, v17.4s", - "fcvtzs v2.4s, v2.4s", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2768]", + "fcvtzs v5.4s, v17.4s", + "fcmgt v6.4s, v4.4s, v17.4s", + "mov v16.16b, v6.16b", + "bsl v16.16b, v5.16b, v3.16b", + "fcvtzs v5.4s, v2.4s", + "fcmgt v2.4s, v4.4s, v2.4s", + "bsl v2.16b, v5.16b, v3.16b", "str q2, [x28, #16]" ] }, @@ -3912,7 +3984,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d", "movi v2.2d, #0x0", @@ -3927,7 +3999,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr q4, [x28, #2352]", + "ldr q4, [x28, #2416]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.2d, v17.2d, v5.2d", "eor v3.16b, v3.16b, v4.16b", @@ -3941,7 +4013,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s", "movi v2.2d, #0x0", @@ -3956,7 +4028,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr q4, [x28, #2320]", + "ldr q4, [x28, #2384]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.4s, v17.4s, v5.4s", "eor v3.16b, v3.16b, v4.16b", @@ -4132,7 +4204,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2640]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4148,7 +4220,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #16]", - "ldr q3, [x28, #2576]", + "ldr q3, [x28, #2640]", "cmlt v4.16b, v16.16b, #0", "and v4.16b, v4.16b, v3.16b", "addp v4.16b, v4.16b, v4.16b", @@ -4649,32 +4721,46 @@ ] }, "vcvttpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 11, "Comment": [ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "frintz v16.2d, v17.2d", - "fcvtn v16.2s, v16.2d", - "fcvtzs v16.2s, v16.2s", + "ldr d2, [x28, #2864]", + "ldr q3, [x28, #2816]", + "frintz v4.2d, v17.2d", + "fcvtn v4.2s, v4.2d", + "fcvtzs v4.2s, v4.2s", + "fcmgt v3.2d, v3.2d, v17.2d", + "shrn v3.2s, v3.2d, #32", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" ] }, "vcvttpd2dq xmm0, ymm1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 18, "Comment": [ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "frintz v3.2d, v17.2d", - "fcvtn v3.2s, v3.2d", - "fcvtzs v3.2s, v3.2s", - "frintz v2.2d, v2.2d", - "fcvtn v2.2s, v2.2d", - "fcvtzs v2.2s, v2.2s", - "zip1 v16.2d, v3.2d, v2.2d", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "frintz v5.2d, v17.2d", + "fcvtn v5.2s, v5.2d", + "fcvtzs v5.2s, v5.2s", + "fcmgt v6.2d, v4.2d, v17.2d", + "shrn v6.2s, v6.2d, #32", + "bif v5.16b, v3.16b, v6.16b", + "frintz v6.2d, v2.2d", + "fcvtn v6.2s, v6.2d", + "fcvtzs v6.2s, v6.2s", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "bsl v2.16b, v6.16b, v3.16b", + "zip1 v16.2d, v5.2d, v2.2d", "movi v2.2d, #0x0", "str q2, [x28, #16]" ] @@ -4705,31 +4791,48 @@ ] }, "vcvtpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 12, "Comment": [ "Map 1 0b11 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "frinti v16.2d, v17.2d", - "fcvtn v16.2s, v16.2d", - "fcvtzs v16.2s, v16.2s", + "frinti v2.2d, v17.2d", + "ldr d3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "frintz v5.2d, v2.2d", + "fcvtn v5.2s, v5.2d", + "fcvtzs v5.2s, v5.2s", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" ] }, "vcvtpd2dq xmm0, ymm1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 20, "Comment": [ "Map 1 0b11 0xe6 256-bit" ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "frinti v3.2d, v17.2d", - "fcvtn v3.2s, v3.2d", - "fcvtzs v3.2s, v3.2s", + "ldr q4, [x28, #2864]", + "ldr q5, [x28, #2816]", + "frintz v6.2d, v3.2d", + "fcvtn v6.2s, v6.2d", + "fcvtzs v6.2s, v6.2s", + "fcmgt v3.2d, v5.2d, v3.2d", + "shrn v3.2s, v3.2d, #32", + "bsl v3.16b, v6.16b, v4.16b", "frinti v2.2d, v2.2d", - "fcvtn v2.2s, v2.2d", - "fcvtzs v2.2s, v2.2s", + "frintz v6.2d, v2.2d", + "fcvtn v6.2s, v6.2d", + "fcvtzs v6.2s, v6.2s", + "fcmgt v2.2d, v5.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "bsl v2.16b, v6.16b, v4.16b", "zip1 v16.2d, v3.2d, v2.2d", "movi v2.2d, #0x0", "str q2, [x28, #16]" diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index b5e2ebb39..cbf4d0eed 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -1964,7 +1964,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2288]", + "ldr q2, [x28, #2352]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -4548,7 +4548,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4566,7 +4566,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4582,7 +4582,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4600,7 +4600,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4616,7 +4616,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4634,7 +4634,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4650,7 +4650,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4668,7 +4668,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -5656,7 +5656,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5674,7 +5674,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5690,7 +5690,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5708,7 +5708,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5724,7 +5724,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5742,7 +5742,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5758,7 +5758,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5776,7 +5776,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5792,7 +5792,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5809,7 +5809,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5824,7 +5824,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5841,7 +5841,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5856,7 +5856,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5873,7 +5873,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5888,7 +5888,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5905,7 +5905,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index efdf3e2a4..8cbc9d928 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -2850,7 +2850,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2868,7 +2868,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2884,7 +2884,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2902,7 +2902,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2918,7 +2918,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2936,7 +2936,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2952,7 +2952,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2970,7 +2970,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -3938,7 +3938,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3956,7 +3956,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3972,7 +3972,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3990,7 +3990,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4006,7 +4006,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -4024,7 +4024,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -4040,7 +4040,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4058,7 +4058,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4074,7 +4074,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4091,7 +4091,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2320]", + "ldr q5, [x28, #2384]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4106,7 +4106,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4123,7 +4123,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2352]", + "ldr q5, [x28, #2416]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4138,7 +4138,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4155,7 +4155,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2384]", + "ldr q5, [x28, #2448]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4170,7 +4170,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4187,7 +4187,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2416]", + "ldr q5, [x28, #2480]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index 90b355055..266b50dcd 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -343,7 +343,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2480]", + "ldr q2, [x28, #2544]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -355,7 +355,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2560]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -378,7 +378,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2512]", + "ldr q2, [x28, #2576]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -402,7 +402,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2528]", + "ldr q2, [x28, #2592]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -425,7 +425,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2608]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -437,7 +437,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2560]", + "ldr q2, [x28, #2624]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -3576,7 +3576,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3591,7 +3591,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3606,7 +3606,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3621,7 +3621,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3636,7 +3636,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3651,7 +3651,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3666,7 +3666,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3681,7 +3681,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3696,7 +3696,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3711,7 +3711,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3726,7 +3726,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3741,7 +3741,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3756,7 +3756,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3771,7 +3771,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3786,7 +3786,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3801,7 +3801,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3816,7 +3816,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3831,7 +3831,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3846,7 +3846,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3861,7 +3861,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3876,7 +3876,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3891,7 +3891,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3906,7 +3906,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3921,7 +3921,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3936,7 +3936,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3951,7 +3951,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3966,7 +3966,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3981,7 +3981,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -3996,7 +3996,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -4011,7 +4011,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2232]", + "ldr x0, [x28, #2296]", "br x0" ] }, @@ -4022,7 +4022,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #2464]", + "ldr q3, [x28, #2528]", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", "tbl v16.16b, {v16.16b}, v3.16b", @@ -4036,7 +4036,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #2464]", + "ldr q3, [x28, #2528]", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", "tbl v16.16b, {v16.16b}, v3.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index ff742c7dc..a7c88fdfc 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2528]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2528]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 254aad64b..350c00c9c 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -59,13 +59,17 @@ ] }, "pf2id mm0, mm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 9, "Comment": [ "0x0f 0x0f 0x1d" ], "ExpectedArm64ASM": [ "ldr d2, [x28, #1056]", - "fcvtzs v2.2s, v2.2s", + "ldr d3, [x28, #2864]", + "ldr d4, [x28, #2768]", + "fcvtzs v5.2s, v2.2s", + "fcmgt v2.4s, v4.4s, v2.4s", + "bsl v2.8b, v5.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index aa7f38fb1..1782ef241 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -198,10 +198,10 @@ "ldr q19, [x11, #272]", "ldr q24, [x11]", "ldr q23, [x11, #16]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q2, [x0, #2832]", "tbl v16.16b, {v18.16b}, v2.16b", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #432]", "tbl v18.16b, {v19.16b}, v3.16b", "ldr q22, [x11, #32]", @@ -285,7 +285,7 @@ "mov v4.s[1], w21", "mov v20.16b, v4.16b", "mov v20.s[0], w23", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q4, [x0, #224]", "tbl v16.16b, {v16.16b}, v4.16b", "mov w21, v20.s[1]", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 6010289c5..cb84d86fa 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1608,7 +1608,7 @@ "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ "ldr d2, [x28, #1040]", - "ldr d3, [x28, #2576]", + "ldr d3, [x28, #2640]", "cmlt v2.16b, v2.16b, #0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 723429cbe..93f1c2949 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -37,7 +37,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2640]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index a8c31ebc8..8c197a909 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -68,7 +68,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2640]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 1bc61434c..035b4e24c 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -3164,7 +3164,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -4191,7 +4191,7 @@ "lsl w20, w21, w20", "bic w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x22, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -6334,7 +6334,7 @@ "movk w21, #0x6, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -6621,7 +6621,7 @@ "movk w21, #0x6, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -6780,7 +6780,7 @@ "movk w21, #0x1, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 6552e9a8f..ce057ca9b 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -56173,7 +56173,7 @@ "lsl w20, w22, w20", "bic w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -58294,7 +58294,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -58683,7 +58683,7 @@ "add w20, w8, #0x10 (16)", "str s2, [x20]", "uxtb w7, w4", - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "str w7, [x8, #56]", "add w20, w8, #0xc (12)", "mrs x0, nzcv", @@ -58953,7 +58953,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -59334,7 +59334,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -74271,7 +74271,7 @@ "lsl w20, w22, w20", "orr w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -74935,7 +74935,7 @@ "movk w21, #0x79, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index ac0769f95..eb8137771 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -32174,7 +32174,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "cfinv", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -65424,7 +65424,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "strb wzr, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -73422,7 +73422,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "strb wzr, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -97581,7 +97581,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2272]", + "ldr x0, [x28, #2336]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index c1aef6b98..e670270dd 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -4468,7 +4468,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4488,7 +4488,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2624]", + "ldr q2, [x28, #2688]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4508,7 +4508,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2640]", + "ldr q2, [x28, #2704]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4528,7 +4528,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4548,7 +4548,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2672]", + "ldr q2, [x28, #2736]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4568,7 +4568,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2752]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4732,7 +4732,7 @@ "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -5015,7 +5015,7 @@ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index d6bdcb649..8751dc946 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -655,7 +655,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2288]", + "ldr q2, [x28, #2352]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index f34c72d31..dd66c7bb3 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -321,7 +321,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2480]", + "ldr q2, [x28, #2544]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -331,7 +331,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2560]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -350,7 +350,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2512]", + "ldr q2, [x28, #2576]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -370,7 +370,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2528]", + "ldr q2, [x28, #2592]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -389,7 +389,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2608]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -399,7 +399,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2560]", + "ldr q2, [x28, #2624]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -468,7 +468,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2024]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 505de3e10..47b3e39cb 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -2825,7 +2825,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2736]", + "ldr x3, [x28, #2928]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2836,7 +2836,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2752]", + "ldr x3, [x28, #2944]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2894,7 +2894,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2744]", + "ldr x3, [x28, #2936]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2907,7 +2907,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2760]", + "ldr x3, [x28, #2952]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 8013f37de..e2e87690a 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -168,46 +168,62 @@ ] }, "cvttps2pi mm0, [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0x2c", "ExpectedArm64ASM": [ "strb wzr, [x28, #1019]", "mov w20, #0xffff", "ldr d2, [x4]", - "fcvtzs v2.2s, v2.2s", + "ldr d3, [x28, #2864]", + "ldr d4, [x28, #2768]", + "fcvtzs v5.2s, v2.2s", + "fcmgt v2.4s, v4.4s, v2.4s", + "bsl v2.8b, v5.8b, v3.8b", "strb w20, [x28, #1298]", "str d2, [x28, #1040]", "strh w20, [x28, #1048]" ] }, "cvttps2pi mm0, xmm0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtzs v2.2s, v16.2s", + "ldr d2, [x28, #2864]", + "ldr d3, [x28, #2768]", + "fcvtzs v4.2s, v16.2s", + "fcmgt v3.4s, v3.4s, v16.4s", + "bit v2.8b, v4.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" ] }, "cvtps2pi mm0, [rax]": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0x2d", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "frinti v2.2s, v2.2s", - "fcvtzs v2.2s, v2.2s", + "frinti v2.4s, v2.4s", + "ldr d3, [x28, #2864]", + "ldr d4, [x28, #2768]", + "fcvtzs v5.2s, v2.2s", + "fcmgt v2.4s, v4.4s, v2.4s", + "bsl v2.8b, v5.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" ] }, "cvtps2pi mm0, xmm0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0x2d", "ExpectedArm64ASM": [ - "frinti v2.2s, v16.2s", - "fcvtzs v2.2s, v2.2s", + "frinti v2.4s, v16.4s", + "ldr d3, [x28, #2864]", + "ldr d4, [x28, #2768]", + "fcvtzs v5.2s, v2.2s", + "fcmgt v2.4s, v4.4s, v2.4s", + "bsl v2.8b, v5.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" @@ -638,7 +654,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2448]", + "ldr q3, [x28, #2512]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -649,7 +665,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2448]", + "ldr q3, [x28, #2512]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -1092,7 +1108,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x28, #1056]", - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #1040]", @@ -1105,7 +1121,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #1040]", @@ -3384,7 +3400,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3393,7 +3409,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3405,7 +3421,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3513,7 +3529,7 @@ "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ "ldr d2, [x28, #1040]", - "ldr d3, [x28, #2576]", + "ldr d3, [x28, #2640]", "cmlt v2.16b, v2.16b, #0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 9f44d8acf..3be79e6e9 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -123,23 +123,35 @@ ] }, "cvttpd2pi mm0, xmm0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 11, "Comment": "0x66 0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtn v2.2s, v16.2d", - "fcvtzs v2.2s, v2.2s", + "ldr d2, [x28, #2864]", + "ldr q3, [x28, #2816]", + "frintz v4.2d, v16.2d", + "fcvtn v4.2s, v4.2d", + "fcvtzs v4.2s, v4.2s", + "fcmgt v3.2d, v3.2d, v16.2d", + "shrn v3.2s, v3.2d, #32", + "bit v2.8b, v4.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" ] }, "cvtpd2pi mm0, xmm0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 12, "Comment": "0x66 0x0f 0x2d", "ExpectedArm64ASM": [ - "fcvtn v2.2s, v16.2d", - "frinti v2.2s, v2.2s", - "fcvtzs v2.2s, v2.2s", + "frinti v2.2d, v16.2d", + "ldr d3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "frintz v5.2d, v2.2d", + "fcvtn v5.2s, v5.2d", + "fcvtzs v5.2s, v5.2s", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "bsl v2.8b, v5.8b, v3.8b", "str d2, [x28, #1040]", "mov w20, #0xffff", "strh w20, [x28, #1048]" @@ -214,20 +226,30 @@ ] }, "cvtps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0x5b", "ExpectedArm64ASM": [ - "frinti v16.4s, v17.4s", - "fcvtzs v16.4s, v16.4s" + "frinti v2.4s, v17.4s", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2768]", + "fcvtzs v5.4s, v2.4s", + "fcmgt v2.4s, v4.4s, v2.4s", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b" ] }, "cvtps2dq xmm0, [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 8, "Comment": "0xf2 0x0f 0x5b", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "frinti v16.4s, v2.4s", - "fcvtzs v16.4s, v16.4s" + "frinti v2.4s, v2.4s", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2768]", + "fcvtzs v5.4s, v2.4s", + "fcmgt v2.4s, v4.4s, v2.4s", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b" ] }, "subpd xmm0, xmm1": { @@ -515,7 +537,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -529,7 +551,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -643,7 +665,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1992]", + "ldr x0, [x28, #2056]", "ldr q3, [x0, #2480]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1184,7 +1206,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] @@ -1240,7 +1262,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2640]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -1360,12 +1382,18 @@ ] }, "cvttpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0x66 0x0f 0xe6", "ExpectedArm64ASM": [ - "frintz v16.2d, v17.2d", - "fcvtn v16.2s, v16.2d", - "fcvtzs v16.2s, v16.2s" + "ldr d2, [x28, #2864]", + "ldr q3, [x28, #2816]", + "frintz v4.2d, v17.2d", + "fcvtn v4.2s, v4.2d", + "fcvtzs v4.2s, v4.2s", + "fcmgt v3.2d, v3.2d, v17.2d", + "shrn v3.2s, v3.2d, #32", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b" ] }, "movntdq [rax], xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 540e2f7f9..f98e9b397 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -111,67 +111,115 @@ ] }, "cvttss2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtzs w4, s16" + "fcvtzs w20, s16", + "mov w21, #0x80000000", + "ldr s2, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvttss2si eax, dword [rbx]": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0x2c", "ExpectedArm64ASM": [ "ldr s2, [x6]", - "fcvtzs w4, s2" + "fcvtzs w20, s2", + "mov w21, #0x80000000", + "ldr s3, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvttss2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtzs x4, s16" + "fcvtzs x20, s16", + "mov x21, #0x8000000000000000", + "ldr s2, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvttss2si rax, dword [rbx]": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0x2c", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "fcvtzs x4, s2" + "fcvtzs x20, s2", + "mov x21, #0x8000000000000000", + "ldr s3, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtss2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0x2d", "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs w4, s0" + "frinti s2, s16", + "fcvtzs w20, s2", + "mov w21, #0x80000000", + "ldr s3, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvtss2si eax, dword [rbx]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0xf3 0x0f 0x2d", "ExpectedArm64ASM": [ "ldr s2, [x6]", - "frinti s0, s2", - "fcvtzs w4, s0" + "frinti s2, s2", + "fcvtzs w20, s2", + "mov w21, #0x80000000", + "ldr s3, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvtss2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0x2d", "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs x4, s0" + "frinti s2, s16", + "fcvtzs x20, s2", + "mov x21, #0x8000000000000000", + "ldr s3, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtss2si rax, dword [rbx]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0xf3 0x0f 0x2d", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "frinti s0, s2", - "fcvtzs x4, s0" + "frinti s2, s2", + "fcvtzs x20, s2", + "mov x21, #0x8000000000000000", + "ldr s3, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "sqrtss xmm0, xmm1": { @@ -243,10 +291,15 @@ ] }, "cvttps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 6, "Comment": "0xf3 0x0f 0x5b", "ExpectedArm64ASM": [ - "fcvtzs v16.4s, v17.4s" + "ldr q2, [x28, #2864]", + "ldr q3, [x28, #2768]", + "fcvtzs v4.4s, v17.4s", + "fcmgt v3.4s, v3.4s, v17.4s", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b" ] }, "subss xmm0, xmm1": { @@ -342,7 +395,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -355,7 +408,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1984]", + "ldr x0, [x28, #2048]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 5a3bcbdc2..ab48ac300 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -96,67 +96,115 @@ ] }, "cvttsd2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": "0xf2 0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtzs w4, d16" + "fcvtzs w20, d16", + "mov w21, #0x80000000", + "ldr d2, [x28, #2816]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvttsd2si eax, qword [rbx]": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf2 0x0f 0x2c", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "fcvtzs w4, d2" + "fcvtzs w20, d2", + "mov w21, #0x80000000", + "ldr d3, [x28, #2816]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "cvttsd2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": "0xf2 0x0f 0x2c", "ExpectedArm64ASM": [ - "fcvtzs x4, d16" + "fcvtzs x20, d16", + "mov x21, #0x8000000000000000", + "ldr d2, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvttsd2si rax, qword [rbx]": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf2 0x0f 0x2c", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "fcvtzs x4, d2" + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtsd2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf2 0x0f 0x2d", "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtsd2si eax, qword [rbx]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0xf2 0x0f 0x2d", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "frinti d0, d2", - "fcvtzs x4, d0" + "frinti d2, d2", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtsd2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": "0xf2 0x0f 0x2d", "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "cvtsd2si rax, qword [rbx]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0xf2 0x0f 0x2d", "ExpectedArm64ASM": [ "ldr d2, [x6]", - "frinti d0, d2", - "fcvtzs x4, d0" + "frinti d2, d2", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "sqrtsd xmm0, xmm1": { @@ -284,7 +332,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -297,7 +345,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1976]", + "ldr x0, [x28, #2040]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -453,7 +501,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] @@ -468,12 +516,19 @@ ] }, "cvtpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 10, "Comment": "0xf2 0x0f 0xe6", "ExpectedArm64ASM": [ - "frinti v16.2d, v17.2d", - "fcvtn v16.2s, v16.2d", - "fcvtzs v16.2s, v16.2s" + "frinti v2.2d, v17.2d", + "ldr d3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "frintz v5.2d, v2.2d", + "fcvtn v5.2s, v5.2d", + "fcvtzs v5.2s, v5.2s", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b" ] }, "lddqu xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index 7f61fda1a..485bf0505 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -12,13 +12,19 @@ }, "Instructions": { "cvtpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0xf2 0x0f 0xe6", "ExpectedArm64ASM": [ - "frinti z16.d, p6/m, z17.d", - "fcvtzs z16.s, p6/m, z16.d", - "uzp1 z16.s, z16.s, z16.s", - "mov v16.8b, v16.8b" + "frinti v2.2d, v17.2d", + "ldr d3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "fcvtzs z5.s, p6/m, z2.d", + "uzp1 z5.s, z5.s, z5.s", + "mov v5.8b, v5.8b", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "movprfx z16, z5", + "bsl z16.d, z16.d, z3.d, z2.d" ] } } diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 04159d40f..1eeafb218 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -2801,7 +2801,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2870,7 +2870,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2939,7 +2939,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2000]", + "ldr x0, [x28, #2064]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -3277,79 +3277,127 @@ ] }, "vcvttss2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b10 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs w4, s16" + "fcvtzs w20, s16", + "mov w21, #0x80000000", + "ldr s2, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvttss2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b10 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs x4, s16" + "fcvtzs x20, s16", + "mov x21, #0x8000000000000000", + "ldr s2, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s2, s16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvttsd2si eax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b11 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs w4, d16" + "fcvtzs w20, d16", + "mov w21, #0x80000000", + "ldr d2, [x28, #2816]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvttsd2si rax, xmm0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b11 0x2c 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs x4, d16" + "fcvtzs x20, d16", + "mov x21, #0x8000000000000000", + "ldr d2, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d2, d16", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtss2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b10 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs w4, s0" + "frinti s2, s16", + "fcvtzs w20, s2", + "mov w21, #0x80000000", + "ldr s3, [x28, #2768]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel w4, w20, w21, gt", + "msr nzcv, x22" ] }, "vcvtss2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b10 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti s0, s16", - "fcvtzs x4, s0" + "frinti s2, s16", + "fcvtzs x20, s2", + "mov x21, #0x8000000000000000", + "ldr s3, [x28, #2800]", + "mrs x22, nzcv", + "fcmp s3, s2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtsd2si eax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b11 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vcvtsd2si rax, xmm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 8, "Comment": [ "Map 1 0b11 0x2d 128-bit" ], "ExpectedArm64ASM": [ - "frinti d0, d16", - "fcvtzs x4, d0" + "frinti d2, d16", + "fcvtzs x20, d2", + "mov x21, #0x8000000000000000", + "ldr d3, [x28, #2848]", + "mrs x22, nzcv", + "fcmp d3, d2", + "csel x4, x20, x21, gt", + "msr nzcv, x22" ] }, "vucomiss xmm0, xmm1": { @@ -3602,41 +3650,73 @@ ] }, "vcvtps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 7, "Comment": [ "Map 1 0b01 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "frinti v16.4s, v17.4s", - "fcvtzs v16.4s, v16.4s" + "frinti v2.4s, v17.4s", + "ldr q3, [x28, #2864]", + "ldr q4, [x28, #2768]", + "fcvtzs v5.4s, v2.4s", + "fcmgt v2.4s, v4.4s, v2.4s", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b" ] }, "vcvtps2dq ymm0, ymm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 13, "Comment": [ "Map 1 0b01 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "frinti z16.s, p7/m, z17.s", - "fcvtzs z16.s, p7/m, z16.s" + "frinti z2.s, p7/m, z17.s", + "ldr x0, [x28, #2024]", + "ld1b {z3.b}, p7/z, [x0]", + "ldr x0, [x28, #1976]", + "ld1b {z4.b}, p7/z, [x0]", + "fcvtzs z5.s, p7/m, z2.s", + "fcmgt p0.s, p7/z, z4.s, z2.s", + "not z0.s, p0/m, z4.s", + "movprfx z2.s, p0/z, z4.s", + "orr z2.s, p0/m, z2.s, z0.s", + "movprfx z0, z5", + "bsl z0.d, z0.d, z3.d, z2.d", + "mov z16.d, z0.d" ] }, "vcvttps2dq xmm0, xmm1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 6, "Comment": [ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs v16.4s, v17.4s" + "ldr q2, [x28, #2864]", + "ldr q3, [x28, #2768]", + "fcvtzs v4.4s, v17.4s", + "fcmgt v3.4s, v3.4s, v17.4s", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b" ] }, "vcvttps2dq ymm0, ymm1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 12, "Comment": [ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "fcvtzs z16.s, p7/m, z17.s" + "ldr x0, [x28, #2024]", + "ld1b {z2.b}, p7/z, [x0]", + "ldr x0, [x28, #1976]", + "ld1b {z3.b}, p7/z, [x0]", + "fcvtzs z4.s, p7/m, z17.s", + "fcmgt p0.s, p7/z, z3.s, z17.s", + "not z0.s, p0/m, z3.s", + "movprfx z3.s, p0/z, z3.s", + "orr z3.s, p0/m, z3.s, z0.s", + "movprfx z0, z4", + "bsl z0.d, z0.d, z2.d, z3.d", + "mov z16.d, z0.d" ] }, "vsubps xmm0, xmm1, xmm2": { @@ -4360,7 +4440,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4383,7 +4463,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4520,7 +4600,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2640]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4907,25 +4987,43 @@ ] }, "vcvttpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": [ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "fcvtzs z16.s, p6/m, z17.d", - "uzp1 z16.s, z16.s, z16.s", - "mov v16.8b, v16.8b" + "ldr d2, [x28, #2864]", + "ldr q3, [x28, #2816]", + "fcvtzs z4.s, p6/m, z17.d", + "uzp1 z4.s, z4.s, z4.s", + "mov v4.8b, v4.8b", + "fcmgt v3.2d, v3.2d, v17.2d", + "shrn v3.2s, v3.2d, #32", + "mov v16.16b, v3.16b", + "bsl v16.16b, v4.16b, v2.16b" ] }, "vcvttpd2dq xmm0, ymm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 15, "Comment": [ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "fcvtzs z16.s, p7/m, z17.d", - "uzp1 z16.s, z16.s, z16.s", - "mov v16.16b, v16.16b" + "ldr q2, [x28, #2864]", + "ldr x0, [x28, #2000]", + "ld1b {z3.b}, p7/z, [x0]", + "fcvtzs z4.s, p7/m, z17.d", + "uzp1 z4.s, z4.s, z4.s", + "mov v4.16b, v4.16b", + "fcmgt p0.d, p7/z, z3.d, z17.d", + "not z0.d, p0/m, z3.d", + "movprfx z3.d, p0/z, z3.d", + "orr z3.d, p0/m, z3.d, z0.d", + "shrnb z3.s, z3.d, #32", + "uzp1 z3.s, z3.s, z3.s", + "movprfx z0, z4", + "bsl z0.d, z0.d, z2.d, z3.d", + "mov z16.d, z0.d" ] }, "vcvtdq2pd xmm0, xmm1": { @@ -4949,27 +5047,45 @@ ] }, "vcvtpd2dq xmm0, xmm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": [ "Map 1 0b11 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "frinti z16.d, p6/m, z17.d", - "fcvtzs z16.s, p6/m, z16.d", - "uzp1 z16.s, z16.s, z16.s", - "mov v16.8b, v16.8b" + "frinti v2.2d, v17.2d", + "ldr d3, [x28, #2864]", + "ldr q4, [x28, #2816]", + "fcvtzs z5.s, p6/m, z2.d", + "uzp1 z5.s, z5.s, z5.s", + "mov v5.8b, v5.8b", + "fcmgt v2.2d, v4.2d, v2.2d", + "shrn v2.2s, v2.2d, #32", + "mov v16.16b, v2.16b", + "bsl v16.16b, v5.16b, v3.16b" ] }, "vcvtpd2dq xmm0, ymm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 16, "Comment": [ "Map 1 0b11 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "frinti z16.d, p7/m, z17.d", - "fcvtzs z16.s, p7/m, z16.d", - "uzp1 z16.s, z16.s, z16.s", - "mov v16.16b, v16.16b" + "frinti z2.d, p7/m, z17.d", + "ldr q3, [x28, #2864]", + "ldr x0, [x28, #2000]", + "ld1b {z4.b}, p7/z, [x0]", + "fcvtzs z5.s, p7/m, z2.d", + "uzp1 z5.s, z5.s, z5.s", + "mov v5.16b, v5.16b", + "fcmgt p0.d, p7/z, z4.d, z2.d", + "not z0.d, p0/m, z4.d", + "movprfx z2.d, p0/z, z4.d", + "orr z2.d, p0/m, z2.d, z0.d", + "shrnb z2.s, z2.d, #32", + "uzp1 z2.s, z2.s, z2.s", + "movprfx z0, z5", + "bsl z0.d, z0.d, z3.d, z2.d", + "mov z16.d, z0.d" ] }, "vmovntdq [rax], xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 05484a68c..953550846 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1603,7 +1603,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2288]", + "ldr q2, [x28, #2352]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3657,7 +3657,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3683,7 +3683,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3709,7 +3709,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3735,7 +3735,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4609,7 +4609,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4635,7 +4635,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4661,7 +4661,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4687,7 +4687,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4713,7 +4713,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2320]", + "ldr q2, [x28, #2384]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4738,7 +4738,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2352]", + "ldr q2, [x28, #2416]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4763,7 +4763,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2384]", + "ldr q2, [x28, #2448]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4788,7 +4788,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2416]", + "ldr q2, [x28, #2480]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 15691167c..50326dd5f 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -5372,7 +5372,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2528]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -5385,7 +5385,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2528]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 18227db45..e4ee32aa6 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -4467,7 +4467,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4487,7 +4487,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2624]", + "ldr q2, [x28, #2688]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4507,7 +4507,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2640]", + "ldr q2, [x28, #2704]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4527,7 +4527,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4547,7 +4547,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2672]", + "ldr q2, [x28, #2736]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4567,7 +4567,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2752]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4731,7 +4731,7 @@ "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -5014,7 +5014,7 @@ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2672]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", diff --git a/unittests/gcc-target-tests-64/Known_Failures b/unittests/gcc-target-tests-64/Known_Failures index 46d1bc6c3..d7b0bdcd0 100644 --- a/unittests/gcc-target-tests-64/Known_Failures +++ b/unittests/gcc-target-tests-64/Known_Failures @@ -12,13 +12,3 @@ asm-5.c.gcc-target-test-64 # Which turns the value in to 0xfffff2f5 # This causes its comparison to fail sse2-mmx-pextrw.c.gcc-target-test-64 - -# These tests fail because of things unrelated to the sse4.1 instructions -sse4_1-ceil-sfix-vec.c.gcc-target-test-64 -sse4_1-ceilf-sfix-vec.c.gcc-target-test-64 -sse4_1-floor-sfix-vec.c.gcc-target-test-64 -sse4_1-floorf-sfix-vec.c.gcc-target-test-64 -sse4_1-rint-sfix-vec.c.gcc-target-test-64 -sse4_1-rintf-sfix-vec.c.gcc-target-test-64 -sse4_1-round-sfix-vec.c.gcc-target-test-64 -sse4_1-roundf-sfix-vec.c.gcc-target-test-64