From d23bb01e963e45eb4a6ffca1074d5b414178463f Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 9 Jul 2025 14:43:54 -0400 Subject: [PATCH] JIT: fix divisor masking oversight. should fix Steam. Fixes: de4becc26 ("OpcodeDispatcher: mask certain divisors") Closes: #4652 Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/JIT/ALUOps.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp index 5ff4caac0..c1d3b1d3f 100644 --- a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp @@ -969,11 +969,15 @@ DEF_OP(UDiv) { break; } case IR::OpSize::i32Bit: { + // We need to mask divisor if we have Upper bits, since the frontend does + // not on the hope that we can optimize to use the path above. + mov(ARMEmitter::Size::i32Bit, TMP2, Divisor); + // TODO: 32-bit operation should be guaranteed not to leave garbage in the upper bits. mov(EmitSize, TMP1, Lower); bfi(EmitSize, TMP1, Upper, 32, 32); - udiv(EmitSize, Quotient, TMP1, Divisor); - msub(EmitSize, Remainder, Quotient, Divisor, TMP1); + udiv(EmitSize, Quotient, TMP1, TMP2); + msub(EmitSize, Remainder, Quotient, TMP2, TMP1); break; } case IR::OpSize::i64Bit: {