diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index d4f267b83..c7178eca2 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -138,7 +138,6 @@ set (SRCS Interface/IR/IREmitter.cpp Interface/IR/PassManager.cpp Interface/IR/Passes/ConstProp.cpp - Interface/IR/Passes/DeadContextStoreElimination.cpp Interface/IR/Passes/IRDumperPass.cpp Interface/IR/Passes/IRValidation.cpp Interface/IR/Passes/RAValidation.cpp diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index 56c8b900b..a4e52061f 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -614,6 +614,20 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue DecodedInfo = &Block.DecodedInstructions[i]; bool IsLocked = DecodedInfo->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK; + // Do a partial register cache flush before every instruction. This + // prevents cross-instruction static register caching, while allowing + // context load/stores to be optimized within a block. Theoretically, + // this flush is not required for correctness, all mandatory flushes are + // included in instruction-specific handlers. Instead, this is a blunt + // heuristic to make the register cache less aggressive, as the current + // RA generates bad code in common cases with tied registers otherwise. + // + // However, it makes our exception handling behaviour more predictable. + // It is potentially correctness bearing in that sense, but that is a + // side effect here and (if that behaviour is required) we should handle + // that more explicitly later. + Thread->OpDispatcher->FlushRegisterCache(true); + if (ExtendedDebugInfo || Thread->OpDispatcher->CanHaveSideEffects(TableInfo, DecodedInfo)) { Thread->OpDispatcher->_GuestOpcode(Block.Entry + BlockInstructionsLength - GuestRIP); } diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 1423999db..e1165d745 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -625,7 +625,7 @@ DEF_OP(ShiftFlags) { // Set the output outside the branch to avoid needing an extra leg of the // branch. We specifically do not hardcode the PF register anywhere (relying - // on a tied SRA register instead) to avoid fighting with RA/RCLSE. + // on a tied SRA register instead) to avoid fighting with RA. if (PFTemp != PFInput) { mov(ARMEmitter::Size::i64Bit, PFTemp, PFInput); } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 2196a528e..484c4a883 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -3366,8 +3366,8 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { auto Src2 = _LoadMem(GPRClass, Size, Dest_RSI, Size); // We'll calculate PF/AF after the loop, so use them as temporaries here. - _StoreRegister(Src1, Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize()); - _StoreRegister(Src2, Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize()); + StoreRegister(Core::CPUState::PF_AS_GREG, false, Src1); + StoreRegister(Core::CPUState::AF_AS_GREG, false, Src2); Ref TailCounter = LoadGPRRegister(X86State::REG_RCX); @@ -3406,8 +3406,8 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { // Make sure to start a new block after ending this one { // Grab the sources from the last iteration so we can set flags. - auto Src1 = _LoadRegister(Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize()); - auto Src2 = _LoadRegister(Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize()); + auto Src1 = LoadGPR(Core::CPUState::PF_AS_GREG); + auto Src2 = LoadGPR(Core::CPUState::AF_AS_GREG); GenerateFlags_SUB(Op, Src2, Src1); } auto Jump_ = Jump(); @@ -4362,7 +4362,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T const auto highIndex = Operand.Data.GPR.HighBits ? 1 : 0; if (gpr >= FEXCore::X86State::REG_MM_0) { - A.Base = _LoadContext(OpSize, FPRClass, offsetof(FEXCore::Core::CPUState, mm[gpr - FEXCore::X86State::REG_MM_0])); + A.Base = LoadContext(MM0Index + gpr - FEXCore::X86State::REG_MM_0); } else if (gpr >= FEXCore::X86State::REG_XMM_0) { const auto gprIndex = gpr - X86State::REG_XMM_0; @@ -4399,7 +4399,7 @@ Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, int8_t Size, uint8_t Offset if (Size == -1) { Size = GPRSize; } - Ref Reg = _LoadRegister(GPR, GPRClass, GPRSize); + Ref Reg = LoadGPR(GPR); if ((!AllowUpperGarbage && (Size != GPRSize)) || Offset != 0) { // Extract the subregister if requested. @@ -4413,11 +4413,6 @@ Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, int8_t Size, uint8_t Offset return Reg; } -Ref OpDispatchBuilder::LoadXMMRegister(uint32_t XMM) { - const auto VectorSize = CTX->HostFeatures.SupportsSVE256 ? 32 : 16; - return _LoadRegister(XMM, FPRClass, VectorSize); -} - void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, const Ref Src, int8_t Size, uint8_t Offset) { const uint8_t GPRSize = CTX->GetGPRSize(); if (Size == -1) { @@ -4427,16 +4422,14 @@ void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, const Ref Src, int8_t Siz Ref Reg = Src; if (Size != GPRSize || Offset != 0) { // Need to do an insert if not automatic size or zero offset. - Reg = LoadGPRRegister(GPR); - Reg = _Bfi(IR::SizeToOpSize(GPRSize), Size * 8, Offset, Reg, Src); + Reg = _Bfi(IR::SizeToOpSize(GPRSize), Size * 8, Offset, LoadGPRRegister(GPR), Src); } - _StoreRegister(Reg, GPR, GPRClass, GPRSize); + StoreRegister(GPR, false, Reg); } void OpDispatchBuilder::StoreXMMRegister(uint32_t XMM, const Ref Src) { - const auto VectorSize = CTX->HostFeatures.SupportsSVE256 ? 32 : 16; - _StoreRegister(Src, XMM, FPRClass, VectorSize); + StoreRegister(XMM, true, Src); } Ref OpDispatchBuilder::LoadSource(RegisterClassType Class, const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, @@ -4455,7 +4448,8 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl const auto gpr = Operand.Data.GPR.GPR; if (gpr >= FEXCore::X86State::REG_MM_0) { - _StoreContext(OpSize, Class, Src, offsetof(FEXCore::Core::CPUState, mm[gpr - FEXCore::X86State::REG_MM_0])); + LOGMAN_THROW_A_FMT(OpSize == 8, "full"); + StoreContext(MM0Index + gpr - FEXCore::X86State::REG_MM_0, Src); } else if (gpr >= FEXCore::X86State::REG_XMM_0) { const auto gprIndex = gpr - X86State::REG_XMM_0; const auto VectorSize = CTX->HostFeatures.SupportsSVE256 ? 32 : 16; @@ -4543,6 +4537,8 @@ void OpDispatchBuilder::ResetWorkingList() { DecodeFailure = false; ShouldDump = false; CurrentCodeBlock = nullptr; + RegCache.Written = 0; + RegCache.Cached = 0; } void OpDispatchBuilder::UnhandledOp(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 147f6e766..e7d1aeead 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -1266,6 +1267,50 @@ public: } } + void FlushRegisterCache(bool SRAOnly = false) { + CalculateDeferredFlags(); + + const uint8_t GPRSize = CTX->GetGPRSize(); + const auto VectorSize = CTX->HostFeatures.SupportsSVE256 ? 32 : 16; + + // Write backwards. This is a heuristic to improve coalescing, since we + // often copy from (low) fixed GPRs to (high) PF/AF for celebrity + // instructions like "add rax, 1". This hack will go away with clauses. + uint64_t Bits = RegCache.Written; + + // We have an SRA only mode that exists as a hack to make register caching + // less aggressive. We should get rid of this once RA can take it. + uint64_t Mask = ~0ULL; + + if (SRAOnly) { + const uint64_t GPRMask = ((1ull << (AFIndex - GPR0Index + 1)) - 1) << GPR0Index; + const uint64_t FPRMask = ((1ull << (FPR15Index - FPR0Index + 1)) - 1) << FPR0Index; + + Mask &= (GPRMask | FPRMask); + Bits &= Mask; + } + + while (Bits != 0) { + uint32_t Index = 63 - std::countl_zero(Bits); + Ref Value = RegCache.Value[Index]; + + if (Index >= GPR0Index && Index <= AFIndex) { + _StoreRegister(Value, Index - GPR0Index, GPRClass, GPRSize); + } else if (Index >= FPR0Index && Index <= FPR15Index) { + _StoreRegister(Value, Index - FPR0Index, FPRClass, VectorSize); + } else if (Index == DFIndex) { + _StoreFlag(Value, X86State::RFLAG_DF_RAW_LOC); + } else { + _StoreContext(CacheIndexToSize(Index), CacheIndexClass(Index), Value, CacheIndexToContextOffset(Index)); + } + + Bits &= ~(1ull << Index); + } + + RegCache.Written &= ~Mask; + RegCache.Cached &= ~Mask; + } + protected: void SaveNZCV(IROps Op = OP_DUMMY) override { /* Some opcodes are conservatively marked as clobbering flags, but in fact @@ -1483,7 +1528,6 @@ private: void UpdatePrefixFromSegment(Ref Segment, uint32_t SegmentReg); Ref LoadGPRRegister(uint32_t GPR, int8_t Size = -1, uint8_t Offset = 0, bool AllowUpperGarbage = false); - Ref LoadXMMRegister(uint32_t XMM); void StoreGPRRegister(uint32_t GPR, const Ref Src, int8_t Size = -1, uint8_t Offset = 0); void StoreXMMRegister(uint32_t XMM, const Ref Src); @@ -1699,9 +1743,9 @@ private: if (IsNZCV(BitOffset)) { InsertNZCV(BitOffset, Value, ValueOffset, MustMask); } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) { - _StoreRegister(Value, Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize()); + StoreRegister(Core::CPUState::PF_AS_GREG, false, Value); } else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) { - _StoreRegister(Value, Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize()); + StoreRegister(Core::CPUState::AF_AS_GREG, false, Value); } else { if (ValueOffset || MustMask) { Value = _Bfe(OpSize::i32Bit, 1, ValueOffset, Value); @@ -1709,10 +1753,10 @@ private: // For DF, we need to transform 0/1 into 1/-1 if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) { - Value = _SubShift(OpSize::i64Bit, _Constant(1), Value, ShiftType::LSL, 1); + StoreDF(_SubShift(OpSize::i64Bit, _Constant(1), Value, ShiftType::LSL, 1)); + } else { + _StoreFlag(Value, BitOffset); } - - _StoreFlag(Value, BitOffset); } } @@ -1728,10 +1772,13 @@ private: void InvalidateAF() { _InvalidateFlags((1u << X86State::RFLAG_AF_RAW_LOC)); + InvalidateReg(Core::CPUState::AF_AS_GREG); } void InvalidatePF_AF() { _InvalidateFlags((1u << X86State::RFLAG_PF_RAW_LOC) | (1u << X86State::RFLAG_AF_RAW_LOC)); + InvalidateReg(Core::CPUState::PF_AS_GREG); + InvalidateReg(Core::CPUState::AF_AS_GREG); } CondClassType CondForNZCVBit(unsigned BitOffset, bool Invert) { @@ -1748,8 +1795,114 @@ private: } } - void FlushRegisterCache() { - CalculateDeferredFlags(); + /* Layout of cache indices. We use a single 64-bit bitmask for the cache */ + static const int GPR0Index = 0; + static const int GPR15Index = 15; + static const int PFIndex = 16; + static const int AFIndex = 17; + /* Gap 18..19 */ + static const int MM0Index = 20; + static const int MM7Index = 27; + static const int AbridgedFTWIndex = 28; + /* Gap 29..30 */ + static const int DFIndex = 31; + static const int FPR0Index = 32; + static const int FPR15Index = 47; + static const int AVXHigh0Index = 48; + static const int AVXHigh15Index = 63; + + int CacheIndexToContextOffset(int Index) { + switch (Index) { + case MM0Index ... MM7Index: return offsetof(FEXCore::Core::CPUState, mm[Index - MM0Index]); + case AVXHigh0Index ... AVXHigh15Index: return offsetof(FEXCore::Core::CPUState, avx_high[Index - AVXHigh0Index][0]); + case AbridgedFTWIndex: return offsetof(FEXCore::Core::CPUState, AbridgedFTW); + default: return -1; + } + } + + RegisterClassType CacheIndexClass(int Index) { + if ((Index >= MM0Index && Index <= MM7Index) || Index >= FPR0Index) { + return FPRClass; + } else { + return GPRClass; + } + } + + unsigned CacheIndexToSize(int Index) { + if (Index >= AVXHigh0Index) { + return 16; + } else if (Index <= MM7Index) { + return 8; + } else { + return 1; + } + } + + struct { + uint64_t Cached; + uint64_t Written; + Ref Value[64]; + } RegCache {}; + + void InvalidateReg(uint8_t Index) { + uint64_t Bit = (1ull << (uint64_t)Index); + RegCache.Cached &= ~Bit; + RegCache.Written &= ~Bit; + } + + Ref LoadRegCache(uint64_t Offset, uint8_t Index, RegisterClassType RegClass, uint8_t Size) { + LOGMAN_THROW_AA_FMT(Index < 64, "valid index"); + uint64_t Bit = (1ull << (uint64_t)Index); + + if (!(RegCache.Cached & Bit)) { + if (Index == DFIndex) { + RegCache.Value[Index] = _LoadDF(); + } else if ((Index >= MM0Index && Index <= AbridgedFTWIndex) || Index >= AVXHigh0Index) { + RegCache.Value[Index] = _LoadContext(Size, RegClass, Offset); + } else { + RegCache.Value[Index] = _LoadRegister(Offset, RegClass, Size); + } + + RegCache.Cached |= Bit; + } + + return RegCache.Value[Index]; + } + + Ref LoadGPR(uint8_t Reg) { + return LoadRegCache(Reg, GPR0Index + Reg, GPRClass, CTX->GetGPRSize()); + } + + Ref LoadContext(uint8_t Index) { + return LoadRegCache(CacheIndexToContextOffset(Index), Index, CacheIndexClass(Index), CacheIndexToSize(Index)); + } + + Ref LoadXMMRegister(uint8_t Reg) { + const auto Size = CTX->HostFeatures.SupportsSVE256 ? 32 : 16; + return LoadRegCache(Reg, FPR0Index + Reg, FPRClass, Size); + } + + Ref LoadDF() { + return LoadGPR(DFIndex); + } + + void StoreContext(uint8_t Index, Ref Value) { + LOGMAN_THROW_AA_FMT(Index < 64, "valid index"); + LOGMAN_THROW_AA_FMT(Value != InvalidNode, "storing valid"); + + uint64_t Bit = (1ull << (uint64_t)Index); + + RegCache.Value[Index] = Value; + RegCache.Cached |= Bit; + RegCache.Written |= Bit; + } + + void StoreRegister(uint8_t Reg, bool FPR, Ref Value) { + StoreContext(Reg + (FPR ? FPR0Index : GPR0Index), Value); + } + + void StoreDF(Ref Value) { + StoreContext(DFIndex, Value); } Ref GetRFLAG(unsigned BitOffset, bool Invert = false) { @@ -1768,12 +1921,12 @@ private: return _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(BitOffset, Invert), _Constant(1), _Constant(0)); } } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) { - return _LoadRegister(Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize()); + return LoadGPR(Core::CPUState::PF_AS_GREG); } else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) { - return _LoadRegister(Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize()); + return LoadGPR(Core::CPUState::AF_AS_GREG); } else if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) { // Recover the sign bit, it is the logical DF value - return _Lshr(OpSize::i64Bit, _LoadDF(), _Constant(63)); + return _Lshr(OpSize::i64Bit, LoadDF(), _Constant(63)); } else { return _LoadFlag(BitOffset); } @@ -1781,7 +1934,7 @@ private: // Returns (DF ? -Size : Size) Ref LoadDir(const unsigned Size) { - auto Dir = _LoadDF(); + auto Dir = LoadDF(); auto Shift = FEXCore::ilog2(Size); if (Shift) { @@ -1795,7 +1948,7 @@ private: Ref OffsetByDir(Ref X, const unsigned Size) { auto Shift = FEXCore::ilog2(Size); - return _AddShift(OpSize::i64Bit, X, _LoadDF(), ShiftType::LSL, Shift); + return _AddShift(OpSize::i64Bit, X, LoadDF(), ShiftType::LSL, Shift); } // Compares two floats and sets flags for a COMISS instruction @@ -1992,7 +2145,6 @@ private: // Future ideas: Use an invalidation mask to do partial generation of flags. // Particularly for the instructions that don't do the full set of flags calculations. // These instructions currently calculate the deferred RFLAGS immediately then overwrite rflags state. - // RCLSE IR pass will catch and remove redundant rflags stores like this currently. struct DeferredFlagData { // What type of flags to generate FlagsGenerationType Type {FlagsGenerationType::TYPE_NONE}; diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index fb916b7d2..9417c9781 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -530,17 +530,17 @@ void OpDispatchBuilder::AVX128_StoreResult_WithOpSize(FEXCore::X86Tables::Decode Ref OpDispatchBuilder::AVX128_LoadXMMRegister(uint32_t XMM, bool High) { if (High) { - return _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, avx_high[XMM][0])); + return LoadContext(AVXHigh0Index + XMM); } else { - return _LoadRegister(XMM, FPRClass, 16); + return LoadXMMRegister(XMM); } } void OpDispatchBuilder::AVX128_StoreXMMRegister(uint32_t XMM, const Ref Src, bool High) { if (High) { - _StoreContext(16, FPRClass, Src, offsetof(FEXCore::Core::CPUState, avx_high[XMM][0])); + StoreContext(AVXHigh0Index + XMM, Src); } else { - _StoreRegister(Src, XMM, FPRClass, 16); + StoreXMMRegister(XMM, Src); } } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index cc8bd58c2..a02dbcb42 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2644,8 +2644,7 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) { { // Abridged FTW - auto AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); - _StoreMem(GPRClass, 1, AbridgedFTW, MemBase, _Constant(4), 2, MEM_OFFSET_SXTX, 1); + _StoreMem(GPRClass, 1, LoadContext(AbridgedFTWIndex), MemBase, _Constant(4), 2, MEM_OFFSET_SXTX, 1); } // BYTE | 0 1 | 2 3 | 4 | 5 | 6 7 | 8 9 | a b | c d | e f | @@ -2693,7 +2692,7 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) { // If OSFXSR bit in CR4 is not set than FXSAVE /may/ not save the XMM registers // This is implementation dependent for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) { - Ref MMReg = _LoadContext(16, FPRClass, offsetof(FEXCore::Core::CPUState, mm[i])); + Ref MMReg = LoadContext(MM0Index + i); _StoreMem(FPRClass, 16, MMReg, MemBase, _Constant(i * 16 + 32), 16, MEM_OFFSET_SXTX, 1); } @@ -2820,13 +2819,12 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) { { // Abridged FTW - auto NewAbridgedFTW = _LoadMem(GPRClass, 1, MemBase, _Constant(4), 2, MEM_OFFSET_SXTX, 1); - _StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, _LoadMem(GPRClass, 1, MemBase, _Constant(4), 2, MEM_OFFSET_SXTX, 1)); } for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) { auto MMReg = _LoadMem(FPRClass, 16, MemBase, _Constant(i * 16 + 32), 16, MEM_OFFSET_SXTX, 1); - _StoreContext(16, FPRClass, MMReg, offsetof(FEXCore::Core::CPUState, mm[i])); + StoreContext(MM0Index + i, MMReg); } } @@ -2865,7 +2863,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) { // all of the ST0-7/MM0-7 registers to zero. Ref ZeroVector = LoadZeroVector(Core::CPUState::MM_REG_SIZE); for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) { - _StoreContext(16, FPRClass, ZeroVector, offsetof(FEXCore::Core::CPUState, mm[i])); + StoreContext(MM0Index + i, ZeroVector); } } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index 3699c0925..3e1db6356 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -31,14 +31,14 @@ Ref OpDispatchBuilder::GetX87Top() { void OpDispatchBuilder::SetX87ValidTag(Ref Value, bool Valid) { // if we are popping then we must first mark this location as empty - Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref AbridgedFTW = LoadContext(AbridgedFTWIndex); Ref RegMask = _Lshl(OpSize::i32Bit, _Constant(1), Value); Ref NewAbridgedFTW = Valid ? _Or(OpSize::i32Bit, AbridgedFTW, RegMask) : _Andn(OpSize::i32Bit, AbridgedFTW, RegMask); - _StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, NewAbridgedFTW); } Ref OpDispatchBuilder::GetX87ValidTag(Ref Value) { - Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref AbridgedFTW = LoadContext(AbridgedFTWIndex); return _And(OpSize::i32Bit, _Lshr(OpSize::i32Bit, AbridgedFTW, Value), _Constant(1)); } @@ -51,8 +51,7 @@ Ref OpDispatchBuilder::GetX87Tag(Ref Value, Ref AbridgedFTW) { } Ref OpDispatchBuilder::GetX87Tag(Ref Value) { - Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); - return GetX87Tag(Value, AbridgedFTW); + return GetX87Tag(Value, LoadContext(AbridgedFTWIndex)); } void OpDispatchBuilder::SetX87FTW(Ref FTW) { @@ -70,11 +69,11 @@ void OpDispatchBuilder::SetX87FTW(Ref FTW) { } } - _StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, NewAbridgedFTW); } Ref OpDispatchBuilder::GetX87FTW() { - Ref AbridgedFTW = _LoadContext(1, GPRClass, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + Ref AbridgedFTW = LoadContext(AbridgedFTWIndex); Ref FTW = _Constant(0); for (int i = 0; i < 8; i++) { @@ -154,7 +153,6 @@ void OpDispatchBuilder::FLD(OpcodeArgs) { SetX87Top(top); // Write to ST[TOP] _StoreContextIndexed(converted, top, 16, MMBaseOffset(), 16, FPRClass); - //_StoreContext(converted, 16, offsetof(FEXCore::Core::CPUState, mm[7][0])); } template void OpDispatchBuilder::FLD<32>(OpcodeArgs); @@ -644,7 +642,7 @@ void OpDispatchBuilder::FNINIT(OpcodeArgs) { SetRFLAG(Zero); // Tags all get marked as invalid - _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, Zero); } template @@ -1215,7 +1213,7 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) { void OpDispatchBuilder::X87EMMS(OpcodeArgs) { // Tags all get set to 0b11 - _StoreContext(1, GPRClass, _Constant(0), offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, _Constant(0)); } void OpDispatchBuilder::X87FFREE(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp index 96d2f3577..a746e5dc0 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp @@ -60,7 +60,7 @@ void OpDispatchBuilder::FNINITF64(OpcodeArgs) { SetRFLAG(Zero); // Tags all get marked as invalid - _StoreContext(1, GPRClass, Zero, offsetof(FEXCore::Core::CPUState, AbridgedFTW)); + StoreContext(AbridgedFTWIndex, Zero); } void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/IR/PassManager.cpp b/FEXCore/Source/Interface/IR/PassManager.cpp index 476460a57..e93e04cd8 100644 --- a/FEXCore/Source/Interface/IR/PassManager.cpp +++ b/FEXCore/Source/Interface/IR/PassManager.cpp @@ -70,7 +70,6 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx) { FEX_CONFIG_OPT(DisablePasses, O0); if (!DisablePasses()) { - InsertPass(CreateContextLoadStoreElimination(ctx->HostFeatures.SupportsSVE256)); InsertPass(CreateDeadStoreElimination()); InsertPass(CreateConstProp(ctx->HostFeatures.SupportsTSOImm9, &ctx->CPUID)); InsertPass(CreateDeadFlagCalculationEliminination()); diff --git a/FEXCore/Source/Interface/IR/Passes.h b/FEXCore/Source/Interface/IR/Passes.h index 72474ad5e..8c18ff2bd 100644 --- a/FEXCore/Source/Interface/IR/Passes.h +++ b/FEXCore/Source/Interface/IR/Passes.h @@ -17,7 +17,6 @@ class RegisterAllocationPass; class RegisterAllocationData; fextl::unique_ptr CreateConstProp(bool SupportsTSOImm9, const FEXCore::CPUIDEmu* CPUID); -fextl::unique_ptr CreateContextLoadStoreElimination(bool SupportsSVE256); fextl::unique_ptr CreateDeadFlagCalculationEliminination(); fextl::unique_ptr CreateDeadStoreElimination(); fextl::unique_ptr CreateRegisterAllocationPass(); diff --git a/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp b/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp deleted file mode 100644 index 419bf5e2a..000000000 --- a/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp +++ /dev/null @@ -1,770 +0,0 @@ -// SPDX-License-Identifier: MIT -/* -$info$ -tags: ir|opts -desc: Transforms ContextLoad/Store to temporaries, similar to mem2reg -$end_info$ -*/ - -#include "Interface/IR/IR.h" -#include "Interface/IR/IREmitter.h" -#include "Interface/IR/Passes.h" -#include "Interface/IR/PassManager.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -namespace { -struct ContextMemberClassification { - size_t Offset; - uint16_t Size; -}; - -enum class LastAccessType { - NONE = (0b000 << 0), ///< Was never previously accessed - WRITE = (0b001 << 0), ///< Was fully overwritten - READ = (0b010 << 0), ///< Was fully read - INVALID = (0b011 << 0), ///< Accessing this is invalid - MASK = (0b011 << 0), - PARTIAL = (0b100 << 0), - PARTIAL_WRITE = (PARTIAL | WRITE), ///< Was partially written - PARTIAL_READ = (PARTIAL | READ), ///< Was partially read -}; -FEX_DEF_NUM_OPS(LastAccessType); - -static bool IsWriteAccess(LastAccessType Type) { - return (Type & LastAccessType::MASK) == LastAccessType::WRITE; -} - -static bool IsReadAccess(LastAccessType Type) { - return (Type & LastAccessType::MASK) == LastAccessType::READ; -} - -[[maybe_unused]] -static bool IsInvalidAccess(LastAccessType Type) { - return (Type & LastAccessType::MASK) == LastAccessType::INVALID; -} - -[[maybe_unused]] -static bool IsPartialAccess(LastAccessType Type) { - return (Type & LastAccessType::PARTIAL) == LastAccessType::PARTIAL; -} - -[[maybe_unused]] -static bool IsFullAccess(LastAccessType Type) { - return (Type & LastAccessType::PARTIAL) == LastAccessType::NONE; -} - -struct ContextMemberInfo { - ContextMemberClassification Class; - LastAccessType Accessed; - FEXCore::IR::RegisterClassType AccessRegClass; - uint32_t AccessOffset; - uint8_t AccessSize; - ///< The last value that was loaded or stored. - FEXCore::IR::Ref ValueNode; - ///< With a store access, the store node that is doing the operation. - FEXCore::IR::Ref StoreNode; -}; - -struct ContextInfo { - fextl::vector Lookup; - fextl::vector ClassificationInfo; -}; - -static void ClassifyContextStruct(ContextInfo* ContextClassificationInfo, bool SupportsSVE256) { - auto ContextClassification = &ContextClassificationInfo->ClassificationInfo; - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader), - sizeof(FEXCore::Core::CPUState::InlineJITBlockHeader), - }, - LastAccessType::INVALID, - FEXCore::IR::InvalidClass, - }); - - // DeferredSignalRefCount - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount), - sizeof(FEXCore::Core::CPUState::DeferredSignalRefCount), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, avx_high[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i, - FEXCore::Core::CPUState::XMM_SSE_REG_SIZE, - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, rip), - sizeof(FEXCore::Core::CPUState::rip), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GPRS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, gregs[0]) + sizeof(FEXCore::Core::CPUState::gregs[0]) * i, - FEXCore::Core::CPUState::GPR_REG_SIZE, - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, _pad), - sizeof(FEXCore::Core::CPUState::_pad), - }, - LastAccessType::INVALID, - FEXCore::IR::InvalidClass, - }); - - if (SupportsSVE256) { - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, xmm.avx.data[0][0]) + FEXCore::Core::CPUState::XMM_AVX_REG_SIZE * i, - FEXCore::Core::CPUState::XMM_AVX_REG_SIZE, - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - } else { - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, xmm.sse.data[0][0]) + FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * i, - FEXCore::Core::CPUState::XMM_SSE_REG_SIZE, - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, xmm.sse.pad[0][0]), - static_cast(FEXCore::Core::CPUState::XMM_SSE_REG_SIZE * FEXCore::Core::CPUState::NUM_XMMS), - }, - LastAccessType::INVALID, - FEXCore::IR::InvalidClass, - }); - } - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, es_idx), - sizeof(FEXCore::Core::CPUState::es_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, cs_idx), - sizeof(FEXCore::Core::CPUState::cs_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, ss_idx), - sizeof(FEXCore::Core::CPUState::ss_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, ds_idx), - sizeof(FEXCore::Core::CPUState::ds_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, gs_idx), - sizeof(FEXCore::Core::CPUState::gs_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, fs_idx), - sizeof(FEXCore::Core::CPUState::fs_idx), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, _pad2), - sizeof(FEXCore::Core::CPUState::_pad2), - }, - LastAccessType::INVALID, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, es_cached), - sizeof(FEXCore::Core::CPUState::es_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, cs_cached), - sizeof(FEXCore::Core::CPUState::cs_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, ss_cached), - sizeof(FEXCore::Core::CPUState::ss_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, ds_cached), - sizeof(FEXCore::Core::CPUState::ds_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, gs_cached), - sizeof(FEXCore::Core::CPUState::gs_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, fs_cached), - sizeof(FEXCore::Core::CPUState::fs_cached), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, flags[0]) + sizeof(FEXCore::Core::CPUState::flags[0]) * i, - FEXCore::Core::CPUState::FLAG_SIZE, - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, pf_raw), - sizeof(FEXCore::Core::CPUState::pf_raw), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, af_raw), - sizeof(FEXCore::Core::CPUState::af_raw), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification {offsetof(FEXCore::Core::CPUState, mm[0][0]) + sizeof(FEXCore::Core::CPUState::mm[0]) * i, - FEXCore::Core::CPUState::MM_REG_SIZE}, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - // GDTs - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GDTS; ++i) { - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, gdt[0]) + sizeof(FEXCore::Core::CPUState::gdt[0]) * i, - sizeof(FEXCore::Core::CPUState::gdt[0]), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - } - - // FCW - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, FCW), - sizeof(FEXCore::Core::CPUState::FCW), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - // AbridgedFTW - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, AbridgedFTW), - sizeof(FEXCore::Core::CPUState::AbridgedFTW), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - // _pad3 - ContextClassification->emplace_back(ContextMemberInfo { - ContextMemberClassification { - offsetof(FEXCore::Core::CPUState, _pad3), - sizeof(FEXCore::Core::CPUState::_pad3), - }, - LastAccessType::NONE, - FEXCore::IR::InvalidClass, - }); - - [[maybe_unused]] size_t ClassifiedStructSize {}; - ContextClassificationInfo->Lookup.reserve(sizeof(FEXCore::Core::CPUState)); - for (auto& it : *ContextClassification) { - LOGMAN_THROW_A_FMT(it.Class.Offset == ContextClassificationInfo->Lookup.size(), "Offset mismatch (offset={})", it.Class.Offset); - for (int i = 0; i < it.Class.Size; i++) { - ContextClassificationInfo->Lookup.push_back(&it); - } - ClassifiedStructSize += it.Class.Size; - } - - LOGMAN_THROW_AA_FMT(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState), - "Classified CPUStruct size doesn't match real CPUState struct size! {} (classified) != {} (real)", - ClassifiedStructSize, sizeof(FEXCore::Core::CPUState)); - - LOGMAN_THROW_A_FMT(ContextClassificationInfo->Lookup.size() == sizeof(FEXCore::Core::CPUState), - "Classified lookup size doesn't match real CPUState struct size! {} (classified) != {} (real)", - ContextClassificationInfo->Lookup.size(), sizeof(FEXCore::Core::CPUState)); -} - -static void ResetClassificationAccesses(ContextInfo* ContextClassificationInfo, bool SupportsSVE256) { - auto ContextClassification = &ContextClassificationInfo->ClassificationInfo; - - auto SetAccess = [&](size_t Offset, LastAccessType Access) { - ContextClassification->at(Offset).Accessed = Access; - ContextClassification->at(Offset).AccessRegClass = FEXCore::IR::InvalidClass; - ContextClassification->at(Offset).AccessOffset = 0; - ContextClassification->at(Offset).StoreNode = nullptr; - }; - - size_t Offset = 0; - - ///< InlineJITBlockHeader - SetAccess(Offset++, LastAccessType::INVALID); - - // DeferredSignalRefCount - SetAccess(Offset++, LastAccessType::INVALID); - - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) { - ///< avx_high - SetAccess(Offset++, LastAccessType::NONE); - } - - // rip - SetAccess(Offset++, LastAccessType::NONE); - - ///< gregs - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GPRS; ++i) { - SetAccess(Offset++, LastAccessType::NONE); - } - - // pad - SetAccess(Offset++, LastAccessType::NONE); - - // xmm - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_XMMS; ++i) { - SetAccess(Offset++, LastAccessType::NONE); - } - - // xmm_pad - if (!SupportsSVE256) { - SetAccess(Offset++, LastAccessType::NONE); - } - - // Segment indexes - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - - // Pad2 - SetAccess(Offset++, LastAccessType::INVALID); - - // Segments - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - SetAccess(Offset++, LastAccessType::NONE); - - ///< flags - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_FLAGS; ++i) { - SetAccess(Offset++, LastAccessType::NONE); - } - - ///< pf_raw - SetAccess(Offset++, LastAccessType::NONE); - - ///< af_raw - SetAccess(Offset++, LastAccessType::NONE); - - ///< mm - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_MMS; ++i) { - SetAccess(Offset++, LastAccessType::NONE); - } - - ///< gdt - for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_GDTS; ++i) { - SetAccess(Offset++, LastAccessType::NONE); - } - - ///< FCW - SetAccess(Offset++, LastAccessType::NONE); - - ///< AbridgedFTW - SetAccess(Offset++, LastAccessType::NONE); - - // pad3 - SetAccess(Offset++, LastAccessType::INVALID); -} - -struct BlockInfo { - fextl::vector Predecessors; - fextl::vector Successors; - ContextInfo IncomingClassifiedStruct; - ContextInfo OutgoingClassifiedStruct; -}; - -class RCLSE final : public FEXCore::IR::Pass { -public: - explicit RCLSE(bool SupportsSVE256) - : SupportsSVE256 {SupportsSVE256} { - ClassifyContextStruct(&ClassifiedStruct, SupportsSVE256); - } - void Run(FEXCore::IR::IREmitter* IREmit) override; -private: - ContextInfo ClassifiedStruct; - fextl::unordered_map OffsetToBlockMap; - - bool SupportsSVE256; - - ContextMemberInfo* FindMemberInfo(ContextInfo* ClassifiedInfo, uint32_t Offset, uint8_t Size); - ContextMemberInfo* RecordAccess(ContextMemberInfo* Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, - LastAccessType AccessType, FEXCore::IR::Ref Node, FEXCore::IR::Ref StoreNode = nullptr); - ContextMemberInfo* RecordAccess(ContextInfo* ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, - LastAccessType AccessType, FEXCore::IR::Ref Node, FEXCore::IR::Ref StoreNode = nullptr); - - void HandleLoadFlag(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::Ref CodeNode, unsigned Flag); - - // Classify context loads and stores. - void ClassifyContextLoad(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, - uint8_t Size, FEXCore::IR::Ref CodeNode, FEXCore::IR::NodeIterator BlockEnd); - void ClassifyContextStore(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, - uint8_t Size, FEXCore::IR::Ref CodeNode, FEXCore::IR::Ref ValueNode); - - // Block local Passes - void RedundantStoreLoadElimination(FEXCore::IR::IREmitter* IREmit); - - unsigned OffsetForReg(FEXCore::IR::RegisterClassType Class, unsigned Reg, unsigned Size) { - if (Class == FEXCore::IR::FPRClass) { - return Size == 32 ? offsetof(FEXCore::Core::CPUState, xmm.avx.data[Reg][0]) : offsetof(FEXCore::Core::CPUState, xmm.sse.data[Reg][0]); - } else if (Reg == FEXCore::Core::CPUState::PF_AS_GREG) { - return offsetof(FEXCore::Core::CPUState, pf_raw); - } else if (Reg == FEXCore::Core::CPUState::AF_AS_GREG) { - return offsetof(FEXCore::Core::CPUState, af_raw); - } else { - return offsetof(FEXCore::Core::CPUState, gregs[Reg]); - } - } -}; - -ContextMemberInfo* RCLSE::FindMemberInfo(ContextInfo* ContextClassificationInfo, uint32_t Offset, uint8_t Size) { - return ContextClassificationInfo->Lookup.at(Offset); -} - -ContextMemberInfo* RCLSE::RecordAccess(ContextMemberInfo* Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, - LastAccessType AccessType, FEXCore::IR::Ref ValueNode, FEXCore::IR::Ref StoreNode) { - LOGMAN_THROW_AA_FMT((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size"); - LOGMAN_THROW_AA_FMT(Info->Accessed != LastAccessType::INVALID, "Tried to access invalid member"); - - // If we aren't fully overwriting the member then it is a partial write that we need to track - if (Size < Info->Class.Size) { - AccessType = AccessType == LastAccessType::WRITE ? LastAccessType::PARTIAL_WRITE : LastAccessType::PARTIAL_READ; - } - if (Size > Info->Class.Size) { - LOGMAN_MSG_A_FMT("Can't handle this"); - } - - Info->Accessed = AccessType; - Info->AccessRegClass = RegClass; - Info->AccessOffset = Offset; - Info->AccessSize = Size; - Info->ValueNode = ValueNode; - if (StoreNode != nullptr) { - Info->StoreNode = StoreNode; - } - return Info; -} - -ContextMemberInfo* RCLSE::RecordAccess(ContextInfo* ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, - LastAccessType AccessType, FEXCore::IR::Ref ValueNode, FEXCore::IR::Ref StoreNode) { - ContextMemberInfo* Info = FindMemberInfo(ClassifiedInfo, Offset, Size); - return RecordAccess(Info, RegClass, Offset, Size, AccessType, ValueNode, StoreNode); -} - -void RCLSE::ClassifyContextLoad(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::RegisterClassType Class, - uint32_t Offset, uint8_t Size, FEXCore::IR::Ref CodeNode, FEXCore::IR::NodeIterator BlockEnd) { - auto Info = FindMemberInfo(LocalInfo, Offset, Size); - ContextMemberInfo PreviousMemberInfoCopy = *Info; - RecordAccess(Info, Class, Offset, Size, LastAccessType::READ, CodeNode); - - if (PreviousMemberInfoCopy.AccessRegClass == Info->AccessRegClass && PreviousMemberInfoCopy.AccessOffset == Info->AccessOffset && - PreviousMemberInfoCopy.AccessSize == Size) { - // This optimizes two cases: - // - Previous access was a load, and we have a redundant load of the same value. - // - Previous access was a store, and we are redundantly loading immediately after the store. Eliminating the store. - IREmit->ReplaceAllUsesWithRange(CodeNode, PreviousMemberInfoCopy.ValueNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd); - RecordAccess(Info, Class, Offset, Size, LastAccessType::READ, PreviousMemberInfoCopy.ValueNode); - } - // TODO: Optimize the case of partial loads. -} - -void RCLSE::ClassifyContextStore(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::RegisterClassType Class, - uint32_t Offset, uint8_t Size, FEXCore::IR::Ref CodeNode, FEXCore::IR::Ref ValueNode) { - auto Info = FindMemberInfo(LocalInfo, Offset, Size); - ContextMemberInfo PreviousMemberInfoCopy = *Info; - RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode, CodeNode); - - if (PreviousMemberInfoCopy.AccessRegClass == Info->AccessRegClass && PreviousMemberInfoCopy.AccessOffset == Info->AccessOffset && - PreviousMemberInfoCopy.AccessSize == Size && PreviousMemberInfoCopy.Accessed == LastAccessType::WRITE) { - // This optimizes redundant stores with no intervening load - // TODO: this is causing RA to fall over in some titles, disabling for now. - // Revisit when the new RA lands. -#if 0 - IREmit->Remove(PreviousMemberInfoCopy.StoreNode); -#endif - } - - // TODO: Optimize the case of partial stores. -} - -void RCLSE::HandleLoadFlag(FEXCore::IR::IREmitter* IREmit, ContextInfo* LocalInfo, FEXCore::IR::Ref CodeNode, unsigned Flag) { - const auto FlagOffset = offsetof(FEXCore::Core::CPUState, flags[Flag]); - auto Info = FindMemberInfo(LocalInfo, FlagOffset, 1); - LastAccessType LastAccess = Info->Accessed; - auto LastValueNode = Info->ValueNode; - - if (IsWriteAccess(LastAccess)) { // 1 byte so always a full write - // If the last store matches this load value then we can replace the loaded value with the previous valid one - IREmit->SetWriteCursor(CodeNode); - IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode); - RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode); - } else if (IsReadAccess(LastAccess)) { - IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode); - RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode); - } -} - -/** - * @brief This pass removes redundant pairs of storecontext and loadcontext ops - * - * eg. - * %26 i128 = LoadMem %25 i64, 0x10 - * (%%27) StoreContext %26 i128, 0x10, 0xb0 - * %28 i128 = LoadContext 0x10, 0x90 - * %29 i128 = LoadContext 0x10, 0xb0 - * Converts to - * %26 i128 = LoadMem %25 i64, 0x10 - * (%%27) StoreContext %26 i128, 0x10, 0xb0 - * %28 i128 = LoadContext 0x10, 0x90 - * - * eg. - * %6 i128 = LoadContext 0x10, 0x90 - * %7 i128 = LoadContext 0x10, 0x90 - * %8 i128 = VXor %7 i128, %6 i128 - * Converts to - * %6 i128 = LoadContext 0x10, 0x90 - * %7 i128 = VXor %6 i128, %6 i128 - * - * eg. - * (%%189) StoreContext %188 i128, 0x10, 0xa0 - * %190 i128 = LoadContext 0x10, 0x90 - * %192 i128 = VAdd %188 i128, %190 i128, 0x10, 0x4 - * (%%193) StoreContext %192 i128, 0x10, 0xa0 - * Converts to - * %173 i128 = LoadContext 0x10, 0x90 - * %175 i128 = VAdd %172 i128, %173 i128, 0x10, 0x4 - * (%%176) StoreContext %175 i128, 0x10, 0xa0 - - */ -void RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter* IREmit) { - using namespace FEXCore; - using namespace FEXCore::IR; - - auto CurrentIR = IREmit->ViewIR(); - auto OriginalWriteCursor = IREmit->GetWriteCursor(); - - // XXX: Walk the list and calculate the control flow - - ContextInfo& LocalInfo = ClassifiedStruct; - - for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) { - auto BlockOp = BlockHeader->CW(); - auto BlockEnd = IREmit->GetIterator(BlockOp->Last); - - ResetClassificationAccesses(&LocalInfo, SupportsSVE256); - - for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { - if (IROp->Op == OP_STORECONTEXT) { - auto Op = IROp->CW(); - ClassifyContextStore(IREmit, &LocalInfo, Op->Class, Op->Offset, IROp->Size, CodeNode, CurrentIR.GetNode(Op->Value)); - } else if (IROp->Op == OP_STOREREGISTER) { - auto Op = IROp->CW(); - auto Offset = OffsetForReg(Op->Class, Op->Reg, IROp->Size); - - ClassifyContextStore(IREmit, &LocalInfo, Op->Class, Offset, IROp->Size, CodeNode, CurrentIR.GetNode(Op->Value)); - } else if (IROp->Op == OP_LOADREGISTER) { - auto Op = IROp->CW(); - auto Offset = OffsetForReg(Op->Class, Op->Reg, IROp->Size); - ClassifyContextLoad(IREmit, &LocalInfo, Op->Class, Offset, IROp->Size, CodeNode, BlockEnd); - } else if (IROp->Op == OP_LOADCONTEXT) { - auto Op = IROp->CW(); - ClassifyContextLoad(IREmit, &LocalInfo, Op->Class, Op->Offset, IROp->Size, CodeNode, BlockEnd); - } else if (IROp->Op == OP_STOREFLAG) { - const auto Op = IROp->CW(); - const auto FlagOffset = offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag; - auto Info = FindMemberInfo(&LocalInfo, FlagOffset, 1); - auto LastStoreNode = Info->StoreNode; - RecordAccess(&LocalInfo, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::WRITE, CurrentIR.GetNode(Op->Header.Args[0]), CodeNode); - - // Flags don't alias, so we can take the simple route here. Kill any flags that have been overwritten - if (LastStoreNode != nullptr) { - IREmit->Remove(LastStoreNode); - } - } else if (IROp->Op == OP_INVALIDATEFLAGS) { - auto Op = IROp->CW(); - - // Loop through non-reserved flag stores and eliminate unused ones. - for (size_t F = 0; F < Core::CPUState::NUM_EFLAG_BITS; F++) { - if (!(Op->Flags & (1ULL << F))) { - continue; - } - - const auto FlagOffset = offsetof(FEXCore::Core::CPUState, flags[0]) + F; - auto Info = FindMemberInfo(&LocalInfo, FlagOffset, 1); - auto LastStoreNode = Info->StoreNode; - - // Flags don't alias, so we can take the simple route here. Kill any flags that have been invalidated without a read. - if (LastStoreNode != nullptr) { - IREmit->SetWriteCursor(CodeNode); - RecordAccess(&LocalInfo, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::WRITE, IREmit->_Constant(0), CodeNode); - - IREmit->Remove(LastStoreNode); - } - } - } else if (IROp->Op == OP_LOADFLAG) { - const auto Op = IROp->CW(); - - HandleLoadFlag(IREmit, &LocalInfo, CodeNode, Op->Flag); - } else if (IROp->Op == OP_LOADDF) { - HandleLoadFlag(IREmit, &LocalInfo, CodeNode, X86State::RFLAG_DF_RAW_LOC); - } else if (IROp->Op == OP_SYSCALL || IROp->Op == OP_INLINESYSCALL) { - FEXCore::IR::SyscallFlags Flags {}; - if (IROp->Op == OP_SYSCALL) { - auto Op = IROp->C(); - Flags = Op->Flags; - } else { - auto Op = IROp->C(); - Flags = Op->Flags; - } - - if ((Flags & FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH) != FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH) { - // We can't track through these - ResetClassificationAccesses(&LocalInfo, SupportsSVE256); - } - } else if (IROp->Op == OP_STORECONTEXTINDEXED || IROp->Op == OP_LOADCONTEXTINDEXED || IROp->Op == OP_BREAK) { - // We can't track through these - ResetClassificationAccesses(&LocalInfo, SupportsSVE256); - } - } - } - - IREmit->SetWriteCursor(OriginalWriteCursor); -} - -void RCLSE::Run(FEXCore::IR::IREmitter* IREmit) { - FEXCORE_PROFILE_SCOPED("PassManager::RCLSE"); - RedundantStoreLoadElimination(IREmit); -} - -} // namespace - -namespace FEXCore::IR { - -fextl::unique_ptr CreateContextLoadStoreElimination(bool SupportsSVE256) { - return fextl::make_unique(SupportsSVE256); -} - -} // namespace FEXCore::IR diff --git a/docs/SourceOutline.md b/docs/SourceOutline.md index 9ecae62ea..72bc6816a 100644 --- a/docs/SourceOutline.md +++ b/docs/SourceOutline.md @@ -109,7 +109,6 @@ IR to IR Optimization - [PassManager.cpp](../FEXCore/Source/Interface/IR/PassManager.cpp): Defines which passes are run, and runs them - [PassManager.h](../FEXCore/Source/Interface/IR/PassManager.h) - [ConstProp.cpp](../FEXCore/Source/Interface/IR/Passes/ConstProp.cpp): ConstProp, ZExt elim, const pooling, fcmp reduction, const inlining -- [DeadContextStoreElimination.cpp](../FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp): Transforms ContextLoad/Store to temporaries, similar to mem2reg - [DeadStoreElimination.cpp](../FEXCore/Source/Interface/IR/Passes/DeadStoreElimination.cpp): Cross block store-after-store elimination - [IRValidation.cpp](../FEXCore/Source/Interface/IR/Passes/IRValidation.cpp): Sanity checking pass - [RedundantFlagCalculationElimination.cpp](../FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp): This is not used right now, possibly broken diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index 8b4034290..8c0f0fef9 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -1045,10 +1045,11 @@ "mov rax, gs:0x100", "mov rbx, gs:0x14" ], - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "ExpectedArm64ASM": [ "ldr x20, [x28, #960]", "ldr x4, [x20, #256]", + "ldr x20, [x28, #960]", "ldur x7, [x20, #20]" ] } diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index db3262752..c6f2a1f51 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -323,10 +323,11 @@ "mov eax, gs:0x100", "mov ebx, gs:0x14" ], - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "ExpectedArm64ASM": [ "ldr w20, [x28, #960]", "ldr w4, [x20, #256]", + "ldr w20, [x28, #960]", "ldr w7, [x20, #20]" ] } diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 8943ec5e8..69f3bd7d8 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -69,11 +69,11 @@ ], "ExpectedArm64ASM": [ "mov w20, #0x1", - "strb w20, [x28, #986]", - "ldrb w20, [x10]", - "strb w20, [x11]", + "ldrb w21, [x10]", + "strb w21, [x11]", "add x10, x10, #0x1 (1)", - "add x11, x11, #0x1 (1)" + "add x11, x11, #0x1 (1)", + "strb w20, [x28, #986]" ] }, "positive movsw": { @@ -88,11 +88,11 @@ ], "ExpectedArm64ASM": [ "mov w20, #0x1", - "strb w20, [x28, #986]", - "ldrh w20, [x10]", - "strh w20, [x11]", + "ldrh w21, [x10]", + "strh w21, [x11]", "add x10, x10, #0x2 (2)", - "add x11, x11, #0x2 (2)" + "add x11, x11, #0x2 (2)", + "strb w20, [x28, #986]" ] }, "positive movsd": { @@ -107,11 +107,11 @@ ], "ExpectedArm64ASM": [ "mov w20, #0x1", - "strb w20, [x28, #986]", - "ldr w20, [x10]", - "str w20, [x11]", + "ldr w21, [x10]", + "str w21, [x11]", "add x10, x10, #0x4 (4)", - "add x11, x11, #0x4 (4)" + "add x11, x11, #0x4 (4)", + "strb w20, [x28, #986]" ] }, "positive movsq": { @@ -126,11 +126,11 @@ ], "ExpectedArm64ASM": [ "mov w20, #0x1", - "strb w20, [x28, #986]", - "ldr x20, [x10]", - "str x20, [x11]", + "ldr x21, [x10]", + "str x21, [x11]", "add x10, x10, #0x8 (8)", - "add x11, x11, #0x8 (8)" + "add x11, x11, #0x8 (8)", + "strb w20, [x28, #986]" ] }, "negative movsb": { @@ -145,11 +145,11 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "ldrb w20, [x10]", - "strb w20, [x11]", + "ldrb w21, [x10]", + "strb w21, [x11]", "sub x10, x10, #0x1 (1)", - "sub x11, x11, #0x1 (1)" + "sub x11, x11, #0x1 (1)", + "strb w20, [x28, #986]" ] }, "negative movsw": { @@ -164,11 +164,11 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "ldrh w20, [x10]", - "strh w20, [x11]", + "ldrh w21, [x10]", + "strh w21, [x11]", "sub x10, x10, #0x2 (2)", - "sub x11, x11, #0x2 (2)" + "sub x11, x11, #0x2 (2)", + "strb w20, [x28, #986]" ] }, "negative movsd": { @@ -183,11 +183,11 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "ldr w20, [x10]", - "str w20, [x11]", + "ldr w21, [x10]", + "str w21, [x11]", "sub x10, x10, #0x4 (4)", - "sub x11, x11, #0x4 (4)" + "sub x11, x11, #0x4 (4)", + "strb w20, [x28, #986]" ] }, "negative movsq": { @@ -202,11 +202,11 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "ldr x20, [x10]", - "str x20, [x11]", + "ldr x21, [x10]", + "str x21, [x11]", "sub x10, x10, #0x8 (8)", - "sub x11, x11, #0x8 (8)" + "sub x11, x11, #0x8 (8)", + "strb w20, [x28, #986]" ] }, "positive rep movsb": { @@ -222,7 +222,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -263,6 +262,7 @@ "add x23, x1, x2", "mov x10, x23", "mov x11, x22", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -279,7 +279,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -320,6 +319,7 @@ "add x23, x1, x2, lsl #1", "mov x10, x23", "mov x11, x22", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -336,7 +336,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -377,6 +376,7 @@ "add x23, x1, x2, lsl #2", "mov x10, x23", "mov x11, x22", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -393,7 +393,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -434,6 +433,7 @@ "add x23, x1, x2, lsl #3", "mov x10, x23", "mov x11, x22", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -449,7 +449,6 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -490,11 +489,12 @@ "mov x0, x11", "mov x1, x10", "mov x2, x5", - "sub x20, x0, x2", - "sub x21, x1, x2", - "mov x10, x21", - "mov x11, x20", - "mov w5, #0x0" + "sub x22, x0, x2", + "sub x23, x1, x2", + "mov x10, x23", + "mov x11, x22", + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep movsw": { @@ -509,7 +509,6 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -550,11 +549,12 @@ "mov x0, x11", "mov x1, x10", "mov x2, x5", - "sub x20, x0, x2, lsl #1", - "sub x21, x1, x2, lsl #1", - "mov x10, x21", - "mov x11, x20", - "mov w5, #0x0" + "sub x22, x0, x2, lsl #1", + "sub x23, x1, x2, lsl #1", + "mov x10, x23", + "mov x11, x22", + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep movsd": { @@ -569,7 +569,6 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -610,11 +609,12 @@ "mov x0, x11", "mov x1, x10", "mov x2, x5", - "sub x20, x0, x2, lsl #2", - "sub x21, x1, x2, lsl #2", - "mov x10, x21", - "mov x11, x20", - "mov w5, #0x0" + "sub x22, x0, x2, lsl #2", + "sub x23, x1, x2, lsl #2", + "mov x10, x23", + "mov x11, x22", + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep movsq": { @@ -629,7 +629,6 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", "mov x0, x5", "mov x1, x11", "mov x2, x10", @@ -670,11 +669,12 @@ "mov x0, x11", "mov x1, x10", "mov x2, x5", - "sub x20, x0, x2, lsl #3", - "sub x21, x1, x2, lsl #3", - "mov x10, x21", - "mov x11, x20", - "mov w5, #0x0" + "sub x22, x0, x2, lsl #3", + "sub x23, x1, x2, lsl #3", + "mov x10, x23", + "mov x11, x22", + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "positive rep stosb": { @@ -690,14 +690,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", - "uxtb w21, w4", + "uxtb w22, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x58", "sub x0, x0, #0x20 (32)", "tbnz x0, #63, #+0x3c", - "dup v1.16b, w21", + "dup v1.16b, w22", "sub x0, x0, #0x20 (32)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #32", @@ -713,10 +712,11 @@ "tbz x0, #63, #-0x8", "add x0, x0, #0x20 (32)", "cbz x0, #+0x10", - "strb w21, [x1], #1", + "strb w22, [x1], #1", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "add x11, x11, x5", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -733,14 +733,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", - "uxth w21, w4", + "uxth w22, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x58", "sub x0, x0, #0x10 (16)", "tbnz x0, #63, #+0x3c", - "dup v1.8h, w21", + "dup v1.8h, w22", "sub x0, x0, #0x10 (16)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #32", @@ -756,10 +755,11 @@ "tbz x0, #63, #-0x8", "add x0, x0, #0x10 (16)", "cbz x0, #+0x10", - "strh w21, [x1], #2", + "strh w22, [x1], #2", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "add x11, x11, x5, lsl #1", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -776,14 +776,13 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", - "mov w21, w4", + "mov w22, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x58", "sub x0, x0, #0x8 (8)", "tbnz x0, #63, #+0x3c", - "dup v1.4s, w21", + "dup v1.4s, w22", "sub x0, x0, #0x8 (8)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #32", @@ -799,10 +798,11 @@ "tbz x0, #63, #-0x8", "add x0, x0, #0x8 (8)", "cbz x0, #+0x10", - "str w21, [x1], #4", + "str w22, [x1], #4", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "add x11, x11, x5, lsl #2", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -819,7 +819,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x1", - "strb w21, [x28, #986]", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x58", @@ -845,6 +844,7 @@ "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "add x11, x11, x5, lsl #3", + "strb w21, [x28, #986]", "mov x5, x20" ] }, @@ -860,15 +860,14 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "uxtb w20, w4", + "uxtb w21, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x60", "sub x1, x1, #0x1f (31)", "sub x0, x0, #0x20 (32)", "tbnz x0, #63, #+0x3c", - "dup v1.16b, w20", + "dup v1.16b, w21", "sub x0, x0, #0x20 (32)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #-32", @@ -885,11 +884,12 @@ "add x0, x0, #0x20 (32)", "cbz x0, #+0x14", "add x1, x1, #0x1f (31)", - "strb w20, [x1], #-1", + "strb w21, [x1], #-1", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "sub x11, x11, x5", - "mov w5, #0x0" + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep stosw": { @@ -904,15 +904,14 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "uxth w20, w4", + "uxth w21, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x60", "sub x1, x1, #0x1e (30)", "sub x0, x0, #0x10 (16)", "tbnz x0, #63, #+0x3c", - "dup v1.8h, w20", + "dup v1.8h, w21", "sub x0, x0, #0x10 (16)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #-32", @@ -929,11 +928,12 @@ "add x0, x0, #0x10 (16)", "cbz x0, #+0x14", "add x1, x1, #0x1e (30)", - "strh w20, [x1], #-2", + "strh w21, [x1], #-2", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "sub x11, x11, x5, lsl #1", - "mov w5, #0x0" + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep stosd": { @@ -948,15 +948,14 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", - "mov w20, w4", + "mov w21, w4", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x60", "sub x1, x1, #0x1c (28)", "sub x0, x0, #0x8 (8)", "tbnz x0, #63, #+0x3c", - "dup v1.4s, w20", + "dup v1.4s, w21", "sub x0, x0, #0x8 (8)", "tbnz x0, #63, #+0x14", "stp q1, q1, [x1], #-32", @@ -973,11 +972,12 @@ "add x0, x0, #0x8 (8)", "cbz x0, #+0x14", "add x1, x1, #0x1c (28)", - "str w20, [x1], #-4", + "str w21, [x1], #-4", "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "sub x11, x11, x5, lsl #2", - "mov w5, #0x0" + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "negative rep stosq": { @@ -992,7 +992,6 @@ ], "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "strb w20, [x28, #986]", "mov x0, x5", "mov x1, x11", "cbz x0, #+0x60", @@ -1020,11 +1019,12 @@ "sub x0, x0, #0x1 (1)", "cbnz x0, #-0x8", "sub x11, x11, x5, lsl #3", - "mov w5, #0x0" + "mov w5, #0x0", + "strb w20, [x28, #986]" ] }, "Sekiro spill block": { - "ExpectedInstructionCount": 148, + "ExpectedInstructionCount": 147, "Comment": [ "This block of code came from the settings screen when it loaded", "It was originally at RIP: 0x14232cca0 and has been deobfuscated" @@ -1173,7 +1173,8 @@ "ldr w11, [x6, #32]", "mov w20, #0x13", "mul w4, w5, w20", - "str w5, [x8, #104]", + "mov w21, w5", + "str w21, [x8, #104]", "mov w21, #0x1000000", "add w4, w4, w21", "lsr w4, w4, #25", @@ -1258,33 +1259,31 @@ "sub w17, w17, w14", "mov w20, w17", "str w20, [x4, #20]", - "ldr w20, [x8, #112]", - "mov x21, x4", - "mov x4, x20", + "ldr w4, [x8, #112]", "lsl w15, w15, #26", - "sub w4, w20, w15", + "sub w4, w4, w15", "lsl w7, w7, #25", "mov w20, w4", - "str w20, [x21, #24]", + "str w20, [x10, #24]", "ldr w4, [x8, #120]", "sub w4, w4, w7", "lsl w11, w11, #26", "mov w20, w4", - "str w20, [x21, #28]", + "str w20, [x10, #28]", "ldr w4, [x8]", "sub w4, w4, w11", "mov w20, w4", - "str w20, [x21, #32]", - "mov x4, x5", - "and w4, w5, #0xfe000000", + "str w20, [x10, #32]", + "mov w4, w5", + "and w4, w4, #0xfe000000", "sub w5, w5, w4", "mov w20, w5", - "str w20, [x21, #36]", + "str w20, [x10, #36]", "mvn w27, w8", "adds x26, x8, #0x18 (24)", "mov x8, x26", - "ldr x29, [x26]", - "add x8, x26, #0x8 (8)", + "ldr x29, [x8]", + "add x8, x8, #0x8 (8)", "ldr x19, [x8]", "add x8, x8, #0x8 (8)", "ldr x17, [x8]", diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 1745e66c3..410a947ea 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -16,7 +16,7 @@ "Comment": [], "Instructions": { "libnss3 sha": { - "ExpectedInstructionCount": 2367, + "ExpectedInstructionCount": 2366, "Comment": [ "This block of code comes from libnss3 which causes panic spilling in FEX's RA.", "This code is hit in steamwebhelper calling in to this function.", @@ -206,7 +206,7 @@ "ldr q22, [x11, #32]", "ldr q21, [x11, #48]", "mov v19.16b, v16.16b", - "ext v19.16b, v18.16b, v16.16b, #8", + "ext v19.16b, v18.16b, v19.16b, #8", "mov v18.d[1], v16.d[1]", "mov w20, #0x1000", "movk w20, #0x1, lsl #16", @@ -230,7 +230,7 @@ "unimplemented (Unimplemented)", "mov w21, v19.s[1]", "mov w22, v19.s[0]", - "mov w23, v18.s[1]", + "mov w23, v20.s[1]", "and w24, w21, w22", "bic w23, w23, w21", "eor w23, w24, w23", @@ -240,11 +240,11 @@ "add w23, w23, w24", "mov w24, v16.s[0]", "add w23, w23, w24", - "mov w24, v18.s[0]", + "mov w24, v20.s[0]", "add w23, w23, w24", "mov w24, v19.s[3]", "mov w25, v19.s[2]", - "mov w30, v18.s[3]", + "mov w30, v20.s[3]", "and w18, w25, w30", "orr w30, w25, w30", "and w30, w24, w30", @@ -254,7 +254,7 @@ "eor w18, w18, w24, ror #13", "eor w18, w18, w24, ror #22", "add w30, w30, w18", - "mov w18, v18.s[2]", + "mov w18, v20.s[2]", "add w23, w23, w18", "and w21, w23, w21", "bic w22, w22, w23", @@ -265,7 +265,7 @@ "add w21, w21, w22", "mov w22, v16.s[1]", "add w21, w21, w22", - "mov w22, v18.s[1]", + "mov w22, v20.s[1]", "add w21, w21, w22", "and w22, w24, w25", "orr w24, w24, w25", @@ -276,9 +276,9 @@ "eor w24, w24, w30, ror #13", "eor w24, w24, w30, ror #22", "add w22, w22, w24", - "mov w24, v18.s[3]", + "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v4.16b, v18.16b", + "mov v4.16b, v20.16b", "mov v4.s[3], w22", "mov v4.s[2], w30", "mov v4.s[1], w21", @@ -289,7 +289,7 @@ "tbl v16.16b, {v16.16b}, v4.16b", "mov w21, v20.s[1]", "mov w22, v20.s[0]", - "mov w23, v19.s[1]", + "mov w23, v17.s[1]", "and w24, w21, w22", "bic w23, w23, w21", "eor w23, w24, w23", @@ -299,11 +299,11 @@ "add w23, w23, w24", "mov w24, v16.s[0]", "add w23, w23, w24", - "mov w24, v19.s[0]", + "mov w24, v17.s[0]", "add w23, w23, w24", "mov w24, v20.s[3]", "mov w25, v20.s[2]", - "mov w30, v19.s[3]", + "mov w30, v17.s[3]", "and w18, w25, w30", "orr w30, w25, w30", "and w30, w24, w30", @@ -313,7 +313,7 @@ "eor w18, w18, w24, ror #13", "eor w18, w18, w24, ror #22", "add w30, w30, w18", - "mov w18, v19.s[2]", + "mov w18, v17.s[2]", "add w23, w23, w18", "and w21, w23, w21", "bic w22, w22, w23", @@ -324,7 +324,7 @@ "add w21, w21, w22", "mov w22, v16.s[1]", "add w21, w21, w22", - "mov w22, v19.s[1]", + "mov w22, v17.s[1]", "add w21, w21, w22", "and w22, w24, w25", "orr w24, w24, w25", @@ -335,16 +335,16 @@ "eor w24, w24, w30, ror #13", "eor w24, w24, w30, ror #22", "add w22, w22, w24", - "mov w24, v19.s[3]", + "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v19.16b", + "mov v5.16b, v17.16b", "mov v5.s[3], w22", "mov v5.s[2], w30", "mov v5.s[1], w21", "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", - "ext v16.16b, v22.16b, v21.16b, #4", + "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v21.s[2]", @@ -499,7 +499,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", - "ext v16.16b, v21.16b, v24.16b, #4", + "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v24.s[2]", @@ -654,7 +654,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", - "ext v16.16b, v24.16b, v23.16b, #4", + "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v23.s[2]", @@ -809,7 +809,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", - "ext v16.16b, v23.16b, v22.16b, #4", + "ext v16.16b, v23.16b, v16.16b, #4", "add v21.4s, v21.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v22.s[2]", @@ -964,7 +964,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", - "ext v16.16b, v22.16b, v21.16b, #4", + "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v21.s[2]", @@ -1119,7 +1119,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", - "ext v16.16b, v21.16b, v24.16b, #4", + "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v24.s[2]", @@ -1274,7 +1274,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", - "ext v16.16b, v24.16b, v23.16b, #4", + "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v23.s[2]", @@ -1429,7 +1429,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", - "ext v16.16b, v23.16b, v22.16b, #4", + "ext v16.16b, v23.16b, v16.16b, #4", "add v21.4s, v21.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v22.s[2]", @@ -1584,7 +1584,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", - "ext v16.16b, v22.16b, v21.16b, #4", + "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v21.s[2]", @@ -1739,7 +1739,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", - "ext v16.16b, v21.16b, v24.16b, #4", + "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v24.s[2]", @@ -1894,7 +1894,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", - "ext v16.16b, v24.16b, v23.16b, #4", + "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", "mov w21, v23.s[2]", @@ -2049,7 +2049,7 @@ "mov v17.16b, v5.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", - "ext v16.16b, v23.16b, v22.16b, #4", + "ext v16.16b, v23.16b, v16.16b, #4", "ldr q5, [x29, x20, sxtx]", "add v23.4s, v23.4s, v5.4s", "add v21.4s, v21.4s, v16.4s", @@ -2219,7 +2219,7 @@ "eor w23, w23, w20, ror #11", "eor w23, w23, w20, ror #25", "add w22, w22, w23", - "mov w23, v23.s[0]", + "mov w23, v16.s[0]", "add w22, w22, w23", "mov w23, v20.s[0]", "add w22, w22, w23", @@ -2244,7 +2244,7 @@ "eor w21, w21, w22, ror #11", "eor w21, w21, w22, ror #25", "add w20, w20, w21", - "mov w21, v23.s[1]", + "mov w21, v16.s[1]", "add w20, w20, w21", "mov w21, v20.s[1]", "add w20, w20, w21", @@ -2333,7 +2333,7 @@ "eor w23, w23, w20, ror #11", "eor w23, w23, w20, ror #25", "add w22, w22, w23", - "mov w23, v22.s[0]", + "mov w23, v16.s[0]", "add w22, w22, w23", "mov w23, v20.s[0]", "add w22, w22, w23", @@ -2358,7 +2358,7 @@ "eor w21, w21, w22, ror #11", "eor w21, w21, w22, ror #25", "add w20, w20, w21", - "mov w21, v22.s[1]", + "mov w21, v16.s[1]", "add w20, w20, w21", "mov w21, v20.s[1]", "add w20, w20, w21", @@ -2447,7 +2447,7 @@ "eor w23, w23, w20, ror #11", "eor w23, w23, w20, ror #25", "add w22, w22, w23", - "mov w23, v21.s[0]", + "mov w23, v16.s[0]", "add w22, w22, w23", "mov w23, v20.s[0]", "add w22, w22, w23", @@ -2472,7 +2472,7 @@ "eor w21, w21, w22, ror #11", "eor w21, w21, w22, ror #25", "add w20, w20, w21", - "mov w21, v21.s[1]", + "mov w21, v16.s[1]", "add w20, w20, w21", "mov w21, v20.s[1]", "add w20, w20, w21", @@ -2555,7 +2555,6 @@ "tbl v20.16b, {v20.16b}, v2.16b", "tbl v17.16b, {v17.16b}, v3.16b", "mov v16.16b, v17.16b", - "mov v16.16b, v17.16b", "mov v16.d[1], v20.d[1]", "ext v20.16b, v17.16b, v20.16b, #8", "str q16, [x11, #256]", diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 653b3e9d4..108529a49 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -95,9 +95,9 @@ "ExpectedArm64ASM": [ "adds x4, x4, x7", "cset w20, hs", - "mov x27, x4", "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -124,9 +124,9 @@ "subs x4, x4, x7", "cfinv", "cset w20, hs", - "mov x27, x4", "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -263,15 +263,16 @@ ] }, "AND use only PF": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "x86Insts": [ "and eax, ebx", "setp cl", "test cl, cl" ], "ExpectedArm64ASM": [ - "and w4, w4, w7", - "eor w20, w4, w4, lsr #4", + "and w26, w4, w7", + "mov x4, x26", + "eor w20, w26, w26, lsr #4", "eor w20, w20, w20, lsr #2", "eon w20, w20, w20, lsr #1", "and x20, x20, #0x1", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 8540fb0eb..b1c4521bc 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -27,7 +27,7 @@ "mov w4, #0x1", "ldaddal x4, x4, [x5]", "mov x6, x4", - "and w6, w4, #0x1f", + "and w6, w6, #0x1f", "add x6, x6, #0x1 (1)", "lsl x6, x6, #6", "eor w27, w6, w5", @@ -81,11 +81,11 @@ "mov w10, w5", "mov x6, x9", "mov x4, x7", - "ldr s18, [x9]", - "add x4, x7, #0x20 (32)", + "ldr s18, [x6]", + "add x4, x4, #0x20 (32)", "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", - "add x6, x9, #0x20 (32)", + "add x6, x6, #0x20 (32)", "ldur s2, [x4, #-32]", "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", @@ -139,9 +139,9 @@ "fadd s0, s18, s2", "mov v18.s[0], v0.s[0]", "stur s18, [x4, #-4]", - "mov x27, x10", "subs w26, w10, #0x1 (1)", "cfinv", + "mov x27, x10", "mov x10, x26" ] }, @@ -168,7 +168,7 @@ ] }, "bytemark data xor loop": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "Saw this in bytemark" ], @@ -187,17 +187,15 @@ "mov x6, x4", "mov x5, x4", "mov x19, x10", - "add x20, x4, #0x1 (1)", - "mov x21, x4", - "mov x4, x20", - "lsr x6, x21, #6", - "and w5, w21, #0x3f", - "lsl x19, x10, x5", - "ldr x21, [x7, x6, sxtx #3]", - "eor x21, x21, x19", - "str x21, [x7, x6, sxtx #3]", - "eor w27, w11, w20", - "subs x26, x11, x20", + "add x4, x4, #0x1 (1)", + "lsr x6, x6, #6", + "and w5, w5, #0x3f", + "lsl x19, x19, x5", + "ldr x20, [x7, x6, sxtx #3]", + "eor x20, x20, x19", + "str x20, [x7, x6, sxtx #3]", + "eor w27, w11, w4", + "subs x26, x11, x4", "cfinv" ] }, @@ -215,7 +213,7 @@ "ExpectedArm64ASM": [ "ldr x17, [x10, x13, sxtx #3]", "mov x15, x13", - "orr x15, x13, #0x1", + "orr x15, x15, #0x1", "ldr x20, [x10, x15, sxtx #3]", "eor w27, w17, w20", "subs x26, x17, x20", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index b238ff47d..44ae86e9e 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -75,13 +75,13 @@ "add w10, w10, #0x40 (64)", "add w11, w11, #0x40 (64)", "sub w5, w5, #0x40 (64)", - "mov x27, x5", "subs w26, w5, #0x40 (64)", - "cfinv" + "cfinv", + "mov x27, x5" ] }, "dxvk hotblock from MGRR": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 38, "Comment": [ "Hottest block in Metal Gear Rising: Revengeance render thread" ], @@ -111,34 +111,31 @@ "mov x20, #0xffffffffffffffdc", "ldr w10, [x9, w20, sxtw]", "mov w20, #0xffffffff", - "adds w5, w4, w20", - "mvn w27, w6", - "adcs w26, w6, w20", + "adds w5, w5, w20", + "mvn w27, w7", + "adcs w26, w7, w20", "mov x7, x26", "mov x20, #0xffffffffffffffd8", "str w5, [x9, w20, sxtw]", "mov x20, #0xffffffffffffffd4", - "str w26, [x9, w20, sxtw]", + "str w7, [x9, w20, sxtw]", "mov x7, x5", "mov x21, #0xffffffffffffffd0", "str w5, [x9, w21, sxtw]", - "ldr w20, [x9, w20, sxtw]", - "mov x21, x5", - "mov x5, x20", - "add w22, w10, #0x8 (8)", - "mov w24, w4", - "mov w25, w6", - "mov w0, w21", - "mov w21, w20", - "mov w20, w0", - "mov w2, w24", - "mov w3, w25", - "caspal w2, w3, w20, w21, [x22]", + "ldr w5, [x9, w20, sxtw]", + "add w20, w10, #0x8 (8)", + "mov w22, w4", + "mov w23, w6", + "mov w24, w7", + "mov w25, w5", + "mov w2, w22", + "mov w3, w23", + "caspal w2, w3, w24, w25, [x20]", "mov w20, w2", "mov w21, w3", "mrs x0, nzcv", - "cmp w20, w24", - "ccmp w21, w25, #nzcv, eq", + "cmp w20, w22", + "ccmp w21, w23, #nzcv, eq", "rmif x0, #0, #NzCV", "mov w22, w21", "csel x4, x20, x4, ne", @@ -146,7 +143,7 @@ ] }, "Psychonauts matrix swizzle": { - "ExpectedInstructionCount": 2406, + "ExpectedInstructionCount": 2340, "Comment": [ "Hottest block in Windows Psychonauts", "Doing a 4x4 32-bit float matrix swizzle", @@ -260,15 +257,14 @@ "ExpectedArm64ASM": [ "str w9, [x8, #-4]!", "mov x9, x8", - "mov x27, x8", "subs w26, w8, #0x44 (68)", "cfinv", - "mov x20, x8", + "mov x27, x8", "mov x8, x26", - "mov x21, #0xffffffffffffffbc", - "str w5, [x20, w21, sxtw]", - "ldr w4, [x20, w21, sxtw]", - "ldrb w20, [x28, #1019]", + "mov x20, #0xffffffffffffffbc", + "str w5, [x9, w20, sxtw]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -298,17 +294,16 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w22, #0x1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldrb w23, [x28, #1298]", - "lsl w24, w22, w20", + "lsl w24, w22, w21", "orr w23, w23, w24", - "strb w23, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -336,16 +331,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x23, #0xffffffffffffffc0", - "str s2, [x9, w23, sxtw]", - "ldrb w24, [x28, #1298]", - "lsl w25, w22, w20", - "bic w24, w24, w25", - "strb w24, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "mov x24, #0xffffffffffffffc0", + "str s2, [x9, w24, sxtw]", + "lsl w25, w22, w21", + "bic w23, w23, w25", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w5, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x5, #16]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -374,16 +368,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w25, w22, w20", - "orr w24, w24, w25", - "strb w24, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w25, w22, w21", + "orr w23, w23, w25", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -411,16 +404,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x24, #0xffffffffffffffc4", - "str s2, [x9, w24, sxtw]", - "ldrb w25, [x28, #1298]", - "lsl w12, w22, w20", - "bic w25, w25, w12", - "strb w25, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "mov x25, #0xffffffffffffffc4", + "str s2, [x9, w25, sxtw]", + "lsl w12, w22, w21", + "bic w23, w23, w12", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w6, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x6, #32]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -449,16 +441,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w12, w22, w20", - "orr w25, w25, w12", - "strb w25, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w12, w22, w21", + "orr w23, w23, w12", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -486,16 +477,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x25, #0xffffffffffffffc8", - "str s2, [x9, w25, sxtw]", - "ldrb w12, [x28, #1298]", - "lsl w13, w22, w20", - "bic w12, w12, w13", - "strb w12, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "mov x12, #0xffffffffffffffc8", + "str s2, [x9, w12, sxtw]", + "lsl w13, w22, w21", + "bic w23, w23, w13", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x4, #48]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -524,16 +514,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w13, w22, w20", - "orr w12, w12, w13", - "strb w12, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w13, w22, w21", + "orr w23, w23, w13", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -561,16 +550,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x12, #0xffffffffffffffcc", - "str s2, [x9, w12, sxtw]", - "ldrb w13, [x28, #1298]", - "lsl w14, w22, w20", - "bic w13, w13, w14", - "strb w13, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "mov x13, #0xffffffffffffffcc", + "str s2, [x9, w13, sxtw]", + "lsl w14, w22, w21", + "bic w23, w23, w14", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w5, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x5, #4]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -599,16 +587,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w14, w22, w20", - "orr w13, w13, w14", - "strb w13, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w14, w22, w21", + "orr w23, w23, w14", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -636,16 +623,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x13, #0xffffffffffffffd0", - "str s2, [x9, w13, sxtw]", - "ldrb w14, [x28, #1298]", - "lsl w15, w22, w20", - "bic w14, w14, w15", - "strb w14, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "mov x14, #0xffffffffffffffd0", + "str s2, [x9, w14, sxtw]", + "lsl w15, w22, w21", + "bic w23, w23, w15", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w6, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x6, #20]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -674,16 +660,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w15, w22, w20", - "orr w14, w14, w15", - "strb w14, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w15, w22, w21", + "orr w23, w23, w15", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -711,16 +696,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x14, #0xffffffffffffffd4", - "str s2, [x9, w14, sxtw]", - "ldrb w15, [x28, #1298]", - "lsl w16, w22, w20", - "bic w15, w15, w16", - "strb w15, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "mov x15, #0xffffffffffffffd4", + "str s2, [x9, w15, sxtw]", + "lsl w16, w22, w21", + "bic w23, w23, w16", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x4, #36]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -749,16 +733,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w16, w22, w20", - "orr w15, w15, w16", - "strb w15, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w16, w22, w21", + "orr w23, w23, w16", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -786,16 +769,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x15, #0xffffffffffffffd8", - "str s2, [x9, w15, sxtw]", - "ldrb w16, [x28, #1298]", - "lsl w17, w22, w20", - "bic w16, w16, w17", - "strb w16, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "mov x16, #0xffffffffffffffd8", + "str s2, [x9, w16, sxtw]", + "lsl w17, w22, w21", + "bic w23, w23, w17", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w5, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x5, #52]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -824,16 +806,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w17, w22, w20", - "orr w16, w16, w17", - "strb w16, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w17, w22, w21", + "orr w23, w23, w17", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -861,16 +842,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x16, #0xffffffffffffffdc", - "str s2, [x9, w16, sxtw]", - "ldrb w17, [x28, #1298]", - "lsl w29, w22, w20", - "bic w17, w17, w29", - "strb w17, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "mov x17, #0xffffffffffffffdc", + "str s2, [x9, w17, sxtw]", + "lsl w29, w22, w21", + "bic w23, w23, w29", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w6, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x6, #8]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -899,16 +879,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w29, w22, w20", - "orr w17, w17, w29", - "strb w17, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w29, w22, w21", + "orr w23, w23, w29", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -936,16 +915,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x17, #0xffffffffffffffe0", - "str s2, [x9, w17, sxtw]", - "ldrb w29, [x28, #1298]", - "lsl w30, w22, w20", - "bic w29, w29, w30", - "strb w29, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "mov x29, #0xffffffffffffffe0", + "str s2, [x9, w29, sxtw]", + "lsl w30, w22, w21", + "bic w23, w23, w30", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x4, #24]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -974,16 +952,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w30, w22, w20", - "orr w29, w29, w30", - "strb w29, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w30, w22, w21", + "orr w23, w23, w30", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1011,16 +988,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x29, #0xffffffffffffffe4", - "str s2, [x9, w29, sxtw]", - "ldrb w30, [x28, #1298]", - "lsl w19, w22, w20", - "bic w30, w30, w19", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "mov x30, #0xffffffffffffffe4", + "str s2, [x9, w30, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w5, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x5, #40]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1049,16 +1025,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w19, w22, w21", + "orr w23, w23, w19", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1086,16 +1061,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xffffffffffffffe8", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "mov x19, #0xffffffffffffffe8", + "str s2, [x9, w19, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w6, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x6, #56]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1124,16 +1098,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w19, w22, w21", + "orr w23, w23, w19", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1161,16 +1134,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xffffffffffffffec", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "mov x19, #0xffffffffffffffec", + "str s2, [x9, w19, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x4, #12]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1199,16 +1171,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w19, w22, w21", + "orr w23, w23, w19", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1236,16 +1207,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff0", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w5, [x9, w21, sxtw]", + "mov x19, #0xfffffffffffffff0", + "str s2, [x9, w19, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w5, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x5, #28]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1274,16 +1244,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w19, w22, w21", + "orr w23, w23, w19", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1311,16 +1280,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff4", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w6, [x9, w21, sxtw]", + "mov x19, #0xfffffffffffffff4", + "str s2, [x9, w19, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w6, [x9, w20, sxtw]", + "ldrb w21, [x28, #1019]", "ldr s2, [x6, #44]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1349,16 +1317,15 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "sub w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "lsl w19, w22, w20", - "orr w30, w30, w19", - "strb w30, [x28, #1298]", - "strb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "sub w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "lsl w19, w22, w21", + "orr w23, w23, w19", + "strb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w20, [x28, #1019]", - "add x0, x28, x20, lsl #4", + "ldrb w21, [x28, #1019]", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1386,16 +1353,15 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x30, #0xfffffffffffffff8", - "str s2, [x9, w30, sxtw]", - "ldrb w19, [x28, #1298]", - "lsl w30, w22, w20", - "bic w30, w19, w30", - "strb w30, [x28, #1298]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #1019]", - "ldr w4, [x9, w21, sxtw]", + "mov x19, #0xfffffffffffffff8", + "str s2, [x9, w19, sxtw]", + "lsl w19, w22, w21", + "bic w23, w23, w19", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #1019]", + "ldr w4, [x9, w20, sxtw]", + "ldrb w20, [x28, #1019]", "ldr s2, [x4, #60]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -1427,8 +1393,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w22, w20", - "orr w21, w30, w21", - "strb w21, [x28, #1298]", + "orr w21, w23, w21", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1461,17 +1426,16 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "fmov s2, s0", - "mov x21, #0xfffffffffffffffc", - "str s2, [x9, w21, sxtw]", - "ldrb w30, [x28, #1298]", + "mov x23, #0xfffffffffffffffc", + "str s2, [x9, w23, sxtw]", "lsl w19, w22, w20", - "bic w30, w30, w19", - "strb w30, [x28, #1298]", + "bic w21, w21, w19", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", - "ldr s2, [x9, w23, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1501,9 +1465,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w23, w22, w20", - "orr w23, w30, w23", - "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1537,15 +1500,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5]", - "ldrb w23, [x28, #1298]", - "lsl w30, w22, w20", - "bic w23, w23, w30", - "strb w23, [x28, #1298]", + "lsl w24, w22, w20", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w6, [x9, #8]", - "ldr s2, [x9, w24, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w25, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1576,8 +1538,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1611,15 +1572,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #4]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", - "ldr s2, [x9, w25, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w12, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1650,8 +1610,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1685,15 +1644,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #8]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", - "ldr s2, [x9, w12, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w13, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1724,8 +1682,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1759,15 +1716,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5, #12]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w6, [x9, #8]", - "ldr s2, [x9, w13, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w14, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1798,8 +1754,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1833,15 +1788,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #16]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", - "ldr s2, [x9, w14, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w15, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1872,8 +1826,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1907,15 +1860,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #20]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", - "ldr s2, [x9, w15, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w16, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -1946,8 +1898,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -1981,15 +1932,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5, #24]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w6, [x9, #8]", - "ldr s2, [x9, w16, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w17, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2020,8 +1970,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2055,15 +2004,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #28]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", - "ldr s2, [x9, w17, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w29, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2094,8 +2042,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2129,15 +2076,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #32]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", - "ldr s2, [x9, w29, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w30, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2168,8 +2114,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2203,14 +2148,13 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5, #36]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w6, [x9, #8]", + "ldrb w20, [x28, #1019]", "mov x24, #0xffffffffffffffe8", "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", @@ -2243,8 +2187,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2278,14 +2221,13 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #40]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", + "ldrb w20, [x28, #1019]", "mov x24, #0xffffffffffffffec", "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", @@ -2318,8 +2260,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2353,14 +2294,13 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #44]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", + "ldrb w20, [x28, #1019]", "mov x24, #0xfffffffffffffff0", "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", @@ -2393,8 +2333,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2428,14 +2367,13 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5, #48]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w6, [x9, #8]", + "ldrb w20, [x28, #1019]", "mov x24, #0xfffffffffffffff4", "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", @@ -2468,8 +2406,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2503,14 +2440,13 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x6, #52]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", + "ldrb w20, [x28, #1019]", "mov x24, #0xfffffffffffffff8", "ldr s2, [x9, w24, sxtw]", "mrs x0, nzcv", @@ -2543,8 +2479,7 @@ "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w24, w22, w20", - "orr w23, w23, w24", - "strb w23, [x28, #1298]", + "orr w21, w21, w24", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2578,15 +2513,14 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #56]", - "ldrb w23, [x28, #1298]", "lsl w24, w22, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1298]", + "bic w21, w21, w24", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w5, [x9, #8]", - "ldr s2, [x9, w21, sxtw]", + "ldrb w20, [x28, #1019]", + "ldr s2, [x9, w23, sxtw]", "mrs x0, nzcv", "str w0, [x28, #1000]", "stp x4, x5, [x28, #280]", @@ -2616,9 +2550,8 @@ "mov v2.h[4], w1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "lsl w21, w22, w20", - "orr w21, w23, w21", - "strb w21, [x28, #1298]", + "lsl w23, w22, w20", + "orr w21, w21, w23", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -2652,18 +2585,16 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x5, #60]", - "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w4, [x9, #8]", "mov x8, x9", - "ldr w20, [x9]", - "add x8, x9, #0x4 (4)", - "mov x9, x20" + "ldr w9, [x8]", + "add x8, x8, #0x4 (4)", + "strb w21, [x28, #1298]" ] } } diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 58745554e..69349b31b 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -58,10 +58,10 @@ "mov w10, w5", "mov x6, x9", "mov x4, x7", - "ldr s18, [x9]", - "add x4, x7, #0x20 (32)", + "ldr s18, [x6]", + "add x4, x4, #0x20 (32)", "fmul s18, s18, s16", - "add x6, x9, #0x20 (32)", + "add x6, x6, #0x20 (32)", "ldur s2, [x4, #-32]", "fadd s18, s18, s2", "stur s18, [x4, #-32]", @@ -100,9 +100,9 @@ "ldur s2, [x4, #-4]", "fadd s18, s18, s2", "stur s18, [x4, #-4]", - "mov x27, x10", "subs w26, w10, #0x1 (1)", "cfinv", + "mov x27, x10", "mov x10, x26" ] } diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 1b3274720..36c953d51 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -105,35 +105,39 @@ ] }, "add al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -141,8 +145,8 @@ "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -221,18 +225,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr w7, w7, w5", - "mov x26, x7", - "tst w7, w7" + "orr w26, w7, w5", + "tst w26, w26", + "mov x7, x26" ] }, "or rbx, rcx": { "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr x7, x7, x5", - "mov x26, x7", - "tst x7, x7" + "orr x26, x7, x5", + "tst x26, x26", + "mov x7, x26" ] }, "db 0x0A, 0xcb": { @@ -266,9 +270,9 @@ "or ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w5, w5, w7", - "mov x26, x5", - "tst w5, w5" + "orr w26, w5, w7", + "tst w26, w26", + "mov x5, x26" ] }, "db 0x48, 0x0B, 0xcb": { @@ -278,9 +282,9 @@ "or rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr x5, x5, x7", - "mov x26, x5", - "tst x5, x5" + "orr x26, x5, x7", + "tst x26, x26", + "mov x5, x26" ] }, "or al, 1": { @@ -305,18 +309,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "or al, -1": { @@ -342,9 +346,9 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "orr w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -1": { @@ -352,9 +356,9 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "orr x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "adc bl, cl": { @@ -486,10 +490,9 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -502,14 +505,16 @@ "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #7, #nzcV", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -522,7 +527,10 @@ "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #15, #nzcV", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "adc eax, 1": { @@ -530,8 +538,8 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -540,8 +548,8 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -746,10 +754,9 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 15, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov x27, x4", "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -761,14 +768,16 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #7, #nzcV", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 15, "Comment": "0x1D", "ExpectedArm64ASM": [ - "mov x27, x4", "uxth w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -780,7 +789,10 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #15, #nzcV", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "sbb eax, 1": { @@ -788,10 +800,10 @@ "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "cfinv", "sbcs w26, w4, w20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -800,10 +812,10 @@ "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "cfinv", "sbcs x26, x4, x20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -1121,38 +1133,42 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "cfinv", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", "cfinv", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "sub eax, 1": { "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -1160,9 +1176,9 @@ "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -1235,18 +1251,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor w7, w7, w5", - "mov x26, x7", - "tst w7, w7" + "eor w26, w7, w5", + "tst w26, w26", + "mov x7, x26" ] }, "xor rbx, rcx": { "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor x7, x7, x5", - "mov x26, x7", - "tst x7, x7" + "eor x26, x7, x5", + "tst x26, x26", + "mov x7, x26" ] }, "db 0x32, 0xcb": { @@ -1280,9 +1296,9 @@ "xor ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w5, w5, w7", - "mov x26, x5", - "tst w5, w5" + "eor w26, w5, w7", + "tst w26, w26", + "mov x5, x26" ] }, "db 0x48, 0x33, 0xcb": { @@ -1292,9 +1308,9 @@ "xor rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor x5, x5, x7", - "mov x26, x5", - "tst x5, x5" + "eor x26, x5, x7", + "tst x26, x26", + "mov x5, x26" ] }, "xor al, 1": { @@ -1319,18 +1335,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "cmp bl, cl": { @@ -1367,9 +1383,9 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "eor w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -1": { @@ -1377,9 +1393,9 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "eor x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "cmp bx, cx": { @@ -1468,11 +1484,11 @@ "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp ax, 1": { @@ -1480,29 +1496,29 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp eax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp rax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp al, -1": { @@ -1766,24 +1782,24 @@ "strb w20, [x28, #985]", "ubfx w20, w27, #10, #1", "sub x20, x21, x20, lsl #1", - "strb w20, [x28, #986]", "rmif x27, #11, #nzcV", - "ubfx w20, w27, #12, #1", - "strb w20, [x28, #988]", - "ubfx w20, w27, #14, #1", - "strb w20, [x28, #990]", - "ubfx w20, w27, #16, #1", - "strb w20, [x28, #992]", - "ubfx w20, w27, #17, #1", - "strb w20, [x28, #993]", - "ubfx w20, w27, #18, #1", - "strb w20, [x28, #994]", - "ubfx w20, w27, #19, #1", - "strb w20, [x28, #995]", - "ubfx w20, w27, #20, #1", - "strb w20, [x28, #996]", - "ubfx w20, w27, #21, #1", - "strb w20, [x28, #997]" + "ubfx w21, w27, #12, #1", + "strb w21, [x28, #988]", + "ubfx w21, w27, #14, #1", + "strb w21, [x28, #990]", + "ubfx w21, w27, #16, #1", + "strb w21, [x28, #992]", + "ubfx w21, w27, #17, #1", + "strb w21, [x28, #993]", + "ubfx w21, w27, #18, #1", + "strb w21, [x28, #994]", + "ubfx w21, w27, #19, #1", + "strb w21, [x28, #995]", + "ubfx w21, w27, #20, #1", + "strb w21, [x28, #996]", + "ubfx w21, w27, #21, #1", + "strb w21, [x28, #997]", + "strb w20, [x28, #986]" ] }, "sahf": { @@ -1893,10 +1909,10 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1917,19 +1933,18 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #24", + "lsl w0, w27, #24", "cmp w0, w26, lsl #24", - "sub w26, w21, w26", - "cfinv" + "sub w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1950,19 +1965,18 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #16", + "lsl w0, w27, #16", "cmp w0, w26, lsl #16", - "sub w26, w21, w26", - "cfinv" + "sub w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x64", + "cbz x5, #+0x60", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1983,17 +1997,16 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs w26, w21, w26", - "cfinv" + "subs w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x64", + "cbz x5, #+0x60", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2014,17 +2027,16 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs x26, x21, x26", - "cfinv" + "subs x26, x27, x26", + "cfinv", + "mov x27, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2045,19 +2057,18 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #24", + "lsl w0, w27, #24", "cmp w0, w26, lsl #24", - "sub w26, w21, w26", - "cfinv" + "sub w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2078,19 +2089,18 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #16", + "lsl w0, w27, #16", "cmp w0, w26, lsl #16", - "sub w26, w21, w26", - "cfinv" + "sub w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x64", + "cbz x5, #+0x60", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2111,17 +2121,16 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs w26, w21, w26", - "cfinv" + "subs w26, w27, w26", + "cfinv", + "mov x27, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 24, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x64", + "cbz x5, #+0x60", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2142,10 +2151,9 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs x26, x21, x26", - "cfinv" + "subs x26, x27, x26", + "cfinv", + "mov x27, x20" ] }, "test al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 44a94f971..7961582e5 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -13,15 +13,17 @@ }, "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "or al, 1": { @@ -34,10 +36,9 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -50,14 +51,16 @@ "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #7, #nzcV", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 15, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov x27, x4", "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -69,7 +72,10 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #7, #nzcV", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "and al, 1": { @@ -82,16 +88,18 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "cfinv", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "xor al, 1": { @@ -108,11 +116,11 @@ "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "add al, -1": { @@ -219,23 +227,25 @@ ] }, "add ax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x100 (256)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -243,8 +253,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -252,18 +262,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0x100", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x100", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0x100", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x100", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, 256": { @@ -271,8 +281,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -281,8 +291,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -291,10 +301,10 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "cfinv", "sbcs w26, w4, w20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -303,10 +313,10 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "cfinv", "sbcs x26, x4, x20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -330,9 +340,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x100 (256)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -340,9 +350,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -350,48 +360,50 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0x100", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x100", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0x100", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x100", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x100 (256)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp rax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "add ax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, -256": { @@ -399,8 +411,8 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "adds w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -408,8 +420,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -417,18 +429,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0xffffff00", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0xffffff00", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0xffffffffffffff00", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0xffffffffffffff00", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, -256": { @@ -436,8 +448,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -446,8 +458,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -456,10 +468,10 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "cfinv", "sbcs w26, w4, w20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -468,10 +480,10 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x27, x4", "cfinv", "sbcs x26, x4, x20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -496,9 +508,9 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "subs w26, w4, w20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -506,9 +518,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -516,18 +528,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0xffffff00", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0xffffff00", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0xffffffffffffff00", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0xffffffffffffff00", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, -256": { @@ -535,38 +547,40 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "subs w26, w4, w20", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp rax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "add ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -574,8 +588,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -583,18 +597,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, 1": { @@ -602,8 +616,8 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -612,8 +626,8 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -622,10 +636,10 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "cfinv", "sbcs w26, w4, w20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -634,10 +648,10 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "cfinv", "sbcs x26, x4, x20", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -661,9 +675,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -671,9 +685,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "cfinv", + "mov x27, x4", "mov x4, x26" ] }, @@ -681,36 +695,36 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "cmp rax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", - "cfinv" + "cfinv", + "mov x27, x4" ] }, "add ax, -1": { @@ -749,9 +763,9 @@ "Comment": "GROUP1 0x83 /-1", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "orr w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -1": { @@ -759,9 +773,9 @@ "Comment": "GROUP1 0x83 /-1", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "orr x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, -1": { @@ -852,9 +866,9 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "eor w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -1": { @@ -862,9 +876,9 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "eor x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, -1": { @@ -2027,14 +2041,16 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ - "mov x27, x7", "cmp wzr, w7, lsl #24", "neg w26, w7", "cfinv", - "bfxil x7, x26, #0, #8" + "mov x20, x7", + "bfxil x20, x26, #0, #8", + "mov x27, x7", + "mov x7, x20" ] }, "mul bl": { @@ -2141,23 +2157,25 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "cmp wzr, w7, lsl #16", "neg w26, w7", "cfinv", - "bfxil x7, x26, #0, #16" + "mov x20, x7", + "bfxil x20, x26, #0, #16", + "mov x27, x7", + "mov x7, x20" ] }, "neg ebx": { "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "negs w26, w7", "cfinv", + "mov x27, x7", "mov x7, x26" ] }, @@ -2165,9 +2183,9 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "negs x26, x7", "cfinv", + "mov x27, x7", "mov x7, x26" ] }, @@ -2204,9 +2222,9 @@ "ExpectedArm64ASM": [ "mul x20, x7, x4", "umulh x6, x7, x4", - "mov x4, x20", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmn xzr, #0, #nzCV, eq", + "mov x4, x20" ] }, "imul bx": { @@ -2310,9 +2328,9 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -2321,9 +2339,9 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -2344,9 +2362,9 @@ "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -2355,9 +2373,9 @@ "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] } diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 225e7e342..4fa69a3d9 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -197,9 +197,9 @@ "Comment": "0x40", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, @@ -234,9 +234,9 @@ "Comment": "0x48", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", + "mov x27, x4", "mov x4, x26" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 4afa6b530..de51a99ff 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1059,13 +1059,15 @@ ] }, "cmpxchg rcx, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 7, "ExpectedArm64ASM": [ "eor w27, w4, w5", "subs x26, x4, x5", "cfinv", - "mov x4, x5", - "csel x5, x7, x5, eq" + "csel x20, x7, x5, eq", + "mov x21, x5", + "mov x5, x20", + "mov x4, x21" ] }, "cmpxchg [rax], rbx": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 378bd69af..87edf7098 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -1205,21 +1205,21 @@ "strh w20, [x4, #2]", "ldrb w20, [x28, #1298]", "strb w20, [x4, #4]", - "ldr q2, [x28, #1040]", + "ldr d2, [x28, #1040]", "str q2, [x4, #32]", - "ldr q2, [x28, #1056]", + "ldr d2, [x28, #1056]", "str q2, [x4, #48]", - "ldr q2, [x28, #1072]", + "ldr d2, [x28, #1072]", "str q2, [x4, #64]", - "ldr q2, [x28, #1088]", + "ldr d2, [x28, #1088]", "str q2, [x4, #80]", - "ldr q2, [x28, #1104]", + "ldr d2, [x28, #1104]", "str q2, [x4, #96]", - "ldr q2, [x28, #1120]", + "ldr d2, [x28, #1120]", "str q2, [x4, #112]", - "ldr q2, [x28, #1136]", + "ldr d2, [x28, #1136]", "str q2, [x4, #128]", - "ldr q2, [x28, #1152]", + "ldr d2, [x28, #1152]", "str q2, [x4, #144]", "str q16, [x4, #160]", "str q17, [x4, #176]", @@ -1280,23 +1280,14 @@ "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1298]", "ldr q2, [x4, #32]", - "str q2, [x28, #1040]", - "ldr q2, [x4, #48]", - "str q2, [x28, #1056]", - "ldr q2, [x4, #64]", - "str q2, [x28, #1072]", - "ldr q2, [x4, #80]", - "str q2, [x28, #1088]", - "ldr q2, [x4, #96]", - "str q2, [x28, #1104]", - "ldr q2, [x4, #112]", - "str q2, [x28, #1120]", - "ldr q2, [x4, #128]", - "str q2, [x28, #1136]", - "ldr q2, [x4, #144]", - "str q2, [x28, #1152]", + "ldr q3, [x4, #48]", + "ldr q4, [x4, #64]", + "ldr q5, [x4, #80]", + "ldr q6, [x4, #96]", + "ldr q7, [x4, #112]", + "ldr q8, [x4, #128]", + "ldr q9, [x4, #144]", "ldr q16, [x4, #160]", "ldr q17, [x4, #176]", "ldr q18, [x4, #192]", @@ -1313,15 +1304,24 @@ "ldr q29, [x4, #368]", "ldr q30, [x4, #384]", "ldr q31, [x4, #400]", - "ldr w20, [x4, #24]", - "ubfx w20, w20, #13, #3", - "rbit w1, w20", + "ldr w21, [x4, #24]", + "ubfx w21, w21, #13, #3", + "rbit w1, w21", "lsr w1, w1, #30", "mrs x0, fpcr", "bfi x0, x1, #22, #2", - "lsr x1, x20, #2", + "lsr x1, x21, #2", "bfi x0, x1, #24, #1", - "msr fpcr, x0" + "msr fpcr, x0", + "strb w20, [x28, #1298]", + "str d9, [x28, #1152]", + "str d8, [x28, #1136]", + "str d7, [x28, #1120]", + "str d6, [x28, #1104]", + "str d5, [x28, #1088]", + "str d4, [x28, #1072]", + "str d3, [x28, #1056]", + "str d2, [x28, #1040]" ] }, "rdgsbase eax": { @@ -1419,21 +1419,21 @@ "strh w20, [x4, #2]", "ldrb w20, [x28, #1298]", "strb w20, [x4, #4]", - "ldr q2, [x28, #1040]", + "ldr d2, [x28, #1040]", "str q2, [x4, #32]", - "ldr q2, [x28, #1056]", + "ldr d2, [x28, #1056]", "str q2, [x4, #48]", - "ldr q2, [x28, #1072]", + "ldr d2, [x28, #1072]", "str q2, [x4, #64]", - "ldr q2, [x28, #1088]", + "ldr d2, [x28, #1088]", "str q2, [x4, #80]", - "ldr q2, [x28, #1104]", + "ldr d2, [x28, #1104]", "str q2, [x4, #96]", - "ldr q2, [x28, #1120]", + "ldr d2, [x28, #1120]", "str q2, [x4, #112]", - "ldr q2, [x28, #1136]", + "ldr d2, [x28, #1136]", "str q2, [x4, #128]", - "ldr q2, [x28, #1152]", + "ldr d2, [x28, #1152]", "str q2, [x4, #144]", "ubfx x20, x4, #1, #1", "cbnz x20, #+0x8", @@ -1499,23 +1499,23 @@ "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1298]", "ldr q2, [x4, #32]", - "str q2, [x28, #1040]", - "ldr q2, [x4, #48]", - "str q2, [x28, #1056]", - "ldr q2, [x4, #64]", - "str q2, [x28, #1072]", - "ldr q2, [x4, #80]", - "str q2, [x28, #1088]", - "ldr q2, [x4, #96]", - "str q2, [x28, #1104]", - "ldr q2, [x4, #112]", - "str q2, [x28, #1120]", - "ldr q2, [x4, #128]", - "str q2, [x28, #1136]", - "ldr q2, [x4, #144]", - "str q2, [x28, #1152]", + "ldr q3, [x4, #48]", + "ldr q4, [x4, #64]", + "ldr q5, [x4, #80]", + "ldr q6, [x4, #96]", + "ldr q7, [x4, #112]", + "ldr q8, [x4, #128]", + "ldr q9, [x4, #144]", + "strb w20, [x28, #1298]", + "str d9, [x28, #1152]", + "str d8, [x28, #1136]", + "str d7, [x28, #1120]", + "str d6, [x28, #1104]", + "str d5, [x28, #1088]", + "str d4, [x28, #1072]", + "str d3, [x28, #1056]", + "str d2, [x28, #1040]", "b #+0x4c", "mov w20, #0x0", "mov w21, #0x37f", @@ -1525,16 +1525,16 @@ "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]", "movi v2.2d, #0x0", - "str q2, [x28, #1040]", - "str q2, [x28, #1056]", - "str q2, [x28, #1072]", - "str q2, [x28, #1088]", - "str q2, [x28, #1104]", - "str q2, [x28, #1120]", - "str q2, [x28, #1136]", - "str q2, [x28, #1152]", + "strb w20, [x28, #1298]", + "str d2, [x28, #1152]", + "str d2, [x28, #1136]", + "str d2, [x28, #1120]", + "str d2, [x28, #1104]", + "str d2, [x28, #1088]", + "str d2, [x28, #1072]", + "str d2, [x28, #1056]", + "str d2, [x28, #1040]", "ldr x20, [x4, #512]", "ubfx x20, x20, #1, #1", "cbnz x20, #+0x8", @@ -1556,22 +1556,22 @@ "ldr q30, [x4, #384]", "ldr q31, [x4, #400]", "b #+0x44", - "movi v16.2d, #0x0", - "mov v17.16b, v16.16b", - "mov v18.16b, v16.16b", - "mov v19.16b, v16.16b", - "mov v20.16b, v16.16b", - "mov v21.16b, v16.16b", - "mov v22.16b, v16.16b", - "mov v23.16b, v16.16b", - "mov v24.16b, v16.16b", - "mov v25.16b, v16.16b", - "mov v26.16b, v16.16b", - "mov v27.16b, v16.16b", - "mov v28.16b, v16.16b", - "mov v29.16b, v16.16b", - "mov v30.16b, v16.16b", - "mov v31.16b, v16.16b", + "movi v31.2d, #0x0", + "mov v30.16b, v31.16b", + "mov v29.16b, v31.16b", + "mov v28.16b, v31.16b", + "mov v27.16b, v31.16b", + "mov v26.16b, v31.16b", + "mov v25.16b, v31.16b", + "mov v24.16b, v31.16b", + "mov v23.16b, v31.16b", + "mov v22.16b, v31.16b", + "mov v21.16b, v31.16b", + "mov v20.16b, v31.16b", + "mov v19.16b, v31.16b", + "mov v18.16b, v31.16b", + "mov v17.16b, v31.16b", + "mov v16.16b, v31.16b", "ldr x20, [x4, #512]", "ubfx x20, x20, #1, #2", "cbnz x20, #+0x8", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index f83e40ecd..154194f20 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -349,9 +349,9 @@ "Map 2 0b00 0xf2 32-bit" ], "ExpectedArm64ASM": [ - "bic w4, w5, w7", - "mov x26, x4", - "tst w4, w4" + "bic w26, w5, w7", + "tst w26, w26", + "mov x4, x26" ] }, "andn rax, rbx, rcx": { @@ -360,9 +360,9 @@ "Map 2 0b00 0xf2 64-bit" ], "ExpectedArm64ASM": [ - "bic x4, x5, x7", - "mov x26, x4", - "tst x4, x4" + "bic x26, x5, x7", + "tst x26, x26", + "mov x4, x26" ] }, "bzhi eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index e7847ada5..9080a088d 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -311,10 +311,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub dword [rax]": { @@ -1832,10 +1832,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st1": { @@ -1893,10 +1893,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st2": { @@ -1954,10 +1954,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st3": { @@ -2015,10 +2015,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st4": { @@ -2076,10 +2076,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st5": { @@ -2137,10 +2137,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st6": { @@ -2198,10 +2198,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st7": { @@ -2259,10 +2259,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub st0, st0": { @@ -3810,10 +3810,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fst dword [rax]": { @@ -3894,10 +3894,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fldenv [rax]": { @@ -3952,8 +3952,8 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1298]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w20, [x28, #1298]" ] }, "fldcw [rax]": { @@ -4065,10 +4065,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st1": { @@ -4088,10 +4088,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st2": { @@ -4111,10 +4111,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st3": { @@ -4134,10 +4134,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st4": { @@ -4157,10 +4157,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st5": { @@ -4180,10 +4180,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st6": { @@ -4203,10 +4203,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st7": { @@ -4226,10 +4226,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxch st0, st0": { @@ -4530,11 +4530,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2672]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2t": { @@ -4550,11 +4550,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2688]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2e": { @@ -4570,11 +4570,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2704]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldpi": { @@ -4590,11 +4590,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2720]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldlg2": { @@ -4610,11 +4610,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2736]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldln2": { @@ -4630,11 +4630,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2752]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldz": { @@ -4650,11 +4650,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "movi v2.2d, #0x0", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "f2xm1": { @@ -4709,13 +4709,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4747,8 +4746,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fptan": { @@ -4764,7 +4764,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -4797,12 +4796,13 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "ldr q3, [x28, #2672]", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q3, [x0, #1040]" + "str q3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fpatan": { @@ -4816,13 +4816,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4854,8 +4853,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxtract": { @@ -4871,7 +4871,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -4934,7 +4933,8 @@ "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fprem1": { @@ -5070,13 +5070,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "ldr q4, [x28, #2672]", "mrs x0, nzcv", @@ -5139,8 +5138,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsqrt": { @@ -5197,7 +5197,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -5257,12 +5256,13 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "frndint": { @@ -5737,10 +5737,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub dword [rax]": { @@ -6732,7 +6732,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -6786,19 +6786,18 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /5" ], @@ -6810,33 +6809,34 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "mov w22, #0x0", - "sxtw x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", + "ldr w22, [x4]", + "mov w23, #0x0", + "sxtw x22, w22", + "mrs x24, nzcv", + "cmp x22, #0x0 (0)", + "mov w25, #0x8000", + "csel x25, x25, xzr, lt", + "cneg x22, x22, mi", + "mov w30, #0x3f", "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", + "clz x18, x22", + "sub x18, x0, x18", + "sub x30, x30, x18", + "lsl x18, x22, x30", + "mov w23, #0x403e", + "sub x23, x23, x30", + "mov w30, #0x0", + "cmp x22, #0x0 (0)", + "csel x22, x30, x23, eq", + "orr x22, x25, x22", + "fmov d2, x18", + "fmov d3, x22", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x24", + "strb w21, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -6879,10 +6879,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist dword [rax]": { @@ -6963,10 +6963,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fld tword [rax]": { @@ -6983,10 +6983,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -7005,10 +7005,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcmovnb st0, st0": { @@ -8845,10 +8845,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub qword [rax]": { @@ -11444,10 +11444,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -11490,10 +11490,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fst qword [rax]": { @@ -11574,10 +11574,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "frstor [rax]": { @@ -11632,63 +11632,63 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #38]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldr q3, [x4, #48]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #58]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #68]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #78]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #88]", "and v2.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur d2, [x4, #98]", "ldr h3, [x4, #106]", "mov v2.h[4], v3.h[0]", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w20, [x28, #1298]" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Comment": [ "0xdd !11b /6" ], @@ -11697,8 +11697,10 @@ "ldrh w21, [x28, #1296]", "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", + "ldrb w22, [x28, #1019]", + "mov x0, x21", + "bfi x0, x22, #11, #3", + "mov x22, x0", "ldrb w23, [x28, #1016]", "ldrb w24, [x28, #1017]", "ldrb w25, [x28, #1018]", @@ -11802,8 +11804,8 @@ "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x25", + "strb w21, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -12115,7 +12117,7 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd8 /3" ], @@ -12131,17 +12133,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd9 /3" ], @@ -12157,17 +12158,16 @@ "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", - "strb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xda /3" ], @@ -12183,17 +12183,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdb /3" ], @@ -12209,17 +12208,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdc /3" ], @@ -12235,17 +12233,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdd /3" ], @@ -12261,17 +12258,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xde /3" ], @@ -12287,17 +12283,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdf /3" ], @@ -12313,13 +12308,12 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucom st0": { @@ -12801,10 +12795,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st1": { @@ -12862,10 +12856,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st2": { @@ -12923,10 +12917,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st3": { @@ -12984,10 +12978,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st4": { @@ -13045,10 +13039,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st5": { @@ -13106,10 +13100,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st6": { @@ -13167,10 +13161,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st7": { @@ -13228,10 +13222,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fiadd word [rax]": { @@ -13532,10 +13526,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub word [rax]": { @@ -13869,12 +13863,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st1": { @@ -13924,12 +13918,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "faddp st2": { @@ -13979,12 +13973,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st3": { @@ -14034,12 +14028,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st4": { @@ -14089,12 +14083,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st5": { @@ -14144,12 +14138,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st6": { @@ -14199,12 +14193,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st7": { @@ -14254,12 +14248,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st0": { @@ -14309,12 +14303,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st1": { @@ -14364,12 +14358,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fmulp st2": { @@ -14419,12 +14413,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st3": { @@ -14474,12 +14468,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st4": { @@ -14529,12 +14523,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st5": { @@ -14584,12 +14578,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st6": { @@ -14639,12 +14633,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st7": { @@ -14694,16 +14688,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fcompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -14757,15 +14751,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "db 0xde, 0xe0": { @@ -14817,12 +14810,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st1, st0": { @@ -14872,12 +14865,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubrp st2, st0": { @@ -14927,12 +14920,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st3, st0": { @@ -14982,12 +14975,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st4, st0": { @@ -15037,12 +15030,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st5, st0": { @@ -15092,12 +15085,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st6, st0": { @@ -15147,12 +15140,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st7, st0": { @@ -15202,12 +15195,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xe8": { @@ -15259,12 +15252,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st1, st0": { @@ -15314,12 +15307,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubp st2, st0": { @@ -15369,12 +15362,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st3, st0": { @@ -15424,12 +15417,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st4, st0": { @@ -15479,12 +15472,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st5, st0": { @@ -15534,12 +15527,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st6, st0": { @@ -15589,12 +15582,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st7, st0": { @@ -15644,12 +15637,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf0": { @@ -15701,12 +15694,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st1, st0": { @@ -15756,12 +15749,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivrp st2, st0": { @@ -15811,12 +15804,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st3, st0": { @@ -15866,12 +15859,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st4, st0": { @@ -15921,12 +15914,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st5, st0": { @@ -15976,12 +15969,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st6, st0": { @@ -16031,12 +16024,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st7, st0": { @@ -16086,12 +16079,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf8": { @@ -16143,12 +16136,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st1, st0": { @@ -16198,12 +16191,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivp st2, st0": { @@ -16253,12 +16246,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st3, st0": { @@ -16308,12 +16301,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st4, st0": { @@ -16363,12 +16356,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st5, st0": { @@ -16418,12 +16411,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st6, st0": { @@ -16473,12 +16466,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st7, st0": { @@ -16528,16 +16521,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fild word [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /0" ], @@ -16549,33 +16542,34 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "mov w22, #0x0", - "sxth x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", + "ldrh w22, [x4]", + "mov w23, #0x0", + "sxth x22, w22", + "mrs x24, nzcv", + "cmp x22, #0x0 (0)", + "mov w25, #0x8000", + "csel x25, x25, xzr, lt", + "cneg x22, x22, mi", + "mov w30, #0x3f", "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", + "clz x18, x22", + "sub x18, x0, x18", + "sub x30, x30, x18", + "lsl x18, x22, x30", + "mov w23, #0x403e", + "sub x23, x23, x30", + "mov w30, #0x0", + "cmp x22, #0x0 (0)", + "csel x22, x30, x23, eq", + "orr x22, x25, x22", + "fmov d2, x18", + "fmov d3, x22", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x24", + "strb w21, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -16618,10 +16612,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist word [rax]": { @@ -16702,10 +16696,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fbld tword [rax]": { @@ -16721,7 +16715,6 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -16753,7 +16746,8 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -16800,10 +16794,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "ffreep st0": { @@ -16975,10 +16969,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st1": { @@ -17034,10 +17028,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st2": { @@ -17093,10 +17087,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st3": { @@ -17152,10 +17146,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st4": { @@ -17211,10 +17205,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st5": { @@ -17270,10 +17264,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st6": { @@ -17329,10 +17323,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st7": { @@ -17388,10 +17382,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st0": { @@ -17447,10 +17441,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st1": { @@ -17506,10 +17500,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st2": { @@ -17565,10 +17559,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st3": { @@ -17624,10 +17618,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st4": { @@ -17683,10 +17677,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st5": { @@ -17742,10 +17736,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st6": { @@ -17801,10 +17795,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st7": { @@ -17860,10 +17854,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] } } diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 3a84afc12..9845cb9be 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -95,10 +95,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub dword [rax]": { @@ -680,10 +680,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st1": { @@ -713,10 +713,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st2": { @@ -746,10 +746,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st3": { @@ -779,10 +779,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st4": { @@ -812,10 +812,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st5": { @@ -845,10 +845,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st6": { @@ -878,10 +878,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st7": { @@ -911,10 +911,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub st0, st0": { @@ -1508,10 +1508,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fst dword [rax]": { @@ -1542,10 +1542,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fldenv [rax]": { @@ -1608,8 +1608,8 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1298]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w20, [x28, #1298]" ] }, "fldcw [rax]": { @@ -1729,10 +1729,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st1": { @@ -1752,10 +1752,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st2": { @@ -1775,10 +1775,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st3": { @@ -1798,10 +1798,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st4": { @@ -1821,10 +1821,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st5": { @@ -1844,10 +1844,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st6": { @@ -1867,10 +1867,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st7": { @@ -1890,10 +1890,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxch st0, st0": { @@ -2160,12 +2160,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x3ff0000000000000", - "fmov d2, x21", + "mov x22, #0x3ff0000000000000", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2t": { @@ -2181,15 +2181,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0xa372", - "movk x21, #0x979, lsl #16", - "movk x21, #0x934f, lsl #32", - "movk x21, #0x400a, lsl #48", - "fmov d2, x21", + "mov x22, #0xa372", + "movk x22, #0x979, lsl #16", + "movk x22, #0x934f, lsl #32", + "movk x22, #0x400a, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2e": { @@ -2205,15 +2205,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x82fe", - "movk x21, #0x652b, lsl #16", - "movk x21, #0x1547, lsl #32", - "movk x21, #0x3ff7, lsl #48", - "fmov d2, x21", + "mov x22, #0x82fe", + "movk x22, #0x652b, lsl #16", + "movk x22, #0x1547, lsl #32", + "movk x22, #0x3ff7, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldpi": { @@ -2229,15 +2229,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x2d18", - "movk x21, #0x5444, lsl #16", - "movk x21, #0x21fb, lsl #32", - "movk x21, #0x4009, lsl #48", - "fmov d2, x21", + "mov x22, #0x2d18", + "movk x22, #0x5444, lsl #16", + "movk x22, #0x21fb, lsl #32", + "movk x22, #0x4009, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldlg2": { @@ -2253,15 +2253,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x79ff", - "movk x21, #0x509f, lsl #16", - "movk x21, #0x4413, lsl #32", - "movk x21, #0x3fd3, lsl #48", - "fmov d2, x21", + "mov x22, #0x79ff", + "movk x22, #0x509f, lsl #16", + "movk x22, #0x4413, lsl #32", + "movk x22, #0x3fd3, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldln2": { @@ -2277,15 +2277,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x39ef", - "movk x21, #0xfefa, lsl #16", - "movk x21, #0x2e42, lsl #32", - "movk x21, #0x3fe6, lsl #48", - "fmov d2, x21", + "mov x22, #0x39ef", + "movk x22, #0xfefa, lsl #16", + "movk x22, #0x2e42, lsl #32", + "movk x22, #0x3fe6, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldz": { @@ -2301,12 +2301,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov w21, #0x0", - "fmov d2, x21", + "mov w22, #0x0", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "f2xm1": { @@ -2384,13 +2384,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2444,8 +2443,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fptan": { @@ -2461,7 +2461,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", @@ -2516,14 +2515,15 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov x23, #0x3ff0000000000000", + "fmov d3, x23", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "str d3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fpatan": { @@ -2537,13 +2537,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v3.8b", "mov v1.8b, v2.8b", @@ -2597,8 +2596,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxtract": { @@ -2614,22 +2614,22 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", - "and x21, x21, #0x800fffffffffffff", - "orr x21, x21, #0x3ff0000000000000", - "fmov d3, x21", + "mov x23, v2.d[0]", + "and x24, x23, #0x7ff0000000000000", + "lsr x24, x24, #52", + "sub x24, x24, #0x3ff (1023)", + "scvtf d2, x24", + "and x23, x23, #0x800fffffffffffff", + "orr x23, x23, #0x3ff0000000000000", + "fmov d3, x23", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "str d3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fprem1": { @@ -2809,13 +2809,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov x20, #0x3ff0000000000000", "fmov d4, x20", @@ -2872,8 +2871,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsqrt": { @@ -2903,7 +2903,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", @@ -3009,12 +3008,13 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "frndint": { @@ -3312,10 +3312,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub dword [rax]": { @@ -4087,7 +4087,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 29, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -4113,15 +4113,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fild dword [rax]": { @@ -4137,12 +4136,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "ldr w22, [x4]", + "scvtf d2, w22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -4160,10 +4159,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist dword [rax]": { @@ -4196,10 +4195,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fld tword [rax]": { @@ -4242,10 +4241,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -4291,10 +4290,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcmovnb st0, st0": { @@ -5404,10 +5403,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub qword [rax]": { @@ -6360,10 +6359,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -6381,10 +6380,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fst qword [rax]": { @@ -6413,10 +6412,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "frstor [rax]": { @@ -6481,11 +6480,10 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6516,8 +6514,8 @@ "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #38]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6546,10 +6544,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldr q3, [x4, #48]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6578,10 +6576,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #58]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6610,10 +6608,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #68]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6642,10 +6640,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #78]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6674,10 +6672,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #88]", "and v2.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6706,10 +6704,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur d2, [x4, #98]", "ldr h3, [x4, #106]", "mov v2.h[4], v3.h[0]", @@ -6739,13 +6737,14 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w20, [x28, #1298]" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 327, + "ExpectedInstructionCount": 329, "Comment": [ "0xdd !11b /6" ], @@ -6754,8 +6753,10 @@ "ldrh w21, [x28, #1296]", "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", + "ldrb w22, [x28, #1019]", + "mov x0, x21", + "bfi x0, x22, #11, #3", + "mov x22, x0", "ldrb w23, [x28, #1016]", "ldrb w24, [x28, #1017]", "ldrb w25, [x28, #1018]", @@ -7075,8 +7076,8 @@ "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x25", + "strb w21, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -7388,7 +7389,7 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd8 /3" ], @@ -7404,17 +7405,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd9 /3" ], @@ -7430,17 +7430,16 @@ "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", - "strb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xda /3" ], @@ -7456,17 +7455,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdb /3" ], @@ -7482,17 +7480,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdc /3" ], @@ -7508,17 +7505,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdd /3" ], @@ -7534,17 +7530,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xde /3" ], @@ -7560,17 +7555,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdf /3" ], @@ -7586,13 +7580,12 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucom st0": { @@ -7822,10 +7815,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st1": { @@ -7855,10 +7848,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st2": { @@ -7888,10 +7881,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st3": { @@ -7921,10 +7914,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st4": { @@ -7954,10 +7947,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st5": { @@ -7987,10 +7980,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st6": { @@ -8020,10 +8013,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st7": { @@ -8053,10 +8046,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fiadd word [rax]": { @@ -8143,10 +8136,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub word [rax]": { @@ -8235,12 +8228,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st1": { @@ -8261,12 +8254,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "faddp st2": { @@ -8287,12 +8280,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st3": { @@ -8313,12 +8306,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st4": { @@ -8339,12 +8332,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st5": { @@ -8365,12 +8358,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st6": { @@ -8391,12 +8384,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st7": { @@ -8417,12 +8410,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st0": { @@ -8443,12 +8436,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st1": { @@ -8469,12 +8462,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fmulp st2": { @@ -8495,12 +8488,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st3": { @@ -8521,12 +8514,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st4": { @@ -8547,12 +8540,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st5": { @@ -8573,12 +8566,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st6": { @@ -8599,12 +8592,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st7": { @@ -8625,16 +8618,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fcompp": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 29, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -8660,15 +8653,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "db 0xde, 0xe0": { @@ -8691,12 +8683,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st1, st0": { @@ -8717,12 +8709,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubrp st2, st0": { @@ -8743,12 +8735,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st3, st0": { @@ -8769,12 +8761,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st4, st0": { @@ -8795,12 +8787,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st5, st0": { @@ -8821,12 +8813,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st6, st0": { @@ -8847,12 +8839,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st7, st0": { @@ -8873,12 +8865,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xe8": { @@ -8901,12 +8893,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st1, st0": { @@ -8927,12 +8919,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubp st2, st0": { @@ -8953,12 +8945,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st3, st0": { @@ -8979,12 +8971,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st4, st0": { @@ -9005,12 +8997,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st5, st0": { @@ -9031,12 +9023,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st6, st0": { @@ -9057,12 +9049,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st7, st0": { @@ -9083,12 +9075,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf0": { @@ -9111,12 +9103,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st1, st0": { @@ -9137,12 +9129,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivrp st2, st0": { @@ -9163,12 +9155,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st3, st0": { @@ -9189,12 +9181,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st4, st0": { @@ -9215,12 +9207,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st5, st0": { @@ -9241,12 +9233,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st6, st0": { @@ -9267,12 +9259,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st7, st0": { @@ -9293,12 +9285,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf8": { @@ -9321,12 +9313,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st1, st0": { @@ -9347,12 +9339,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivp st2, st0": { @@ -9373,12 +9365,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st3, st0": { @@ -9399,12 +9391,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st4, st0": { @@ -9425,12 +9417,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st5, st0": { @@ -9451,12 +9443,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st6, st0": { @@ -9477,12 +9469,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st7, st0": { @@ -9503,12 +9495,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fild word [rax]": { @@ -9524,13 +9516,13 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, x21", + "ldrh w22, [x4]", + "sxth x22, w22", + "scvtf d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -9548,10 +9540,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist word [rax]": { @@ -9584,10 +9576,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fbld tword [rax]": { @@ -9603,7 +9595,6 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -9661,7 +9652,8 @@ "ldr x30, [sp], #16", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -9735,10 +9727,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "ffreep st0": { @@ -9878,10 +9870,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st1": { @@ -9905,10 +9897,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st2": { @@ -9932,10 +9924,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st3": { @@ -9959,10 +9951,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st4": { @@ -9986,10 +9978,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st5": { @@ -10013,10 +10005,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st6": { @@ -10040,10 +10032,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomip st7": { @@ -10067,10 +10059,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st0": { @@ -10094,10 +10086,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st1": { @@ -10121,10 +10113,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st2": { @@ -10148,10 +10140,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st3": { @@ -10175,10 +10167,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st4": { @@ -10202,10 +10194,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st5": { @@ -10229,10 +10221,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st6": { @@ -10256,10 +10248,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomip st7": { @@ -10283,10 +10275,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] } } diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 649534976..ae8d6ffd8 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -104,35 +104,39 @@ ] }, "add al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -140,8 +144,8 @@ "ExpectedInstructionCount": 3, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -220,18 +224,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr w7, w7, w5", - "mov x26, x7", - "tst w7, w7" + "orr w26, w7, w5", + "tst w26, w26", + "mov x7, x26" ] }, "or rbx, rcx": { "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr x7, x7, x5", - "mov x26, x7", - "tst x7, x7" + "orr x26, x7, x5", + "tst x26, x26", + "mov x7, x26" ] }, "db 0x0A, 0xcb": { @@ -265,9 +269,9 @@ "or ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w5, w5, w7", - "mov x26, x5", - "tst w5, w5" + "orr w26, w5, w7", + "tst w26, w26", + "mov x5, x26" ] }, "db 0x48, 0x0B, 0xcb": { @@ -277,9 +281,9 @@ "or rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr x5, x5, x7", - "mov x26, x5", - "tst x5, x5" + "orr x26, x5, x7", + "tst x26, x26", + "mov x5, x26" ] }, "or al, 1": { @@ -304,18 +308,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "or al, -1": { @@ -341,9 +345,9 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "orr w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -1": { @@ -351,9 +355,9 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "orr x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "adc bl, cl": { @@ -497,10 +501,9 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 19, "Comment": "0x14", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -515,15 +518,17 @@ "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 19, "Comment": "0x15", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -538,8 +543,11 @@ "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", - "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #16", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "adc eax, 1": { @@ -547,8 +555,8 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -557,8 +565,8 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -687,8 +695,8 @@ "sbcs w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x7, x26" ] }, "sbb rbx, rcx": { @@ -702,8 +710,8 @@ "sbcs x26, x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x7, x26" ] }, "db 0x1A, 0xcb": { @@ -774,8 +782,8 @@ "sbcs w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x5, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x5, x26" ] }, "db 0x48, 0x1B, 0xcb": { @@ -792,15 +800,14 @@ "sbcs x26, x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x5, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x5, x26" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 18, "Comment": "0x1C", "ExpectedArm64ASM": [ - "mov x27, x4", "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -814,15 +821,17 @@ "bic w20, w20, w26", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 18, "Comment": "0x1D", "ExpectedArm64ASM": [ - "mov x27, x4", "uxth w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -836,8 +845,11 @@ "bic w20, w20, w26", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", - "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #16", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "sbb eax, 1": { @@ -845,15 +857,15 @@ "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sbb rax, 1": { @@ -861,15 +873,15 @@ "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sbb al, -1": { @@ -929,8 +941,8 @@ "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "sbb rax, -1": { @@ -945,8 +957,8 @@ "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "and bl, cl": { @@ -1135,8 +1147,8 @@ "subs w26, w7, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x7, x26" ] }, "sub rbx, rcx": { @@ -1147,8 +1159,8 @@ "subs x26, x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x7, x26" ] }, "db 0x2A, 0xcb": { @@ -1196,8 +1208,8 @@ "subs w26, w5, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x5, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x5, x26" ] }, "db 0x48, 0x2B, 0xcb": { @@ -1211,62 +1223,66 @@ "subs x26, x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x5, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x5, x26" ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 11, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 11, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #16", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "sub eax, 1": { "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sub rax, 1": { "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sub al, -1": { @@ -1308,8 +1324,8 @@ "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "sub rax, -1": { @@ -1320,8 +1336,8 @@ "adds x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "xor bl, cl": { @@ -1346,18 +1362,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor w7, w7, w5", - "mov x26, x7", - "tst w7, w7" + "eor w26, w7, w5", + "tst w26, w26", + "mov x7, x26" ] }, "xor rbx, rcx": { "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor x7, x7, x5", - "mov x26, x7", - "tst x7, x7" + "eor x26, x7, x5", + "tst x26, x26", + "mov x7, x26" ] }, "db 0x32, 0xcb": { @@ -1391,9 +1407,9 @@ "xor ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w5, w5, w7", - "mov x26, x5", - "tst w5, w5" + "eor w26, w5, w7", + "tst w26, w26", + "mov x5, x26" ] }, "db 0x48, 0x33, 0xcb": { @@ -1403,9 +1419,9 @@ "xor rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor x5, x5, x7", - "mov x26, x5", - "tst x5, x5" + "eor x26, x5, x7", + "tst x26, x26", + "mov x5, x26" ] }, "xor al, 1": { @@ -1430,18 +1446,18 @@ "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "cmp bl, cl": { @@ -1480,9 +1496,9 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "eor w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -1": { @@ -1490,9 +1506,9 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "eor x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "cmp bx, cx": { @@ -1595,13 +1611,13 @@ "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp ax, 1": { @@ -1609,35 +1625,35 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp eax, 1": { "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp rax, 1": { "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp al, -1": { @@ -1908,14 +1924,13 @@ ] }, "xchg bl, cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x86", "ExpectedArm64ASM": [ "mov x20, x5", "bfxil x20, x7, #0, #8", - "mov x21, x5", - "mov x5, x20", - "bfxil x7, x21, #0, #8" + "bfxil x7, x5, #0, #8", + "mov x5, x20" ] }, "xchg [rax], cl": { @@ -1927,14 +1942,13 @@ ] }, "xchg bx, cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x87", "ExpectedArm64ASM": [ "mov x20, x5", "bfxil x20, x7, #0, #16", - "mov x21, x5", - "mov x5, x20", - "bfxil x7, x21, #0, #16" + "bfxil x7, x5, #0, #16", + "mov x5, x20" ] }, "xchg [rax], cx": { @@ -1946,13 +1960,12 @@ ] }, "xchg ebx, ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x87", "ExpectedArm64ASM": [ "mov w20, w7", - "mov x21, x5", - "mov x5, x20", - "mov w7, w21" + "mov w7, w5", + "mov x5, x20" ] }, "xchg [rax], ecx": { @@ -1966,9 +1979,9 @@ "ExpectedInstructionCount": 3, "Comment": "0x87", "ExpectedArm64ASM": [ - "mov x20, x5", - "mov x5, x7", - "mov x7, x20" + "mov x20, x7", + "mov x7, x5", + "mov x5, x20" ] }, "xchg [rax], rcx": { @@ -2431,24 +2444,22 @@ ] }, "xchg ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x90", "ExpectedArm64ASM": [ "mov x20, x7", "bfxil x20, x4, #0, #16", - "mov x21, x7", - "mov x7, x20", - "bfxil x4, x21, #0, #16" + "bfxil x4, x7, #0, #16", + "mov x7, x20" ] }, "xchg eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x90", "ExpectedArm64ASM": [ "mov w20, w4", - "mov x21, x7", - "mov x7, x20", - "mov w4, w21" + "mov w4, w7", + "mov x7, x20" ] }, "xchg rax, rbx": { @@ -2630,26 +2641,26 @@ "strb w21, [x28, #985]", "ubfx w21, w27, #10, #1", "sub x21, x22, x21, lsl #1", - "strb w21, [x28, #986]", - "ubfx x21, x27, #11, #1", - "orr w20, w20, w21, lsl #28", - "ubfx w21, w27, #12, #1", - "strb w21, [x28, #988]", - "ubfx w21, w27, #14, #1", - "strb w21, [x28, #990]", - "ubfx w21, w27, #16, #1", - "strb w21, [x28, #992]", - "ubfx w21, w27, #17, #1", - "strb w21, [x28, #993]", - "ubfx w21, w27, #18, #1", - "strb w21, [x28, #994]", - "ubfx w21, w27, #19, #1", - "strb w21, [x28, #995]", - "ubfx w21, w27, #20, #1", - "strb w21, [x28, #996]", - "ubfx w21, w27, #21, #1", - "strb w21, [x28, #997]", - "msr nzcv, x20" + "ubfx x22, x27, #11, #1", + "orr w20, w20, w22, lsl #28", + "ubfx w22, w27, #12, #1", + "strb w22, [x28, #988]", + "ubfx w22, w27, #14, #1", + "strb w22, [x28, #990]", + "ubfx w22, w27, #16, #1", + "strb w22, [x28, #992]", + "ubfx w22, w27, #17, #1", + "strb w22, [x28, #993]", + "ubfx w22, w27, #18, #1", + "strb w22, [x28, #994]", + "ubfx w22, w27, #19, #1", + "strb w22, [x28, #995]", + "ubfx w22, w27, #20, #1", + "strb w22, [x28, #996]", + "ubfx w22, w27, #21, #1", + "strb w22, [x28, #997]", + "msr nzcv, x20", + "strb w21, [x28, #986]" ] }, "sahf": { @@ -3236,10 +3247,10 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x74", + "cbz x5, #+0x70", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3260,21 +3271,20 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #24", + "lsl w0, w27, #24", "cmp w0, w26, lsl #24", - "sub w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x74", + "cbz x5, #+0x70", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3295,21 +3305,20 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #16", + "lsl w0, w27, #16", "cmp w0, w26, lsl #16", - "sub w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3330,19 +3339,18 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3363,19 +3371,18 @@ "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs x26, x21, x26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x27, x26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x74", + "cbz x5, #+0x70", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3396,21 +3403,20 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #24", + "lsl w0, w27, #24", "cmp w0, w26, lsl #24", - "sub w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 28, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x74", + "cbz x5, #+0x70", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3431,21 +3437,20 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "lsl w0, w21, #16", + "lsl w0, w27, #16", "cmp w0, w26, lsl #16", - "sub w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3466,19 +3471,18 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs w26, w21, w26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w27, w26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 26, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x6c", + "cbz x5, #+0x68", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3499,12 +3503,11 @@ "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", "eor w20, w27, w26", - "mov x21, x27", - "mov x27, x20", - "subs x26, x21, x26", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x27, x26", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x27, x20" ] }, "test al, 1": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index c5a7dbfb3..78e34df22 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -16,15 +16,17 @@ ], "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #8" + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "mov x27, x4", + "mov x4, x20" ] }, "or al, 1": { @@ -37,10 +39,9 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ - "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", "add w21, w4, w20", @@ -55,15 +56,17 @@ "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ - "mov x27, x4", "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", @@ -77,8 +80,11 @@ "bic w20, w20, w26", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "and al, 1": { @@ -91,18 +97,20 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x4", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x21" ] }, "xor al, 1": { @@ -119,13 +127,13 @@ "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "add al, -1": { @@ -242,23 +250,25 @@ ] }, "add ax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x100 (256)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -266,8 +276,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -275,18 +285,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0x100", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x100", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0x100", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x100", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, 256": { @@ -294,8 +304,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -304,8 +314,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -314,15 +324,15 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sbb rax, 256": { @@ -330,15 +340,15 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "and eax, 256": { @@ -361,76 +371,78 @@ "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sub rax, 256": { "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "xor eax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0x100", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x100", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0x100", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x100", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, 256": { "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp rax, 256": { "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "add ax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, -256": { @@ -438,8 +450,8 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "adds w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -447,8 +459,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x100 (256)", + "mov x27, x4", "mov x4, x26" ] }, @@ -456,18 +468,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0xffffff00", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0xffffff00", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0xffffffffffffff00", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0xffffffffffffff00", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, -256": { @@ -475,8 +487,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -485,8 +497,8 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -495,15 +507,15 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sbb rax, -256": { @@ -511,15 +523,15 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "and eax, -256": { @@ -543,42 +555,42 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sub rax, -256": { "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "xor eax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0xffffff00", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0xffffff00", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -256": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0xffffffffffffff00", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0xffffffffffffff00", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, -256": { @@ -586,42 +598,44 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x27, x4", "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp rax, -256": { "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "add ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, #0x1 (1)", - "bfxil x4, x26, #0, #16" + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "mov x27, x4", + "mov x4, x20" ] }, "add eax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds w26, w4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -629,8 +643,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x27, x4", "adds x26, x4, #0x1 (1)", + "mov x27, x4", "mov x4, x26" ] }, @@ -638,18 +652,18 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ - "orr w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ - "orr x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, 1": { @@ -657,8 +671,8 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs w26, w4, w20", + "mov x27, x4", "mov x4, x26" ] }, @@ -667,8 +681,8 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "adcs x26, x4, x20", + "mov x27, x4", "mov x4, x26" ] }, @@ -677,15 +691,15 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sbb rax, 1": { @@ -693,15 +707,15 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mov x27, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "and eax, 1": { @@ -724,64 +738,64 @@ "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "sub rax, 1": { "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4", + "mov x4, x26" ] }, "xor eax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ - "eor w4, w4, #0x1", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, #0x1", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, 1": { "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ - "eor x4, x4, #0x1", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, #0x1", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, 1": { "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "cmp rax, 1": { "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov x27, x4", "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x4" ] }, "add ax, -1": { @@ -820,9 +834,9 @@ "Comment": "GROUP1 0x83 /-1", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "orr w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "orr w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "or rax, -1": { @@ -830,9 +844,9 @@ "Comment": "GROUP1 0x83 /-1", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "orr x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "orr x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "adc eax, -1": { @@ -867,8 +881,8 @@ "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "sbb rax, -1": { @@ -883,8 +897,8 @@ "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "and eax, -1": { @@ -914,8 +928,8 @@ "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "sub rax, -1": { @@ -926,8 +940,8 @@ "adds x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x4, x26" ] }, "xor eax, -1": { @@ -935,9 +949,9 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "eor w4, w4, w20", - "mov x26, x4", - "tst w4, w4" + "eor w26, w4, w20", + "tst w26, w26", + "mov x4, x26" ] }, "xor rax, -1": { @@ -945,9 +959,9 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "eor x4, x4, x20", - "mov x26, x4", - "tst x4, x4" + "eor x26, x4, x20", + "tst x26, x26", + "mov x4, x26" ] }, "cmp eax, -1": { @@ -1622,8 +1636,8 @@ "eor x21, x20, x4", "lsr x21, x21, #63", "bfi w22, w21, #28, #1", - "mov x4, x20", - "msr nzcv, x22" + "msr nzcv, x22", + "mov x4, x20" ] }, "rcr ax, 1": { @@ -2405,16 +2419,18 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ - "mov x27, x7", "cmp wzr, w7, lsl #24", "neg w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "bfxil x7, x26, #0, #8", - "msr nzcv, x20" + "mov x21, x7", + "bfxil x21, x26, #0, #8", + "msr nzcv, x20", + "mov x27, x7", + "mov x7, x21" ] }, "mul bl": { @@ -2542,40 +2558,42 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "cmp wzr, w7, lsl #16", "neg w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "bfxil x7, x26, #0, #16", - "msr nzcv, x20" + "mov x21, x7", + "bfxil x21, x26, #0, #16", + "msr nzcv, x20", + "mov x27, x7", + "mov x7, x21" ] }, "neg ebx": { "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "negs w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x7", + "mov x7, x26" ] }, "neg rbx": { "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x27, x7", "negs x26, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x26", - "msr nzcv, x20" + "msr nzcv, x20", + "mov x27, x7", + "mov x7, x26" ] }, "mul bx": { @@ -2611,9 +2629,9 @@ "ExpectedArm64ASM": [ "mul x20, x7, x4", "umulh x6, x7, x4", - "mov x4, x20", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmn xzr, #0, #nzCV, eq", + "mov x4, x20" ] }, "imul bx": { @@ -2851,12 +2869,12 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "inc rax": { @@ -2864,12 +2882,12 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds x26, x4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "dec ax": { @@ -2893,12 +2911,12 @@ "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "dec rax": { @@ -2906,12 +2924,12 @@ "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs x26, x4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "push ax": { diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index bc6531b9c..0b9b669a1 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -204,12 +204,12 @@ "Comment": "0x40", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "dec ax": { @@ -247,12 +247,12 @@ "Comment": "0x48", "ExpectedArm64ASM": [ "cset w20, hs", - "mov x27, x4", "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", - "mov x4, x26", - "msr nzcv, x21" + "msr nzcv, x21", + "mov x27, x4", + "mov x4, x26" ] }, "pusha": { diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index e678f584b..3f41731af 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -1389,21 +1389,21 @@ "strh w20, [x4, #2]", "ldrb w20, [x28, #1298]", "strb w20, [x4, #4]", - "ldr q2, [x28, #1040]", + "ldr d2, [x28, #1040]", "str q2, [x4, #32]", - "ldr q2, [x28, #1056]", + "ldr d2, [x28, #1056]", "str q2, [x4, #48]", - "ldr q2, [x28, #1072]", + "ldr d2, [x28, #1072]", "str q2, [x4, #64]", - "ldr q2, [x28, #1088]", + "ldr d2, [x28, #1088]", "str q2, [x4, #80]", - "ldr q2, [x28, #1104]", + "ldr d2, [x28, #1104]", "str q2, [x4, #96]", - "ldr q2, [x28, #1120]", + "ldr d2, [x28, #1120]", "str q2, [x4, #112]", - "ldr q2, [x28, #1136]", + "ldr d2, [x28, #1136]", "str q2, [x4, #128]", - "ldr q2, [x28, #1152]", + "ldr d2, [x28, #1152]", "str q2, [x4, #144]", "str q16, [x4, #160]", "str q17, [x4, #176]", @@ -1464,23 +1464,14 @@ "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1298]", "ldr q2, [x4, #32]", - "str q2, [x28, #1040]", - "ldr q2, [x4, #48]", - "str q2, [x28, #1056]", - "ldr q2, [x4, #64]", - "str q2, [x28, #1072]", - "ldr q2, [x4, #80]", - "str q2, [x28, #1088]", - "ldr q2, [x4, #96]", - "str q2, [x28, #1104]", - "ldr q2, [x4, #112]", - "str q2, [x28, #1120]", - "ldr q2, [x4, #128]", - "str q2, [x28, #1136]", - "ldr q2, [x4, #144]", - "str q2, [x28, #1152]", + "ldr q3, [x4, #48]", + "ldr q4, [x4, #64]", + "ldr q5, [x4, #80]", + "ldr q6, [x4, #96]", + "ldr q7, [x4, #112]", + "ldr q8, [x4, #128]", + "ldr q9, [x4, #144]", "ldr q16, [x4, #160]", "ldr q17, [x4, #176]", "ldr q18, [x4, #192]", @@ -1497,15 +1488,24 @@ "ldr q29, [x4, #368]", "ldr q30, [x4, #384]", "ldr q31, [x4, #400]", - "ldr w20, [x4, #24]", - "ubfx w20, w20, #13, #3", - "rbit w1, w20", + "ldr w21, [x4, #24]", + "ubfx w21, w21, #13, #3", + "rbit w1, w21", "lsr w1, w1, #30", "mrs x0, fpcr", "bfi x0, x1, #22, #2", - "lsr x1, x20, #2", + "lsr x1, x21, #2", "bfi x0, x1, #24, #1", - "msr fpcr, x0" + "msr fpcr, x0", + "strb w20, [x28, #1298]", + "str d9, [x28, #1152]", + "str d8, [x28, #1136]", + "str d7, [x28, #1120]", + "str d6, [x28, #1104]", + "str d5, [x28, #1088]", + "str d4, [x28, #1072]", + "str d3, [x28, #1056]", + "str d2, [x28, #1040]" ] }, "rdgsbase eax": { @@ -1603,21 +1603,21 @@ "strh w20, [x4, #2]", "ldrb w20, [x28, #1298]", "strb w20, [x4, #4]", - "ldr q2, [x28, #1040]", + "ldr d2, [x28, #1040]", "str q2, [x4, #32]", - "ldr q2, [x28, #1056]", + "ldr d2, [x28, #1056]", "str q2, [x4, #48]", - "ldr q2, [x28, #1072]", + "ldr d2, [x28, #1072]", "str q2, [x4, #64]", - "ldr q2, [x28, #1088]", + "ldr d2, [x28, #1088]", "str q2, [x4, #80]", - "ldr q2, [x28, #1104]", + "ldr d2, [x28, #1104]", "str q2, [x4, #96]", - "ldr q2, [x28, #1120]", + "ldr d2, [x28, #1120]", "str q2, [x4, #112]", - "ldr q2, [x28, #1136]", + "ldr d2, [x28, #1136]", "str q2, [x4, #128]", - "ldr q2, [x28, #1152]", + "ldr d2, [x28, #1152]", "str q2, [x4, #144]", "ubfx x20, x4, #1, #1", "cbnz x20, #+0x8", @@ -1683,23 +1683,23 @@ "strb w23, [x28, #1018]", "strb w20, [x28, #1022]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1298]", "ldr q2, [x4, #32]", - "str q2, [x28, #1040]", - "ldr q2, [x4, #48]", - "str q2, [x28, #1056]", - "ldr q2, [x4, #64]", - "str q2, [x28, #1072]", - "ldr q2, [x4, #80]", - "str q2, [x28, #1088]", - "ldr q2, [x4, #96]", - "str q2, [x28, #1104]", - "ldr q2, [x4, #112]", - "str q2, [x28, #1120]", - "ldr q2, [x4, #128]", - "str q2, [x28, #1136]", - "ldr q2, [x4, #144]", - "str q2, [x28, #1152]", + "ldr q3, [x4, #48]", + "ldr q4, [x4, #64]", + "ldr q5, [x4, #80]", + "ldr q6, [x4, #96]", + "ldr q7, [x4, #112]", + "ldr q8, [x4, #128]", + "ldr q9, [x4, #144]", + "strb w20, [x28, #1298]", + "str d9, [x28, #1152]", + "str d8, [x28, #1136]", + "str d7, [x28, #1120]", + "str d6, [x28, #1104]", + "str d5, [x28, #1088]", + "str d4, [x28, #1072]", + "str d3, [x28, #1056]", + "str d2, [x28, #1040]", "b #+0x4c", "mov w20, #0x0", "mov w21, #0x37f", @@ -1709,16 +1709,16 @@ "strb w20, [x28, #1017]", "strb w20, [x28, #1018]", "strb w20, [x28, #1022]", - "strb w20, [x28, #1298]", "movi v2.2d, #0x0", - "str q2, [x28, #1040]", - "str q2, [x28, #1056]", - "str q2, [x28, #1072]", - "str q2, [x28, #1088]", - "str q2, [x28, #1104]", - "str q2, [x28, #1120]", - "str q2, [x28, #1136]", - "str q2, [x28, #1152]", + "strb w20, [x28, #1298]", + "str d2, [x28, #1152]", + "str d2, [x28, #1136]", + "str d2, [x28, #1120]", + "str d2, [x28, #1104]", + "str d2, [x28, #1088]", + "str d2, [x28, #1072]", + "str d2, [x28, #1056]", + "str d2, [x28, #1040]", "ldr x20, [x4, #512]", "ubfx x20, x20, #1, #1", "cbnz x20, #+0x8", @@ -1740,22 +1740,22 @@ "ldr q30, [x4, #384]", "ldr q31, [x4, #400]", "b #+0x44", - "movi v16.2d, #0x0", - "mov v17.16b, v16.16b", - "mov v18.16b, v16.16b", - "mov v19.16b, v16.16b", - "mov v20.16b, v16.16b", - "mov v21.16b, v16.16b", - "mov v22.16b, v16.16b", - "mov v23.16b, v16.16b", - "mov v24.16b, v16.16b", - "mov v25.16b, v16.16b", - "mov v26.16b, v16.16b", - "mov v27.16b, v16.16b", - "mov v28.16b, v16.16b", - "mov v29.16b, v16.16b", - "mov v30.16b, v16.16b", - "mov v31.16b, v16.16b", + "movi v31.2d, #0x0", + "mov v30.16b, v31.16b", + "mov v29.16b, v31.16b", + "mov v28.16b, v31.16b", + "mov v27.16b, v31.16b", + "mov v26.16b, v31.16b", + "mov v25.16b, v31.16b", + "mov v24.16b, v31.16b", + "mov v23.16b, v31.16b", + "mov v22.16b, v31.16b", + "mov v21.16b, v31.16b", + "mov v20.16b, v31.16b", + "mov v19.16b, v31.16b", + "mov v18.16b, v31.16b", + "mov v17.16b, v31.16b", + "mov v16.16b, v31.16b", "ldr x20, [x4, #512]", "ubfx x20, x20, #1, #2", "cbnz x20, #+0x8", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index e8913792d..0d1a7d5d5 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -3198,9 +3198,9 @@ "Map 2 0b00 0xf2 32-bit" ], "ExpectedArm64ASM": [ - "bic w4, w5, w7", - "mov x26, x4", - "tst w4, w4" + "bic w26, w5, w7", + "tst w26, w26", + "mov x4, x26" ] }, "andn rax, rbx, rcx": { @@ -3209,9 +3209,9 @@ "Map 2 0b00 0xf2 64-bit" ], "ExpectedArm64ASM": [ - "bic x4, x5, x7", - "mov x26, x4", - "tst x4, x4" + "bic x26, x5, x7", + "tst x26, x26", + "mov x4, x26" ] }, "bzhi eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 87f7f36ea..47981e80e 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -310,10 +310,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub dword [rax]": { @@ -1831,10 +1831,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st1": { @@ -1892,10 +1892,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st2": { @@ -1953,10 +1953,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st3": { @@ -2014,10 +2014,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st4": { @@ -2075,10 +2075,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st5": { @@ -2136,10 +2136,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st6": { @@ -2197,10 +2197,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st7": { @@ -2258,10 +2258,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub st0, st0": { @@ -3809,10 +3809,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fst dword [rax]": { @@ -3893,10 +3893,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fldenv [rax]": { @@ -3951,8 +3951,8 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1298]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w20, [x28, #1298]" ] }, "fldcw [rax]": { @@ -4064,10 +4064,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st1": { @@ -4087,10 +4087,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st2": { @@ -4110,10 +4110,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st3": { @@ -4133,10 +4133,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st4": { @@ -4156,10 +4156,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st5": { @@ -4179,10 +4179,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st6": { @@ -4202,10 +4202,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st7": { @@ -4225,10 +4225,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxch st0, st0": { @@ -4529,11 +4529,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2672]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2t": { @@ -4549,11 +4549,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2688]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2e": { @@ -4569,11 +4569,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2704]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldpi": { @@ -4589,11 +4589,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2720]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldlg2": { @@ -4609,11 +4609,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2736]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldln2": { @@ -4629,11 +4629,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x28, #2752]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldz": { @@ -4649,11 +4649,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "movi v2.2d, #0x0", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "f2xm1": { @@ -4708,13 +4708,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4746,8 +4745,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fptan": { @@ -4763,7 +4763,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -4796,12 +4795,13 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "ldr q3, [x28, #2672]", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q3, [x0, #1040]" + "str q3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fpatan": { @@ -4815,13 +4815,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -4853,8 +4852,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxtract": { @@ -4870,7 +4870,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -4933,7 +4932,8 @@ "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fprem1": { @@ -5069,13 +5069,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr q3, [x0, #1040]", "ldr q4, [x28, #2672]", "mrs x0, nzcv", @@ -5138,8 +5137,9 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsqrt": { @@ -5196,7 +5196,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", @@ -5256,12 +5255,13 @@ "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "frndint": { @@ -5736,10 +5736,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub dword [rax]": { @@ -6731,7 +6731,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -6785,19 +6785,18 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /5" ], @@ -6809,33 +6808,34 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "mov w22, #0x0", - "sxtw x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", + "ldr w22, [x4]", + "mov w23, #0x0", + "sxtw x22, w22", + "mrs x24, nzcv", + "cmp x22, #0x0 (0)", + "mov w25, #0x8000", + "csel x25, x25, xzr, lt", + "cneg x22, x22, mi", + "mov w30, #0x3f", "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", + "clz x18, x22", + "sub x18, x0, x18", + "sub x30, x30, x18", + "lsl x18, x22, x30", + "mov w23, #0x403e", + "sub x23, x23, x30", + "mov w30, #0x0", + "cmp x22, #0x0 (0)", + "csel x22, x30, x23, eq", + "orr x22, x25, x22", + "fmov d2, x18", + "fmov d3, x22", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x24", + "strb w21, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -6878,10 +6878,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist dword [rax]": { @@ -6962,10 +6962,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fld tword [rax]": { @@ -6982,10 +6982,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -7004,10 +7004,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcmovnb st0, st0": { @@ -8860,10 +8860,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub qword [rax]": { @@ -11459,10 +11459,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -11505,10 +11505,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fst qword [rax]": { @@ -11589,10 +11589,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "frstor [rax]": { @@ -11647,63 +11647,63 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #38]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldr q3, [x4, #48]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #58]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #68]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #78]", "and v3.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #88]", "and v2.16b, v3.16b, v2.16b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur d2, [x4, #98]", "ldr h3, [x4, #106]", "mov v2.h[4], v3.h[0]", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w20, [x28, #1298]" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Comment": [ "0xdd !11b /6" ], @@ -11712,8 +11712,10 @@ "ldrh w21, [x28, #1296]", "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", + "ldrb w22, [x28, #1019]", + "mov x0, x21", + "bfi x0, x22, #11, #3", + "mov x22, x0", "ldrb w23, [x28, #1016]", "ldrb w24, [x28, #1017]", "ldrb w25, [x28, #1018]", @@ -11817,8 +11819,8 @@ "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x25", + "strb w21, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -12130,7 +12132,7 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd8 /3" ], @@ -12146,17 +12148,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd9 /3" ], @@ -12172,17 +12173,16 @@ "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", - "strb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xda /3" ], @@ -12198,17 +12198,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdb /3" ], @@ -12224,17 +12223,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdc /3" ], @@ -12250,17 +12248,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdd /3" ], @@ -12276,17 +12273,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xde /3" ], @@ -12302,17 +12298,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdf /3" ], @@ -12328,13 +12323,12 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucom st0": { @@ -12816,10 +12810,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st1": { @@ -12877,10 +12871,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st2": { @@ -12938,10 +12932,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st3": { @@ -12999,10 +12993,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st4": { @@ -13060,10 +13054,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st5": { @@ -13121,10 +13115,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st6": { @@ -13182,10 +13176,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st7": { @@ -13243,10 +13237,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fiadd word [rax]": { @@ -13547,10 +13541,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub word [rax]": { @@ -13884,12 +13878,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st1": { @@ -13939,12 +13933,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "faddp st2": { @@ -13994,12 +13988,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st3": { @@ -14049,12 +14043,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st4": { @@ -14104,12 +14098,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st5": { @@ -14159,12 +14153,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st6": { @@ -14214,12 +14208,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st7": { @@ -14269,12 +14263,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st0": { @@ -14324,12 +14318,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st1": { @@ -14379,12 +14373,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fmulp st2": { @@ -14434,12 +14428,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st3": { @@ -14489,12 +14483,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st4": { @@ -14544,12 +14538,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st5": { @@ -14599,12 +14593,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st6": { @@ -14654,12 +14648,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st7": { @@ -14709,16 +14703,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fcompp": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 57, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -14772,15 +14766,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "db 0xde, 0xe0": { @@ -14832,12 +14825,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st1, st0": { @@ -14887,12 +14880,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubrp st2, st0": { @@ -14942,12 +14935,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st3, st0": { @@ -14997,12 +14990,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st4, st0": { @@ -15052,12 +15045,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st5, st0": { @@ -15107,12 +15100,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st6, st0": { @@ -15162,12 +15155,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st7, st0": { @@ -15217,12 +15210,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xe8": { @@ -15274,12 +15267,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st1, st0": { @@ -15329,12 +15322,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubp st2, st0": { @@ -15384,12 +15377,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st3, st0": { @@ -15439,12 +15432,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st4, st0": { @@ -15494,12 +15487,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st5, st0": { @@ -15549,12 +15542,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st6, st0": { @@ -15604,12 +15597,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st7, st0": { @@ -15659,12 +15652,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf0": { @@ -15716,12 +15709,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st1, st0": { @@ -15771,12 +15764,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivrp st2, st0": { @@ -15826,12 +15819,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st3, st0": { @@ -15881,12 +15874,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st4, st0": { @@ -15936,12 +15929,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st5, st0": { @@ -15991,12 +15984,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st6, st0": { @@ -16046,12 +16039,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st7, st0": { @@ -16101,12 +16094,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf8": { @@ -16158,12 +16151,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st1, st0": { @@ -16213,12 +16206,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivp st2, st0": { @@ -16268,12 +16261,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st3, st0": { @@ -16323,12 +16316,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st4, st0": { @@ -16378,12 +16371,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st5, st0": { @@ -16433,12 +16426,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st6, st0": { @@ -16488,12 +16481,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st7, st0": { @@ -16543,16 +16536,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fild word [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /0" ], @@ -16564,33 +16557,34 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "mov w22, #0x0", - "sxth x21, w21", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", - "cneg x21, x21, mi", - "mov w25, #0x3f", + "ldrh w22, [x4]", + "mov w23, #0x0", + "sxth x22, w22", + "mrs x24, nzcv", + "cmp x22, #0x0 (0)", + "mov w25, #0x8000", + "csel x25, x25, xzr, lt", + "cneg x22, x22, mi", + "mov w30, #0x3f", "mov x0, #0x3f", - "clz x30, x21", - "sub x30, x0, x30", - "sub x25, x25, x30", - "lsl x30, x21, x25", - "mov w18, #0x403e", - "sub x25, x18, x25", - "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x30", - "fmov d3, x21", + "clz x18, x22", + "sub x18, x0, x18", + "sub x30, x30, x18", + "lsl x18, x22, x30", + "mov w23, #0x403e", + "sub x23, x23, x30", + "mov w30, #0x0", + "cmp x22, #0x0 (0)", + "csel x22, x30, x23, eq", + "orr x22, x25, x22", + "fmov d2, x18", + "fmov d3, x22", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x24", + "strb w21, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -16633,10 +16627,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist word [rax]": { @@ -16717,10 +16711,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fbld tword [rax]": { @@ -16736,7 +16730,6 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -16768,7 +16761,8 @@ "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #1040]" + "str q2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -16815,10 +16809,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "ffreep st0": { @@ -16990,11 +16984,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st1": { @@ -17050,11 +17044,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w21, [x28, #1298]" ] }, "fucomip st2": { @@ -17110,11 +17104,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st3": { @@ -17170,11 +17164,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st4": { @@ -17230,11 +17224,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st5": { @@ -17290,11 +17284,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st6": { @@ -17350,11 +17344,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st7": { @@ -17410,11 +17404,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st0": { @@ -17470,11 +17464,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st1": { @@ -17530,11 +17524,11 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w21, [x28, #1298]" ] }, "fcomip st2": { @@ -17590,11 +17584,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st3": { @@ -17650,11 +17644,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st4": { @@ -17710,11 +17704,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st5": { @@ -17770,11 +17764,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st6": { @@ -17830,11 +17824,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st7": { @@ -17890,11 +17884,11 @@ "ldrb w21, [x28, #1298]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] } } diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index e8de0d876..222e98327 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -96,10 +96,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub dword [rax]": { @@ -690,10 +690,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st1": { @@ -724,10 +724,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st2": { @@ -758,10 +758,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st3": { @@ -792,10 +792,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st4": { @@ -826,10 +826,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st5": { @@ -860,10 +860,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st6": { @@ -894,10 +894,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcomp st0, st7": { @@ -928,10 +928,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub st0, st0": { @@ -1525,10 +1525,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fst dword [rax]": { @@ -1559,10 +1559,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fldenv [rax]": { @@ -1625,8 +1625,8 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1298]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w20, [x28, #1298]" ] }, "fldcw [rax]": { @@ -1746,10 +1746,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st1": { @@ -1769,10 +1769,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st2": { @@ -1792,10 +1792,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st3": { @@ -1815,10 +1815,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st4": { @@ -1838,10 +1838,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st5": { @@ -1861,10 +1861,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st6": { @@ -1884,10 +1884,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fld st7": { @@ -1907,10 +1907,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxch st0, st0": { @@ -2178,12 +2178,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x3ff0000000000000", - "fmov d2, x21", + "mov x22, #0x3ff0000000000000", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2t": { @@ -2199,15 +2199,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0xa372", - "movk x21, #0x979, lsl #16", - "movk x21, #0x934f, lsl #32", - "movk x21, #0x400a, lsl #48", - "fmov d2, x21", + "mov x22, #0xa372", + "movk x22, #0x979, lsl #16", + "movk x22, #0x934f, lsl #32", + "movk x22, #0x400a, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldl2e": { @@ -2223,15 +2223,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x82fe", - "movk x21, #0x652b, lsl #16", - "movk x21, #0x1547, lsl #32", - "movk x21, #0x3ff7, lsl #48", - "fmov d2, x21", + "mov x22, #0x82fe", + "movk x22, #0x652b, lsl #16", + "movk x22, #0x1547, lsl #32", + "movk x22, #0x3ff7, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldpi": { @@ -2247,15 +2247,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x2d18", - "movk x21, #0x5444, lsl #16", - "movk x21, #0x21fb, lsl #32", - "movk x21, #0x4009, lsl #48", - "fmov d2, x21", + "mov x22, #0x2d18", + "movk x22, #0x5444, lsl #16", + "movk x22, #0x21fb, lsl #32", + "movk x22, #0x4009, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldlg2": { @@ -2271,15 +2271,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x79ff", - "movk x21, #0x509f, lsl #16", - "movk x21, #0x4413, lsl #32", - "movk x21, #0x3fd3, lsl #48", - "fmov d2, x21", + "mov x22, #0x79ff", + "movk x22, #0x509f, lsl #16", + "movk x22, #0x4413, lsl #32", + "movk x22, #0x3fd3, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldln2": { @@ -2295,15 +2295,15 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov x21, #0x39ef", - "movk x21, #0xfefa, lsl #16", - "movk x21, #0x2e42, lsl #32", - "movk x21, #0x3fe6, lsl #48", - "fmov d2, x21", + "mov x22, #0x39ef", + "movk x22, #0xfefa, lsl #16", + "movk x22, #0x2e42, lsl #32", + "movk x22, #0x3fe6, lsl #48", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fldz": { @@ -2319,12 +2319,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "mov w21, #0x0", - "fmov d2, x21", + "mov w22, #0x0", + "fmov d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "f2xm1": { @@ -2402,13 +2402,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", @@ -2462,8 +2461,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fptan": { @@ -2479,7 +2479,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", @@ -2534,14 +2533,15 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov x23, #0x3ff0000000000000", + "fmov d3, x23", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "str d3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fpatan": { @@ -2555,13 +2555,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov v0.8b, v3.8b", "mov v1.8b, v2.8b", @@ -2615,8 +2614,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fxtract": { @@ -2632,22 +2632,22 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", - "and x21, x21, #0x800fffffffffffff", - "orr x21, x21, #0x3ff0000000000000", - "fmov d3, x21", + "mov x23, v2.d[0]", + "and x24, x23, #0x7ff0000000000000", + "lsr x24, x24, #52", + "sub x24, x24, #0x3ff (1023)", + "scvtf d2, x24", + "and x23, x23, #0x800fffffffffffff", + "orr x23, x23, #0x3ff0000000000000", + "fmov d3, x23", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d3, [x0, #1040]" + "str d3, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fprem1": { @@ -2827,13 +2827,12 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #1019]", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "add x0, x28, x21, lsl #4", + "add x0, x28, x22, lsl #4", "ldr d3, [x0, #1040]", "mov x20, #0x3ff0000000000000", "fmov d4, x20", @@ -2890,8 +2889,9 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "add x0, x28, x22, lsl #4", + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsqrt": { @@ -2921,7 +2921,6 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w22", "orr w21, w23, w21", - "strb w21, [x28, #1298]", "strb w22, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", @@ -3027,12 +3026,13 @@ "ldr x26, [x28, #1024]", "ldr x27, [x28, #1032]", "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #1018]", + "mov w23, #0x0", + "strb w23, [x28, #1018]", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "frndint": { @@ -3332,10 +3332,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub dword [rax]": { @@ -4107,7 +4107,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 30, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -4134,15 +4134,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fild dword [rax]": { @@ -4158,12 +4157,12 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldr w21, [x4]", - "scvtf d2, w21", + "ldr w22, [x4]", + "scvtf d2, w22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp dword [rax]": { @@ -4181,10 +4180,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist dword [rax]": { @@ -4217,10 +4216,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fld tword [rax]": { @@ -4263,10 +4262,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fstp tword [rax]": { @@ -4312,10 +4311,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fcmovnb st0, st0": { @@ -5523,10 +5522,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fsub qword [rax]": { @@ -6479,10 +6478,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp qword [rax]": { @@ -6500,10 +6499,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fst qword [rax]": { @@ -6532,10 +6531,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "frstor [rax]": { @@ -6600,11 +6599,10 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1298]", - "mov x20, #0xffffffffffffffff", - "mov w22, #0xffff", - "fmov d2, x20", - "mov v2.d[1], x22", + "mov x22, #0xffffffffffffffff", + "mov w24, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x24", "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6635,8 +6633,8 @@ "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w21, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #38]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6665,10 +6663,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldr q3, [x4, #48]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6697,10 +6695,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #58]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6729,10 +6727,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #68]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6761,10 +6759,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #78]", "and v3.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6793,10 +6791,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v3.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d3, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur q3, [x4, #88]", "and v2.16b, v3.16b, v2.16b", "mrs x0, nzcv", @@ -6825,10 +6823,10 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", "ldur d2, [x4, #98]", "ldr h3, [x4, #106]", "mov v2.h[4], v3.h[0]", @@ -6858,13 +6856,14 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x30, [sp], #16", "mov v2.8b, v0.8b", - "add x0, x28, x20, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "msr nzcv, x23" + "msr nzcv, x23", + "strb w20, [x28, #1298]" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 327, + "ExpectedInstructionCount": 329, "Comment": [ "0xdd !11b /6" ], @@ -6873,8 +6872,10 @@ "ldrh w21, [x28, #1296]", "str w21, [x4]", "mov w21, #0x0", - "mov x22, x21", - "bfi x22, x20, #11, #3", + "ldrb w22, [x28, #1019]", + "mov x0, x21", + "bfi x0, x22, #11, #3", + "mov x22, x0", "ldrb w23, [x28, #1016]", "ldrb w24, [x28, #1017]", "ldrb w25, [x28, #1018]", @@ -7194,8 +7195,8 @@ "strb w21, [x28, #1017]", "strb w21, [x28, #1018]", "strb w21, [x28, #1022]", - "strb w21, [x28, #1298]", - "msr nzcv, x25" + "msr nzcv, x25", + "strb w21, [x28, #1298]" ] }, "fnstsw [rax]": { @@ -7507,7 +7508,7 @@ ] }, "fstp st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd8 /3" ], @@ -7523,17 +7524,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xd9 /3" ], @@ -7549,17 +7549,16 @@ "ldrb w23, [x28, #1298]", "lsl w22, w21, w22", "orr w22, w23, w22", - "strb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xda /3" ], @@ -7575,17 +7574,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdb /3" ], @@ -7601,17 +7599,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdc /3" ], @@ -7627,17 +7624,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdd /3" ], @@ -7653,17 +7649,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xde /3" ], @@ -7679,17 +7674,16 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fstp st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": [ "0xdd 11b 0xdf /3" ], @@ -7705,13 +7699,12 @@ "mov w23, #0x1", "lsl w21, w23, w21", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "lsl w22, w23, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucom st0": { @@ -7950,10 +7943,10 @@ "ldrb w21, [x28, #1298]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st1": { @@ -7984,10 +7977,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st2": { @@ -8018,10 +8011,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st3": { @@ -8052,10 +8045,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st4": { @@ -8086,10 +8079,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st5": { @@ -8120,10 +8113,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st6": { @@ -8154,10 +8147,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fucomp st7": { @@ -8188,10 +8181,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fiadd word [rax]": { @@ -8280,10 +8273,10 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fisub word [rax]": { @@ -8372,12 +8365,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st1": { @@ -8398,12 +8391,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "faddp st2": { @@ -8424,12 +8417,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st3": { @@ -8450,12 +8443,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st4": { @@ -8476,12 +8469,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st5": { @@ -8502,12 +8495,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st6": { @@ -8528,12 +8521,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "faddp st7": { @@ -8554,12 +8547,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st0": { @@ -8580,12 +8573,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st1": { @@ -8606,12 +8599,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fmulp st2": { @@ -8632,12 +8625,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st3": { @@ -8658,12 +8651,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st4": { @@ -8684,12 +8677,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st5": { @@ -8710,12 +8703,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st6": { @@ -8736,12 +8729,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fmulp st7": { @@ -8762,16 +8755,16 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fcompp": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 30, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -8798,15 +8791,14 @@ "ldrb w22, [x28, #1298]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "db 0xde, 0xe0": { @@ -8829,12 +8821,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st1, st0": { @@ -8855,12 +8847,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubrp st2, st0": { @@ -8881,12 +8873,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st3, st0": { @@ -8907,12 +8899,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st4, st0": { @@ -8933,12 +8925,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st5, st0": { @@ -8959,12 +8951,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st6, st0": { @@ -8985,12 +8977,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubrp st7, st0": { @@ -9011,12 +9003,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xe8": { @@ -9039,12 +9031,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st1, st0": { @@ -9065,12 +9057,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fsubp st2, st0": { @@ -9091,12 +9083,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st3, st0": { @@ -9117,12 +9109,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st4, st0": { @@ -9143,12 +9135,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st5, st0": { @@ -9169,12 +9161,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st6, st0": { @@ -9195,12 +9187,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fsubp st7, st0": { @@ -9221,12 +9213,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf0": { @@ -9249,12 +9241,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st1, st0": { @@ -9275,12 +9267,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivrp st2, st0": { @@ -9301,12 +9293,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st3, st0": { @@ -9327,12 +9319,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st4, st0": { @@ -9353,12 +9345,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st5, st0": { @@ -9379,12 +9371,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st6, st0": { @@ -9405,12 +9397,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivrp st7, st0": { @@ -9431,12 +9423,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "db 0xde, 0xf8": { @@ -9459,12 +9451,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st1, st0": { @@ -9485,12 +9477,12 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fdivp st2, st0": { @@ -9511,12 +9503,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st3, st0": { @@ -9537,12 +9529,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st4, st0": { @@ -9563,12 +9555,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st5, st0": { @@ -9589,12 +9581,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st6, st0": { @@ -9615,12 +9607,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fdivp st7, st0": { @@ -9641,12 +9633,12 @@ "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w22, [x28, #1298]" ] }, "fild word [rax]": { @@ -9662,13 +9654,13 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", - "ldrh w21, [x4]", - "sxth x21, w21", - "scvtf d2, x21", + "ldrh w22, [x4]", + "sxth x22, w22", + "scvtf d2, x22", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fisttp word [rax]": { @@ -9686,10 +9678,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fist word [rax]": { @@ -9722,10 +9714,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "fbld tword [rax]": { @@ -9741,7 +9733,6 @@ "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1298]", "strb w20, [x28, #1019]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -9799,7 +9790,8 @@ "ldr x30, [sp], #16", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #1040]" + "str d2, [x0, #1040]", + "strb w21, [x28, #1298]" ] }, "fbstp tword [rax]": { @@ -9873,10 +9865,10 @@ "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "strb w20, [x28, #1019]" + "strb w20, [x28, #1019]", + "strb w21, [x28, #1298]" ] }, "ffreep st0": { @@ -10021,11 +10013,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st1": { @@ -10054,11 +10046,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st2": { @@ -10087,11 +10079,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st3": { @@ -10120,11 +10112,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st4": { @@ -10153,11 +10145,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st5": { @@ -10186,11 +10178,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st6": { @@ -10219,11 +10211,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fucomip st7": { @@ -10252,11 +10244,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st0": { @@ -10285,11 +10277,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st1": { @@ -10318,11 +10310,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st2": { @@ -10351,11 +10343,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st3": { @@ -10384,11 +10376,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st4": { @@ -10417,11 +10409,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st5": { @@ -10450,11 +10442,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st6": { @@ -10483,11 +10475,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] }, "fcomip st7": { @@ -10516,11 +10508,11 @@ "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x22", + "strb w21, [x28, #1298]" ] } }