diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index dcba25815..9f4752584 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -159,8 +159,6 @@ void OpDispatchBuilder::RETOp(OpcodeArgs) { if (CTX->Config.ABILocalFlags) { _InvalidateFlags(~0UL); // all flags InvalidatePF_AF(); - // Deferred flags are invalidated now - InvalidateDeferredFlags(); } Ref SP = _RMWHandle(LoadGPRRegister(X86State::REG_RSP)); @@ -557,8 +555,6 @@ void OpDispatchBuilder::CALLOp(OpcodeArgs) { if (CTX->Config.ABILocalFlags) { _InvalidateFlags(~0UL); // all flags InvalidatePF_AF(); - // Deferred flags are invalidated now - InvalidateDeferredFlags(); } auto ConstantPC = GetRelocatedPC(Op); @@ -2029,8 +2025,6 @@ void OpDispatchBuilder::RCROp(OpcodeArgs) { Ref Res = _Lshr(OpSize, Dest, Src); auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC); - InvalidateDeferredFlags(); - // Constant folded version of the above, with fused shifts. if (Const > 1) { Res = _Orlshl(OpSize, Res, Dest, Size + 1 - Const); @@ -2254,8 +2248,6 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) { Ref Res = _Lshl(OpSize, Dest, Src); auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC); - InvalidateDeferredFlags(); - // Res |= (Src << (Size - Shift + 1)); if (Const > 1) { Res = _Orlshr(OpSize, Res, Dest, Size + 1 - Const); @@ -2384,9 +2376,6 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) { const uint32_t Size = GetDstBitSize(Op); const uint32_t Mask = Size - 1; - // Deferred flags are invalidated now - InvalidateDeferredFlags(); - if (IsNonconstant) { // Because we mask explicitly with And/Bfe/Sbfe after, we can allow garbage here. Src = LoadSource(GPRClass, Op, Op->Src[SrcIndex], Op->Flags, {.AllowUpperGarbage = true}); @@ -2855,8 +2844,6 @@ void OpDispatchBuilder::DASOp(OpcodeArgs) { } void OpDispatchBuilder::AAAOp(OpcodeArgs) { - InvalidateDeferredFlags(); - auto A = LoadGPRRegister(X86State::REG_RAX); auto AF = CalculateAFForDecimal(A); @@ -2874,8 +2861,6 @@ void OpDispatchBuilder::AAAOp(OpcodeArgs) { } void OpDispatchBuilder::AASOp(OpcodeArgs) { - InvalidateDeferredFlags(); - auto A = LoadGPRRegister(X86State::REG_RAX); auto AF = CalculateAFForDecimal(A); @@ -2893,8 +2878,6 @@ void OpDispatchBuilder::AASOp(OpcodeArgs) { } void OpDispatchBuilder::AAMOp(OpcodeArgs) { - InvalidateDeferredFlags(); - auto AL = LoadGPRRegister(X86State::REG_RAX, OpSize::i8Bit); auto Imm8 = _Constant(Op->Src[0].Data.Literal.Value & 0xFF); auto UDivOp = _UDiv(OpSize::i64Bit, AL, Imm8); @@ -2908,8 +2891,6 @@ void OpDispatchBuilder::AAMOp(OpcodeArgs) { } void OpDispatchBuilder::AADOp(OpcodeArgs) { - InvalidateDeferredFlags(); - auto A = LoadGPRRegister(X86State::REG_RAX); auto AH = _Lshr(OpSize::i32Bit, A, _Constant(8)); auto Imm8 = _Constant(Op->Src[0].Data.Literal.Value & 0xFF); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index b1658569e..82b512c94 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1579,7 +1579,6 @@ private: // Set flag tracking to prepare for an operation that directly writes NZCV. void HandleNZCVWrite() { - InvalidateDeferredFlags(); CachedNZCV = nullptr; NZCVDirty = false; } @@ -2253,12 +2252,6 @@ private: */ void CalculateDeferredFlags(); - /** - * @brief Invalidates NZCV. Mostly vestigial. - */ - void InvalidateDeferredFlags() { - } - void ZeroShiftResult(FEXCore::X86Tables::DecodedOp Op) { // In the case of zero-rotate, we need to store the destination still to deal with 32-bit semantics. const auto Size = OpSizeFromSrc(Op); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 14cba5db3..5bcf58d12 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -2226,8 +2226,6 @@ void OpDispatchBuilder::AVX128_VPERM2(OpcodeArgs) { template void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs) { - InvalidateDeferredFlags(); - const auto Size = GetSrcSize(Op); const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE; @@ -2296,9 +2294,6 @@ void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs) { } void OpDispatchBuilder::AVX128_PTest(OpcodeArgs) { - // Invalidate deferred flags early - InvalidateDeferredFlags(); - const auto Size = GetSrcSize(Op); const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE; diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index 22a4abda0..6b39d6480 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -36,13 +36,9 @@ void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, Ref Src) { size_t NumFlags = FlagOffsets.size(); if (Lower8) { // Calculate flags early. - // Could use InvalidateDeferredFlags() if we had masked invalidation. // This is only a partial overwrite of flags since OF isn't stored here. CalculateDeferredFlags(); NumFlags = 5; - } else { - // We are overwriting all RFLAGS. Invalidate the deferred flag state. - InvalidateDeferredFlags(); } // PF and CF are both stored inverted, so hoist the invert. diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index b7864c5cc..3d5e55ffe 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -3924,9 +3924,6 @@ void OpDispatchBuilder::AVXVectorVariableBlend(OpcodeArgs, IR::OpSize ElementSiz } void OpDispatchBuilder::PTestOpImpl(OpSize Size, Ref Dest, Ref Src) { - // Invalidate deferred flags early - InvalidateDeferredFlags(); - Ref Test1 = _VAnd(Size, OpSize::i8Bit, Dest, Src); Ref Test2 = _VAndn(Size, OpSize::i8Bit, Src, Dest); @@ -3959,8 +3956,6 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) { } void OpDispatchBuilder::VTESTOpImpl(OpSize SrcSize, IR::OpSize ElementSize, Ref Src1, Ref Src2) { - InvalidateDeferredFlags(); - const auto ElementSizeInBits = IR::OpSizeAsBits(ElementSize); const auto MaskConstant = uint64_t {1} << (ElementSizeInBits - 1); @@ -4835,10 +4830,6 @@ template void OpDispatchBuilder::VPERMILRegOp(OpcodeArgs); void OpDispatchBuilder::PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask) { const uint16_t Control = Op->Src[1].Literal(); - // SSE4.2 string instructions modify flags, so invalidate - // any previously deferred flags. - InvalidateDeferredFlags(); - // NOTE: Unlike most other SSE/AVX instructions, the SSE4.2 string and text // instructions do *not* require memory operands to be aligned on a 16 byte // boundary (see "Other Exceptions" descriptions for the relevant diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index b165dd1df..51a2da554 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -634,10 +634,7 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs, IR::OpSize Width, bool Integer, OpDisp SetRFLAG(HostFlag_Unordered); SetRFLAG(HostFlag_ZF); } else { - // Invalidate deferred flags early // OF, SF, AF, PF all undefined - InvalidateDeferredFlags(); - SetCFDirect(HostFlag_CF); SetRFLAG(HostFlag_ZF);