From cf3c41acc75c12978afd3865ccfc76325f4c90b1 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 10 Feb 2026 14:29:32 -0800 Subject: [PATCH] FEXCore: Fixup ARPL implementation Some subtle details were wrong in the implementation, and some minor changes to be more optimal. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 11 +++++------ .../Source/Interface/Core/X86Tables/BaseTables.cpp | 2 +- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index b5175860f..91fe96b57 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1052,19 +1052,18 @@ void OpDispatchBuilder::ARPLOp(OpcodeArgs) { Ref Src = LoadSourceGPR_WithOpSize(Op, Op->Src[0], Size, Op->Flags, {.AllowUpperGarbage = true}); // RPL is the low two bits of the selector. - Ref DestRPL = _And(Size, Dest, Constant(0x3)); - Ref SrcRPL = _And(Size, Src, Constant(0x3)); + Ref DestRPL = _Bfe(OpSize::i32Bit, 2, 0, Dest); + Ref SrcRPL = _Bfe(OpSize::i32Bit, 2, 0, Src); // NeedUpdate is 1 when DestRPL < SrcRPL, else 0. - Ref NeedUpdate = _Select(OpSize::i32Bit, Size, CondClass::ULT, DestRPL, SrcRPL, Constant(1), Constant(0)); + Ref NeedUpdate = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClass::ULT, DestRPL, SrcRPL, Constant(1), Constant(0)); SetRFLAG(NeedUpdate); // Compute adjusted destination selector: (Dest & ~3) | SrcRPL. - Ref Cleared = _And(Size, Dest, Constant(0xFFFC)); - Ref NewDest = _Or(Size, Cleared, SrcRPL); + auto NewDest = _Bfxil(OpSize::i32Bit, 2, 0, Dest, SrcRPL); // Conditionally select updated selector based on NeedUpdate. - Ref FinalDest = _Select(Size, OpSize::i32Bit, CondClass::NEQ, NeedUpdate, Constant(0), NewDest, Dest); + Ref FinalDest = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClass::NEQ, NeedUpdate, Constant(0), NewDest, Dest); StoreResultGPR_WithOpSize(Op, Op->Dest, FinalDest, Size); } diff --git a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp index 9859ef99b..f4b631dce 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp @@ -124,7 +124,7 @@ constexpr std::array Primary_ArchSelect_LUT = {{ }, // ENTRY_63 { - {"ARPL", TYPE_INST, GenFlagsSameSize(SIZE_16BIT) | FLAGS_MODRM, 0, { .OpDispatch = &IR::OpDispatchBuilder::ARPLOp } }, + {"ARPL", TYPE_INST, GenFlagsSameSize(SIZE_16BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST, 0, { .OpDispatch = &IR::OpDispatchBuilder::ARPLOp } }, {"MOVSXD", TYPE_INST, GenFlagsDstSize(SIZE_64BIT) | FLAGS_MODRM, 0, { .OpDispatch = &IR::OpDispatchBuilder::MOVSXDOp } }, }, // ENTRY_9A