From ca31a0404c130305a3c49d4b6553989cf7bba637 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Mon, 29 Jan 2024 15:11:59 +0000 Subject: [PATCH 1/4] ConstProp should generate 32bit constants when required --- FEXCore/Source/Interface/IR/Passes/ConstProp.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index af4cba631..3b4aee0b5 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -833,12 +833,17 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current uint64_t Constant; if (IREmit->IsValueConstant(Op->Src, &Constant)) { // SBFE of a constant can be converted to a constant. - uint64_t SourceMask = Op->Width == 64 ? ~0ULL : ((1ULL << Op->Width) - 1); + uint64_t SourceMask = + Op->Width == 64 ? ~0ULL : ((1ULL << Op->Width) - 1); + uint64_t DestSizeInBits = IROp->Size * 8; + uint64_t DestMask = + DestSizeInBits == 64 ? ~0ULL : ((1ULL << DestSizeInBits) - 1); SourceMask <<= Op->lsb; int64_t NewConstant = (Constant & SourceMask) >> Op->lsb; NewConstant <<= 64 - Op->Width; NewConstant >>= 64 - Op->Width; + NewConstant &= DestMask; IREmit->ReplaceWithConstant(CodeNode, NewConstant); Changed = true; From 027fbbf051f8840850c2f5b955d2c42686fb9a21 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Mon, 29 Jan 2024 15:12:20 +0000 Subject: [PATCH 2/4] Optimize CDQOp --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index c2b72e654..52b64c02e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1395,11 +1395,12 @@ void OpDispatchBuilder::XCHGOp(OpcodeArgs) { } void OpDispatchBuilder::CDQOp(OpcodeArgs) { - OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); uint8_t DstSize = GetDstSize(Op); uint8_t SrcSize = DstSize >> 1; + OrderedNode *Src = LoadGPRRegister(X86State::REG_RAX, SrcSize, 0, true); - Src = _Sbfe(OpSize::i64Bit, SrcSize * 8, 0, Src); + Src = _Sbfe(DstSize <= 4 ? OpSize::i32Bit : OpSize::i64Bit, SrcSize * 8, 0, + Src); StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Src, DstSize, -1); } From 85105a6af3f88c3d77702f442161303dec755825 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Mon, 29 Jan 2024 15:13:43 +0000 Subject: [PATCH 3/4] Update instcountci json file --- unittests/InstructionCountCI/Primary.json | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index e6af1e194..62a1f6e00 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2786,8 +2786,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x98", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sxtb x20, w20", + "sxtb w20, w4", "bfxil x4, x20, #0, #16" ] }, @@ -2795,9 +2794,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x98", "ExpectedArm64ASM": [ - "mov w20, w4", - "sxth x20, w20", - "mov w4, w20" + "sxth w4, w4" ] }, "cdqe": { From 515e98f4cb1c039cccb910122fbf4ba89d2517ac Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Tue, 30 Jan 2024 10:47:56 +0000 Subject: [PATCH 4/4] Update instruction counts --- unittests/InstructionCountCI/Primary.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 62a1f6e00..6246ae6d4 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2783,7 +2783,7 @@ "ExpectedArm64ASM": [] }, "cbw": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x98", "ExpectedArm64ASM": [ "sxtb w20, w4", @@ -2791,7 +2791,7 @@ ] }, "cwde": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 1, "Comment": "0x98", "ExpectedArm64ASM": [ "sxth w4, w4"