From ce8392d5ae3a29b984fe1a8ba0cbc89e52467c8a Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 27 Aug 2023 22:21:30 -0700 Subject: [PATCH] IR: Removes implicit sized ror --- .../Interface/Core/OpcodeDispatcher.cpp | 14 +++++----- .../Core/OpcodeDispatcher/Crypto.cpp | 26 +++++++++---------- FEXCore/include/FEXCore/IR/IREmitter.h | 3 --- 3 files changed, 20 insertions(+), 23 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 277625ec9..c7e9d2bed 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -2171,7 +2171,7 @@ void OpDispatchBuilder::ROROp(OpcodeArgs) { } } - auto ALUOp = _Ror(Dest, Src); + auto ALUOp = _Ror(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); StoreResult(GPRClass, Op, ALUOp, -1); @@ -2210,7 +2210,7 @@ void OpDispatchBuilder::RORImmediateOp(OpcodeArgs) { } } - auto ALUOp = _Ror(Dest, Src); + auto ALUOp = _Ror(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); StoreResult(GPRClass, Op, ALUOp, -1); @@ -2249,7 +2249,7 @@ void OpDispatchBuilder::ROLOp(OpcodeArgs) { } } - auto ALUOp = _Ror(Dest, _Sub(_Constant(Size, std::max(32U, Size)), Src)); + auto ALUOp = _Ror(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, _Sub(_Constant(Size, std::max(32U, Size)), Src)); StoreResult(GPRClass, Op, ALUOp, -1); @@ -2290,7 +2290,7 @@ void OpDispatchBuilder::ROLImmediateOp(OpcodeArgs) { } } - auto ALUOp = _Ror(Dest, Src); + auto ALUOp = _Ror(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); StoreResult(GPRClass, Op, ALUOp, -1); @@ -2438,7 +2438,7 @@ void OpDispatchBuilder::RORX(OpcodeArgs) { LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); const uint64_t Amount = Op->Src[1].Data.Literal.Value; - auto Result = _Ror(Src, _Constant(Amount)); + auto Result = _Ror(IR::SizeToOpSize(GetSrcSize(Op)), Src, _Constant(Amount)); StoreResult(GPRClass, Op, Result, -1); } @@ -2870,7 +2870,7 @@ void OpDispatchBuilder::RCLSmallerOp(OpcodeArgs) { // Shift 1 more bit that expected to get our result // Shifting to the right will now behave like a rotate to the left // Which we emulate with a _Ror - OrderedNode *Res = _Ror(Tmp, _Sub(_Constant(Size, 64), Src)); + OrderedNode *Res = _Ror(OpSize::i64Bit, Tmp, _Sub(_Constant(Size, 64), Src)); StoreResult(GPRClass, Op, Res, -1); @@ -2878,7 +2878,7 @@ void OpDispatchBuilder::RCLSmallerOp(OpcodeArgs) { // Our new CF is now at the bit position that we are shifting // Either 0 if CF hasn't changed (CF is living in bit 0) // or higher - auto NewCF = _Bfe(1, 0, _Ror(Tmp, _Sub(_Constant(63), Src))); + auto NewCF = _Bfe(1, 0, _Ror(OpSize::i64Bit, Tmp, _Sub(_Constant(63), Src))); auto CompareResult = _Select(FEXCore::IR::COND_UGE, Src, _Constant(1), NewCF, CF); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp index 9901f6b09..319f1dcbf 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp @@ -25,7 +25,7 @@ void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) { OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); - auto Tmp = _Ror(_VExtractToGPR(16, 4, Dest, 3), _Constant(32, 2)); + auto Tmp = _Ror(OpSize::i32Bit, _VExtractToGPR(16, 4, Dest, 3), _Constant(32, 2)); auto Top = _Add(_VExtractToGPR(16, 4, Src, 3), Tmp); auto Result = _VInsGPR(16, 4, 3, Src, Top); @@ -54,10 +54,10 @@ void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) { auto W13 = _VExtractToGPR(16, 4, Src, 2); auto W14 = _VExtractToGPR(16, 4, Src, 1); auto W15 = _VExtractToGPR(16, 4, Src, 0); - auto W16 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 3), W13), ThirtyOne); - auto W17 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 2), W14), ThirtyOne); - auto W18 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 1), W15), ThirtyOne); - auto W19 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 0), W16), ThirtyOne); + auto W16 = _Ror(OpSize::i32Bit, _Xor(_VExtractToGPR(16, 4, Dest, 3), W13), ThirtyOne); + auto W17 = _Ror(OpSize::i32Bit, _Xor(_VExtractToGPR(16, 4, Dest, 2), W14), ThirtyOne); + auto W18 = _Ror(OpSize::i32Bit, _Xor(_VExtractToGPR(16, 4, Dest, 1), W15), ThirtyOne); + auto W19 = _Ror(OpSize::i32Bit, _Xor(_VExtractToGPR(16, 4, Dest, 0), W16), ThirtyOne); auto D3 = _VInsGPR(16, 4, 3, Dest, W16); auto D2 = _VInsGPR(16, 4, 2, D3, W17); @@ -117,9 +117,9 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) { auto C = _VExtractToGPR(16, 4, Dest, 1); auto D = _VExtractToGPR(16, 4, Dest, 0); - auto A1 = _Add(_Add(_Add(Fn(*this, B, C, D), _Ror(A, _Constant(32, 27))), W0E), K); + auto A1 = _Add(_Add(_Add(Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W0E), K); auto B1 = A; - auto C1 = _Ror(B, _Constant(32, 2)); + auto C1 = _Ror(OpSize::i32Bit, B, _Constant(32, 2)); auto D1 = C; auto E1 = D; @@ -127,9 +127,9 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) { }; const auto Round1To3 = [&](OrderedNode *A, OrderedNode *B, OrderedNode *C, OrderedNode *D, OrderedNode *E, OrderedNode *W) -> RoundResult { - auto ANext = _Add(_Add(_Add(_Add(Fn(*this, B, C, D), _Ror(A, _Constant(32, 27))), W), E), K); + auto ANext = _Add(_Add(_Add(_Add(Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W), E), K); auto BNext = A; - auto CNext = _Ror(B, _Constant(32, 2)); + auto CNext = _Ror(OpSize::i32Bit, B, _Constant(32, 2)); auto DNext = C; auto ENext = D; @@ -151,7 +151,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) { void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) { const auto Sigma0 = [this](OrderedNode* W) -> OrderedNode* { - return _Xor(_Xor(_Ror(W, _Constant(32, 7)), _Ror(W, _Constant(32, 18))), _Lshr(W, _Constant(32, 3))); + return _Xor(_Xor(_Ror(OpSize::i32Bit, W, _Constant(32, 7)), _Ror(OpSize::i32Bit, W, _Constant(32, 18))), _Lshr(W, _Constant(32, 3))); }; OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); @@ -178,7 +178,7 @@ void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) { void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) { const auto Sigma1 = [this](OrderedNode* W) -> OrderedNode* { - return _Xor(_Xor(_Ror(W, _Constant(32, 17)), _Ror(W, _Constant(32, 19))), _Lshr(W, _Constant(32, 10))); + return _Xor(_Xor(_Ror(OpSize::i32Bit, W, _Constant(32, 17)), _Ror(OpSize::i32Bit, W, _Constant(32, 19))), _Lshr(W, _Constant(32, 10))); }; OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); @@ -207,10 +207,10 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) { return _Xor(_Xor(_And(A, B), _And(A, C)), _And(B, C)); }; const auto Sigma0 = [this](OrderedNode *A) -> OrderedNode* { - return _Xor(_Xor(_Ror(A, _Constant(32, 2)), _Ror(A, _Constant(32, 13))), _Ror(A, _Constant(32, 22))); + return _Xor(_Xor(_Ror(OpSize::i32Bit, A, _Constant(32, 2)), _Ror(OpSize::i32Bit, A, _Constant(32, 13))), _Ror(OpSize::i32Bit, A, _Constant(32, 22))); }; const auto Sigma1 = [this](OrderedNode *E) -> OrderedNode* { - return _Xor(_Xor(_Ror(E, _Constant(32, 6)), _Ror(E, _Constant(32, 11))), _Ror(E, _Constant(32, 25))); + return _Xor(_Xor(_Ror(OpSize::i32Bit, E, _Constant(32, 6)), _Ror(OpSize::i32Bit, E, _Constant(32, 11))), _Ror(OpSize::i32Bit, E, _Constant(32, 25))); }; OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h index ccafbe840..d667a9300 100644 --- a/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/FEXCore/include/FEXCore/IR/IREmitter.h @@ -200,9 +200,6 @@ friend class FEXCore::IR::PassManager; IRPair _Ashr(uint8_t Size, OrderedNode *_Src1, OrderedNode *_Src2) { return _Ashr(static_cast(Size), _Src1, _Src2); } - IRPair _Ror(OrderedNode *_Src1, OrderedNode *_Src2) { - return _Ror(static_cast(std::max(4, GetOpSize(_Src1))), _Src1, _Src2); - } IRPair _Mul(OrderedNode *_Src1, OrderedNode *_Src2) { return _Mul(static_cast(std::max(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2); }