From cc2eef619ca30899220da826585656d71b2e8bfe Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 7 Oct 2023 22:09:42 -0700 Subject: [PATCH] InstCountCI: Update for AFP optimizations A bunch of random instructions have converted to be optimal in a vacuum. --- unittests/InstructionCountCI/AFP/H0F3A.json | 70 ++- .../AFP/SVE256/Secondary.json | 20 +- .../AFP/SVE256/Secondary_REP.json | 232 +++------ .../AFP/SVE256/Secondary_REPNE.json | 222 +++------ .../InstructionCountCI/AFP/Secondary.json | 10 +- .../InstructionCountCI/AFP/Secondary_REP.json | 121 ++--- .../AFP/Secondary_REPNE.json | 116 ++--- .../InstructionCountCI/AFP/VEX_map1.json | 374 ++++++-------- .../InstructionCountCI/AFP/VEX_map3.json | 110 ++--- unittests/InstructionCountCI/H0F3A.json | 40 +- .../RPRES/Secondary_REP.json | 11 +- .../RPRES/Secondary_REP_AFP.json | 37 ++ .../InstructionCountCI/RPRES/VEX_map1.json | 24 +- .../RPRES/VEX_map1_AFP.json | 79 +++ unittests/InstructionCountCI/Secondary.json | 8 +- .../InstructionCountCI/SecondaryModRM.json | 3 +- .../InstructionCountCI/Secondary_REP.json | 116 ++--- .../InstructionCountCI/Secondary_REPNE.json | 104 ++-- unittests/InstructionCountCI/VEX_map1.json | 458 ++++++++---------- unittests/InstructionCountCI/VEX_map2.json | 4 +- unittests/InstructionCountCI/VEX_map3.json | 100 ++-- unittests/InstructionCountCI/x87.json | 3 +- unittests/InstructionCountCI/x87_f64.json | 3 +- 23 files changed, 969 insertions(+), 1296 deletions(-) create mode 100644 unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json create mode 100644 unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index 50fc5f020..8ca887413 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -11,123 +11,113 @@ }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "Nearest rounding", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintn s2, s17", - "mov v16.s[0], v2.s[0]" + "frintn s16, s17" ] }, "roundss xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "-inf rounding", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintm s2, s17", - "mov v16.s[0], v2.s[0]" + "frintm s16, s17" ] }, "roundss xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "+inf rounding", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintp s2, s17", - "mov v16.s[0], v2.s[0]" + "frintp s16, s17" ] }, "roundss xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "truncate rounding", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintz s2, s17", - "mov v16.s[0], v2.s[0]" + "frintz s16, s17" ] }, "roundss xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "host rounding mode rounding", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frinti s2, s17", - "mov v16.s[0], v2.s[0]" + "frinti s16, s17" ] }, "roundsd xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "Nearest rounding", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintn d2, d17", - "mov v16.d[0], v2.d[0]" + "frintn d16, d17" ] }, "roundsd xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "-inf rounding", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintm d2, d17", - "mov v16.d[0], v2.d[0]" + "frintm d16, d17" ] }, "roundsd xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "+inf rounding", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintp d2, d17", - "mov v16.d[0], v2.d[0]" + "frintp d16, d17" ] }, "roundsd xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "truncate rounding", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintz d2, d17", - "mov v16.d[0], v2.d[0]" + "frintz d16, d17" ] }, "roundsd xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "host rounding mode rounding", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frinti d2, d17", - "mov v16.d[0], v2.d[0]" + "frinti d16, d17" ] } } diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 72e0962e5..c4b7497d1 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -10,33 +10,25 @@ }, "Instructions": { "cvtpi2ps xmm0, [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf v2.4s, v2.4s", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf v16.2s, v2.2s" ] }, "cvtpi2ps xmm0, mm0": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x28, #752]", - "scvtf v2.4s, v2.4s", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf v16.2s, v2.2s" ] } } diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index 93370e686..28340389e 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -10,64 +10,48 @@ }, "Instructions": { "cvtsi2ss xmm0, eax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf s2, w4", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf s16, w4" ] }, "cvtsi2ss xmm0, dword [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr s2, [x4]", - "scvtf s2, s2", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf s16, s2" ] }, "cvtsi2ss xmm0, qword [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr x20, [x4]", - "scvtf s2, x20", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf s16, x20" ] }, "sqrtss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x51", "ExpectedArm64ASM": [ - "fsqrt s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fsqrt s16, s17" ] }, "rsqrtss xmm0, xmm1": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", "0xf3 0x0f 0x52" @@ -75,258 +59,192 @@ "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", "fsqrt s1, s17", - "fdiv s2, s0, s1", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s16, s0, s1" ] }, "rcpss xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", "0xf3 0x0f 0x53" ], "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", - "fdiv s2, s0, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s16, s0, s17" ] }, "addss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd s2, s16, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fadd s16, s16, s17" ] }, "mulss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul s2, s16, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmul s16, s16, s17" ] }, "cvtss2sd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "fcvt d2, s17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcvt d16, s17" ] }, "cvtss2sd xmm0, [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "ldr s2, [x4]", - "fcvt d2, s2", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "ldr d2, [x4]", + "fcvt d16, s2" ] }, "subss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub s2, s16, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fsub s16, s16, s17" ] }, "minss xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5d" ], "ExpectedArm64ASM": [ - "fcmp s16, s17", - "fcsel s2, s16, s17, mi", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmin s16, s16, s17" ] }, "divss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv s2, s16, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s16, s16, s17" ] }, "maxss xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5f" ], "ExpectedArm64ASM": [ - "fcmp s16, s17", - "fcsel s2, s17, s16, mi", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmax s16, s16, s17" ] }, "cmpss xmm0, xmm1, 0": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmeq s16, s16, s17" ] }, "cmpss xmm0, xmm1, 1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt s2, s17, s16", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmgt s16, s17, s16" ] }, "cmpss xmm0, xmm1, 2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge s2, s17, s16", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmge s16, s17, s16" ] }, "cmpss xmm0, xmm1, 3": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "ptrue p0.s, vl1", + "mov z16.s, p0/m, z0.s" ] }, "cmpss xmm0, xmm1, 4": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mvn v2.8b, v2.8b", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmeq s0, s16, s17", + "mvn v0.8b, v0.8b", + "ptrue p0.s, vl1", + "mov z16.s, p0/m, z0.s" ] }, "cmpss xmm0, xmm1, 5": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmgt s2, s17, s16", "mvn v2.16b, v2.16b", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.s[0], v2.s[0]" ] }, "cmpss xmm0, xmm1, 6": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s2, s17, s16", "mvn v2.16b, v2.16b", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.s[0], v2.s[0]" ] }, "cmpss xmm0, xmm1, 7": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "ptrue p0.s, vl1", + "mov z16.s, p0/m, z0.s" ] } } diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index ef33ba0e2..2f22ce192 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -10,310 +10,232 @@ }, "Instructions": { "cvtsi2sd xmm0, eax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, w4", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf d16, w4" ] }, "cvtsi2sd xmm0, dword [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr w20, [x4]", - "scvtf d2, w20", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf d16, w20" ] }, "cvtsi2sd xmm0, rax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, x4", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf d16, x4" ] }, "cvtsi2sd xmm0, qword [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf d2, d2", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "scvtf d16, d2" ] }, "sqrtsd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x51" ], "ExpectedArm64ASM": [ - "fsqrt d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fsqrt d16, d17" ] }, "addsd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd d2, d16, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fadd d16, d16, d17" ] }, "mulsd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul d2, d16, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmul d16, d16, d17" ] }, "cvtsd2ss xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "fcvt s2, d17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcvt s16, d17" ] }, "cvtsd2ss xmm0, [rax]": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "ldr d2, [x4]", - "fcvt s2, d2", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "ldr q2, [x4]", + "fcvt s16, d2" ] }, "subsd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub d2, d16, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fsub d16, d16, d17" ] }, "minsd xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5d" ], "ExpectedArm64ASM": [ - "fcmp d16, d17", - "fcsel d2, d16, d17, mi", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmin d16, d16, d17" ] }, "divsd xmm0, xmm1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv d2, d16, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv d16, d16, d17" ] }, "maxsd xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5f" ], "ExpectedArm64ASM": [ - "fcmp d16, d17", - "fcsel d2, d17, d16, mi", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fmax d16, d16, d17" ] }, "cmpsd xmm0, xmm1, 0": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmeq d16, d16, d17" ] }, "cmpsd xmm0, xmm1, 1": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt d2, d17, d16", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmgt d16, d17, d16" ] }, "cmpsd xmm0, xmm1, 2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge d2, d17, d16", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmge d16, d17, d16" ] }, "cmpsd xmm0, xmm1, 3": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "ptrue p0.d, vl1", + "mov z16.d, p0/m, z0.d" ] }, "cmpsd xmm0, xmm1, 4": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mvn v2.8b, v2.8b", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcmeq d0, d16, d17", + "mvn v0.8b, v0.8b", + "ptrue p0.d, vl1", + "mov z16.d, p0/m, z0.d" ] }, "cmpsd xmm0, xmm1, 5": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmgt d2, d17, d16", "mvn v2.16b, v2.16b", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.d[0], v2.d[0]" ] }, "cmpsd xmm0, xmm1, 6": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d2, d17, d16", "mvn v2.16b, v2.16b", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.d[0], v2.d[0]" ] }, "cmpsd xmm0, xmm1, 7": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "ptrue p0.d, vl1", + "mov z16.d, p0/m, z0.d" ] } } diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index 1f3cb6f91..466bfe5b9 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -11,27 +11,25 @@ }, "Instructions": { "cvtpi2ps xmm0, [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf v2.4s, v2.4s", - "mov v16.d[0], v2.d[0]" + "scvtf v16.2s, v2.2s" ] }, "cvtpi2ps xmm0, mm0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x28, #752]", - "scvtf v2.4s, v2.4s", - "mov v16.d[0], v2.d[0]" + "scvtf v16.2s, v2.2s" ] } } diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index 194a16464..47f802bb2 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -11,51 +11,47 @@ }, "Instructions": { "cvtsi2ss xmm0, eax": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf s2, w4", - "mov v16.s[0], v2.s[0]" + "scvtf s16, w4" ] }, "cvtsi2ss xmm0, dword [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr s2, [x4]", - "scvtf s2, s2", - "mov v16.s[0], v2.s[0]" + "scvtf s16, s2" ] }, "cvtsi2ss xmm0, qword [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr x20, [x4]", - "scvtf s2, x20", - "mov v16.s[0], v2.s[0]" + "scvtf s16, x20" ] }, "sqrtss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": "0xf3 0x0f 0x51", "ExpectedArm64ASM": [ - "fsqrt s2, s17", - "mov v16.s[0], v2.s[0]" + "fsqrt s16, s17" ] }, "rsqrtss xmm0, xmm1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", @@ -64,12 +60,11 @@ "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", "fsqrt s1, s17", - "fdiv s2, s0, s1", - "mov v16.s[0], v2.s[0]" + "fdiv s16, s0, s1" ] }, "rcpss xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", @@ -77,159 +72,145 @@ ], "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", - "fdiv s2, s0, s17", - "mov v16.s[0], v2.s[0]" + "fdiv s16, s0, s17" ] }, "addss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fadd s16, s16, s17" ] }, "mulss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fmul s16, s16, s17" ] }, "cvtss2sd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "fcvt d2, s17", - "mov v16.d[0], v2.d[0]" + "fcvt d16, s17" ] }, "cvtss2sd xmm0, [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "ldr s2, [x4]", - "fcvt d2, s2", - "mov v16.d[0], v2.d[0]" + "ldr d2, [x4]", + "fcvt d16, s2" ] }, "subss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fsub s16, s16, s17" ] }, "minss xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5d" ], "ExpectedArm64ASM": [ - "fcmp s16, s17", - "fcsel s2, s16, s17, mi", - "mov v16.s[0], v2.s[0]" + "fmin s16, s16, s17" ] }, "divss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fdiv s16, s16, s17" ] }, "maxss xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5f" ], "ExpectedArm64ASM": [ - "fcmp s16, s17", - "fcsel s2, s17, s16, mi", - "mov v16.s[0], v2.s[0]" + "fmax s16, s16, s17" ] }, "cmpss xmm0, xmm1, 0": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fcmeq s16, s16, s17" ] }, "cmpss xmm0, xmm1, 1": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt s2, s17, s16", - "mov v16.s[0], v2.s[0]" + "fcmgt s16, s17, s16" ] }, "cmpss xmm0, xmm1, 2": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge s2, s17, s16", - "mov v16.s[0], v2.s[0]" + "fcmge s16, s17, s16" ] }, "cmpss xmm0, xmm1, 3": { "ExpectedInstructionCount": 5, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v16.s[0], v2.s[0]" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 4": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mvn v2.8b, v2.8b", - "mov v16.s[0], v2.s[0]" + "fcmeq s0, s16, s17", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 5": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], @@ -241,7 +222,7 @@ }, "cmpss xmm0, xmm1, 6": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], @@ -253,15 +234,15 @@ }, "cmpss xmm0, xmm1, 7": { "ExpectedInstructionCount": 4, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mov v16.s[0], v2.s[0]" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.s[0], v0.s[0]" ] } } diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index 4054feb4c..4f75893bc 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -11,215 +11,197 @@ }, "Instructions": { "cvtsi2sd xmm0, eax": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, w4", - "mov v16.d[0], v2.d[0]" + "scvtf d16, w4" ] }, "cvtsi2sd xmm0, dword [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr w20, [x4]", - "scvtf d2, w20", - "mov v16.d[0], v2.d[0]" + "scvtf d16, w20" ] }, "cvtsi2sd xmm0, rax": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, x4", - "mov v16.d[0], v2.d[0]" + "scvtf d16, x4" ] }, "cvtsi2sd xmm0, qword [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf d2, d2", - "mov v16.d[0], v2.d[0]" + "scvtf d16, d2" ] }, "sqrtsd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x51" ], "ExpectedArm64ASM": [ - "fsqrt d2, d17", - "mov v16.d[0], v2.d[0]" + "fsqrt d16, d17" ] }, "addsd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fadd d16, d16, d17" ] }, "mulsd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fmul d16, d16, d17" ] }, "cvtsd2ss xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "fcvt s2, d17", - "mov v16.s[0], v2.s[0]" + "fcvt s16, d17" ] }, "cvtsd2ss xmm0, [rax]": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "ldr d2, [x4]", - "fcvt s2, d2", - "mov v16.s[0], v2.s[0]" + "ldr q2, [x4]", + "fcvt s16, d2" ] }, "subsd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fsub d16, d16, d17" ] }, "minsd xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5d" ], "ExpectedArm64ASM": [ - "fcmp d16, d17", - "fcsel d2, d16, d17, mi", - "mov v16.d[0], v2.d[0]" + "fmin d16, d16, d17" ] }, "divsd xmm0, xmm1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fdiv d16, d16, d17" ] }, "maxsd xmm0, xmm1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 1, "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5f" ], "ExpectedArm64ASM": [ - "fcmp d16, d17", - "fcsel d2, d17, d16, mi", - "mov v16.d[0], v2.d[0]" + "fmax d16, d16, d17" ] }, "cmpsd xmm0, xmm1, 0": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fcmeq d16, d16, d17" ] }, "cmpsd xmm0, xmm1, 1": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt d2, d17, d16", - "mov v16.d[0], v2.d[0]" + "fcmgt d16, d17, d16" ] }, "cmpsd xmm0, xmm1, 2": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge d2, d17, d16", - "mov v16.d[0], v2.d[0]" + "fcmge d16, d17, d16" ] }, "cmpsd xmm0, xmm1, 3": { "ExpectedInstructionCount": 5, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v16.d[0], v2.d[0]" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 4": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mvn v2.8b, v2.8b", - "mov v16.d[0], v2.d[0]" + "fcmeq d0, d16, d17", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 5": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], @@ -231,7 +213,7 @@ }, "cmpsd xmm0, xmm1, 6": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], @@ -243,15 +225,15 @@ }, "cmpsd xmm0, xmm1, 7": { "ExpectedInstructionCount": 4, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mov v16.d[0], v2.d[0]" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.d[0], v0.d[0]" ] } } diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index bd97d9c80..ec33807d9 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -10,532 +10,430 @@ }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x51 128-bit" ], "ExpectedArm64ASM": [ - "fsqrt s2, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsqrt s16, s18" ] }, "vsqrtsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x51 128-bit" ], "ExpectedArm64ASM": [ - "fsqrt d2, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsqrt d16, d18" ] }, "vrsqrtss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b10 0x52 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fmov s0, #0x70 (1.0000)", "fsqrt s1, s18", - "fdiv s2, s0, s1", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s16, s0, s1" ] }, "vrcpss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b10 0x53 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fmov s0, #0x70 (1.0000)", - "fdiv s2, s0, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s16, s0, s18" ] }, "vcmpss xmm0, xmm1, xmm2, 0x00": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq s16, s17, s18" ] }, "vcmpss xmm0, xmm1, xmm2, 0x01": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmgt s2, s18, s17", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmgt s16, s18, s17" ] }, "vcmpss xmm0, xmm1, xmm2, 0x02": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmge s2, s18, s17", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmge s16, s18, s17" ] }, "vcmpss xmm0, xmm1, xmm2, 0x03": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge s0, s17, s18", "fcmgt s1, s18, s17", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x04": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq s2, s17, s18", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq s0, s17, s18", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x05": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmgt s2, s18, s17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.s[0], v2.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x06": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmge s2, s18, s17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.s[0], v2.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x07": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge s0, s17, s18", "fcmgt s1, s18, s17", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x00": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq d16, d17, d18" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x01": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmgt d2, d18, d17", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmgt d16, d18, d17" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x02": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmge d2, d18, d17", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmge d16, d18, d17" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x03": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge d0, d17, d18", "fcmgt d1, d18, d17", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x04": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq d2, d17, d18", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq d0, d17, d18", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x05": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmgt d2, d18, d17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.d[0], v2.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x06": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmge d2, d18, d17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.d[0], v2.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x07": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge d0, d17, d18", "fcmgt d1, d18, d17", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.d[0], v0.d[0]" ] }, "vcvtsi2ss xmm0, xmm1, eax": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf s2, w4", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf s16, w4" ] }, "vcvtsi2ss xmm0, xmm1, rax": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf s2, x4", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf s16, x4" ] }, "vcvtsi2sd xmm0, xmm1, eax": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf d2, w4", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf d16, w4" ] }, "vcvtsi2sd xmm0, xmm1, rax": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf d2, x4", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf d16, x4" ] }, "vmulss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x59 128-bit" ], "ExpectedArm64ASM": [ - "fmul s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmul s16, s17, s18" ] }, "vmulsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x59 128-bit" ], "ExpectedArm64ASM": [ - "fmul d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmul d16, d17, d18" ] }, "vcvtss2sd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5a 128-bit" ], "ExpectedArm64ASM": [ - "fcvt d2, s18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcvt d16, s18" ] }, "vcvtsd2ss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5a 128-bit" ], "ExpectedArm64ASM": [ - "fcvt s2, d18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcvt s16, d18" ] }, "vsubss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5c 128-bit" ], "ExpectedArm64ASM": [ - "fsub s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsub s16, s17, s18" ] }, "vsubsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5c 128-bit" ], "ExpectedArm64ASM": [ - "fsub d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsub d16, d17, d18" ] }, "vminss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5d 128-bit" ], "ExpectedArm64ASM": [ - "fcmp s17, s18", - "fcsel s2, s17, s18, mi", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmin s16, s17, s18" ] }, "vminsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5d 128-bit" ], "ExpectedArm64ASM": [ - "fcmp d17, d18", - "fcsel d2, d17, d18, mi", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmin d16, d17, d18" ] }, "vdivss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5e 128-bit" ], "ExpectedArm64ASM": [ - "fdiv s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fdiv s16, s17, s18" ] }, "vdivsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5e 128-bit" ], "ExpectedArm64ASM": [ - "fdiv d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fdiv d16, d17, d18" ] }, "vmaxss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5f 128-bit" ], "ExpectedArm64ASM": [ - "fcmp s17, s18", - "fcsel s2, s18, s17, mi", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmax s16, s17, s18" ] }, "vmaxsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5f 128-bit" ], "ExpectedArm64ASM": [ - "fcmp d17, d18", - "fcsel d2, d18, d17, mi", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmax d16, d17, d18" ] } } diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index bc5f36627..f8557e37e 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -10,153 +10,123 @@ }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "nearest rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintn s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintn s16, s16" ] }, "vroundss xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "-inf rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintm s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintm s16, s16" ] }, "vroundss xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "+inf rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintp s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintp s16, s16" ] }, "vroundss xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "truncate rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintz s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintz s16, s16" ] }, "vroundss xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "host mode rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frinti s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frinti s16, s16" ] }, "vroundsd xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "nearest rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintn d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintn d16, d16" ] }, "vroundsd xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "-inf rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintm d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintm d16, d16" ] }, "vroundsd xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "+inf rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintp d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintp d16, d16" ] }, "vroundsd xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "truncate rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintz d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintz d16, d16" ] }, "vroundsd xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": [ "host mode rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frinti d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frinti d16, d16" ] } } diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index a35a1b717..103ca28a6 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -168,8 +168,8 @@ "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintn s2, s17", - "mov v16.s[0], v2.s[0]" + "frintn s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "roundss xmm0, xmm1, 00000001b": { @@ -180,8 +180,8 @@ "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintm s2, s17", - "mov v16.s[0], v2.s[0]" + "frintm s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "roundss xmm0, xmm1, 00000010b": { @@ -192,8 +192,8 @@ "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintp s2, s17", - "mov v16.s[0], v2.s[0]" + "frintp s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "roundss xmm0, xmm1, 00000011b": { @@ -204,8 +204,8 @@ "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintz s2, s17", - "mov v16.s[0], v2.s[0]" + "frintz s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "roundss xmm0, xmm1, 00000100b": { @@ -216,8 +216,8 @@ "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frinti s2, s17", - "mov v16.s[0], v2.s[0]" + "frinti s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "roundsd xmm0, xmm1, 00000000b": { @@ -228,8 +228,8 @@ "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintn d2, d17", - "mov v16.d[0], v2.d[0]" + "frintn d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "roundsd xmm0, xmm1, 00000001b": { @@ -240,8 +240,8 @@ "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintm d2, d17", - "mov v16.d[0], v2.d[0]" + "frintm d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "roundsd xmm0, xmm1, 00000010b": { @@ -252,8 +252,8 @@ "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintp d2, d17", - "mov v16.d[0], v2.d[0]" + "frintp d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "roundsd xmm0, xmm1, 00000011b": { @@ -264,8 +264,8 @@ "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintz d2, d17", - "mov v16.d[0], v2.d[0]" + "frintz d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "roundsd xmm0, xmm1, 00000100b": { @@ -276,8 +276,8 @@ "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frinti d2, d17", - "mov v16.d[0], v2.d[0]" + "frinti d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "blendps xmm0, xmm1, 0000b": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP.json index aab887a1c..92058a539 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP.json @@ -6,7 +6,8 @@ ], "DisabledHostFeatures": [ "SVE128", - "SVE256" + "SVE256", + "AFP" ] }, "Instructions": { @@ -18,8 +19,8 @@ "0xf3 0x0f 0x52" ], "ExpectedArm64ASM": [ - "frsqrte s2, s17", - "mov v16.s[0], v2.s[0]" + "frecpe s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "rcpss xmm0, xmm1": { @@ -30,8 +31,8 @@ "0xf3 0x0f 0x53" ], "ExpectedArm64ASM": [ - "frecpe s2, s17", - "mov v16.s[0], v2.s[0]" + "frsqrte s0, s17", + "mov v16.s[0], v0.s[0]" ] } } diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json new file mode 100644 index 000000000..014b5658d --- /dev/null +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -0,0 +1,37 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "RPRES", + "AFP" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "rsqrtss xmm0, xmm1": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "AFP can make this more optimal", + "0xf3 0x0f 0x52" + ], + "ExpectedArm64ASM": [ + "frecpe s16, s17" + ] + }, + "rcpss xmm0, xmm1": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "AFP can make this more optimal", + "0xf3 0x0f 0x53" + ], + "ExpectedArm64ASM": [ + "frsqrte s16, s17" + ] + } + } +} diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1.json b/unittests/InstructionCountCI/RPRES/VEX_map1.json index 2920ae245..5384e4f28 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1.json @@ -6,7 +6,9 @@ "SVE256", "RPRES" ], - "DisabledHostFeatures": [] + "DisabledHostFeatures": [ + "AFP" + ] }, "Instructions": { "vrsqrtps xmm0, xmm1": { @@ -31,18 +33,16 @@ ] }, "vrsqrtss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "AFP can make this more optimal", "Map 1 0b10 0x52 128-bit" ], "ExpectedArm64ASM": [ - "frsqrte s2, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "frecpe s0, s18", + "mov v16.s[0], v0.s[0]" ] }, "vrcpps xmm0, xmm1": { @@ -67,17 +67,15 @@ ] }, "vrcpss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "Map 1 0b10 0x53 128-bit" ], "ExpectedArm64ASM": [ - "frecpe s2, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "frsqrte s0, s18", + "mov v16.s[0], v0.s[0]" ] } } diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json new file mode 100644 index 000000000..f87b68efc --- /dev/null +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -0,0 +1,79 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "RPRES", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "vrsqrtps xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x52 128-bit" + ], + "ExpectedArm64ASM": [ + "frsqrte v2.4s, v17.4s", + "mov v16.16b, v2.16b" + ] + }, + "vrsqrtps ymm0, ymm1": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b00 0x52 256-bit" + ], + "ExpectedArm64ASM": [ + "frsqrte z16.s, z17.s" + ] + }, + "vrsqrtss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "AFP can make this more optimal", + "Map 1 0b10 0x52 128-bit" + ], + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", + "frecpe s16, s18" + ] + }, + "vrcpps xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x53 128-bit" + ], + "ExpectedArm64ASM": [ + "frecpe v2.4s, v17.4s", + "mov v16.16b, v2.16b" + ] + }, + "vrcpps ymm0, ymm1": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b00 0x53 256-bit" + ], + "ExpectedArm64ASM": [ + "frecpe z16.s, z17.s" + ] + }, + "vrcpss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x53 128-bit" + ], + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", + "frsqrte s16, s18" + ] + } + } +} diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 718ce3f85..9c250e75e 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -135,8 +135,8 @@ ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf v2.4s, v2.4s", - "mov v16.d[0], v2.d[0]" + "scvtf v0.2s, v2.2s", + "mov v16.d[0], v0.d[0]" ] }, "cvtpi2ps xmm0, mm0": { @@ -147,8 +147,8 @@ ], "ExpectedArm64ASM": [ "ldr d2, [x28, #752]", - "scvtf v2.4s, v2.4s", - "mov v16.d[0], v2.d[0]" + "scvtf v0.2s, v2.2s", + "mov v16.d[0], v0.d[0]" ] }, "movntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index c9737cadb..92a987de6 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -6,7 +6,8 @@ ], "DisabledHostFeatures": [ "SVE128", - "SVE256" + "SVE256", + "AFP" ] }, "Instructions": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 93cc6c68d..2a395f009 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -75,8 +75,8 @@ "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf s2, w4", - "mov v16.s[0], v2.s[0]" + "scvtf s0, w4", + "mov v16.s[0], v0.s[0]" ] }, "cvtsi2ss xmm0, dword [rax]": { @@ -87,8 +87,8 @@ ], "ExpectedArm64ASM": [ "ldr s2, [x4]", - "scvtf s2, s2", - "mov v16.s[0], v2.s[0]" + "scvtf s0, s2", + "mov v16.s[0], v0.s[0]" ] }, "cvtsi2ss xmm0, rax": { @@ -96,8 +96,8 @@ "Optimal": "Yes", "Comment": "0xf3 0x0f 0x2a", "ExpectedArm64ASM": [ - "scvtf s2, x4", - "mov v16.s[0], v2.s[0]" + "scvtf s0, x4", + "mov v16.s[0], v0.s[0]" ] }, "cvtsi2ss xmm0, qword [rax]": { @@ -108,8 +108,8 @@ ], "ExpectedArm64ASM": [ "ldr x20, [x4]", - "scvtf s2, x20", - "mov v16.s[0], v2.s[0]" + "scvtf s0, x20", + "mov v16.s[0], v0.s[0]" ] }, "movntss [rax], xmm0": { @@ -194,36 +194,36 @@ }, "sqrtss xmm0, xmm1": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x51", "ExpectedArm64ASM": [ - "fsqrt s2, s17", - "mov v16.s[0], v2.s[0]" + "fsqrt s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "rsqrtss xmm0, xmm1": { "ExpectedInstructionCount": 4, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x52" ], "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", "fsqrt s1, s17", - "fdiv s2, s0, s1", - "mov v16.s[0], v2.s[0]" + "fdiv s0, s0, s1", + "mov v16.s[0], v0.s[0]" ] }, "rcpss xmm0, xmm1": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x53" ], "ExpectedArm64ASM": [ "fmov s0, #0x70 (1.0000)", - "fdiv s2, s0, s17", - "mov v16.s[0], v2.s[0]" + "fdiv s0, s0, s17", + "mov v16.s[0], v0.s[0]" ] }, "addss xmm0, xmm1": { @@ -233,8 +233,8 @@ "0xf3 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fadd s0, s16, s17", + "mov v16.s[0], v0.s[0]" ] }, "mulss xmm0, xmm1": { @@ -244,8 +244,8 @@ "0xf3 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fmul s0, s16, s17", + "mov v16.s[0], v0.s[0]" ] }, "cvtss2sd xmm0, xmm1": { @@ -253,8 +253,8 @@ "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "fcvt d2, s17", - "mov v16.d[0], v2.d[0]" + "fcvt d0, s17", + "mov v16.d[0], v0.d[0]" ] }, "cvtss2sd xmm0, [rax]": { @@ -262,9 +262,9 @@ "Optimal": "Yes", "Comment": "0xf3 0x0f 0x5a", "ExpectedArm64ASM": [ - "ldr s2, [x4]", - "fcvt d2, s2", - "mov v16.d[0], v2.d[0]" + "ldr d2, [x4]", + "fcvt d0, s2", + "mov v16.d[0], v0.d[0]" ] }, "cvttps2dq xmm0, xmm1": { @@ -282,20 +282,20 @@ "0xf3 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fsub s0, s16, s17", + "mov v16.s[0], v0.s[0]" ] }, "minss xmm0, xmm1": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5d" ], "ExpectedArm64ASM": [ "fcmp s16, s17", - "fcsel s2, s16, s17, mi", - "mov v16.s[0], v2.s[0]" + "fcsel s0, s16, s17, mi", + "mov v16.s[0], v0.s[0]" ] }, "divss xmm0, xmm1": { @@ -305,20 +305,20 @@ "0xf3 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fdiv s0, s16, s17", + "mov v16.s[0], v0.s[0]" ] }, "maxss xmm0, xmm1": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0x5f" ], "ExpectedArm64ASM": [ "fcmp s16, s17", - "fcsel s2, s17, s16, mi", - "mov v16.s[0], v2.s[0]" + "fcsel s0, s17, s16, mi", + "mov v16.s[0], v0.s[0]" ] }, "movdqu xmm0, xmm1": { @@ -580,66 +580,66 @@ }, "cmpss xmm0, xmm1, 0": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mov v16.s[0], v2.s[0]" + "fcmeq s0, s16, s17", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 1": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt s2, s17, s16", - "mov v16.s[0], v2.s[0]" + "fcmgt s0, s17, s16", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 2": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge s2, s17, s16", - "mov v16.s[0], v2.s[0]" + "fcmge s0, s17, s16", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 3": { "ExpectedInstructionCount": 5, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v16.s[0], v2.s[0]" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 4": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq s2, s16, s17", - "mvn v2.8b, v2.8b", - "mov v16.s[0], v2.s[0]" + "fcmeq s0, s16, s17", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "cmpss xmm0, xmm1, 5": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], @@ -651,7 +651,7 @@ }, "cmpss xmm0, xmm1, 6": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], @@ -663,15 +663,15 @@ }, "cmpss xmm0, xmm1, 7": { "ExpectedInstructionCount": 4, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge s0, s16, s17", "fcmgt s1, s17, s16", - "orr v2.8b, v0.8b, v1.8b", - "mov v16.s[0], v2.s[0]" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.s[0], v0.s[0]" ] }, "movq2dq xmm0, mm0": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index fbfd7542d..c9be66a7f 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -58,8 +58,8 @@ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, w4", - "mov v16.d[0], v2.d[0]" + "scvtf d0, w4", + "mov v16.d[0], v0.d[0]" ] }, "cvtsi2sd xmm0, dword [rax]": { @@ -70,8 +70,8 @@ ], "ExpectedArm64ASM": [ "ldr w20, [x4]", - "scvtf d2, w20", - "mov v16.d[0], v2.d[0]" + "scvtf d0, w20", + "mov v16.d[0], v0.d[0]" ] }, "cvtsi2sd xmm0, rax": { @@ -81,8 +81,8 @@ "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ - "scvtf d2, x4", - "mov v16.d[0], v2.d[0]" + "scvtf d0, x4", + "mov v16.d[0], v0.d[0]" ] }, "cvtsi2sd xmm0, qword [rax]": { @@ -93,8 +93,8 @@ ], "ExpectedArm64ASM": [ "ldr d2, [x4]", - "scvtf d2, d2", - "mov v16.d[0], v2.d[0]" + "scvtf d0, d2", + "mov v16.d[0], v0.d[0]" ] }, "movntsd [rax], xmm0": { @@ -179,13 +179,13 @@ }, "sqrtsd xmm0, xmm1": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x51" ], "ExpectedArm64ASM": [ - "fsqrt d2, d17", - "mov v16.d[0], v2.d[0]" + "fsqrt d0, d17", + "mov v16.d[0], v0.d[0]" ] }, "addsd xmm0, xmm1": { @@ -195,8 +195,8 @@ "0xf2 0x0f 0x58" ], "ExpectedArm64ASM": [ - "fadd d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fadd d0, d16, d17", + "mov v16.d[0], v0.d[0]" ] }, "mulsd xmm0, xmm1": { @@ -206,8 +206,8 @@ "0xf2 0x0f 0x59" ], "ExpectedArm64ASM": [ - "fmul d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fmul d0, d16, d17", + "mov v16.d[0], v0.d[0]" ] }, "cvtsd2ss xmm0, xmm1": { @@ -217,8 +217,8 @@ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "fcvt s2, d17", - "mov v16.s[0], v2.s[0]" + "fcvt s0, d17", + "mov v16.s[0], v0.s[0]" ] }, "cvtsd2ss xmm0, [rax]": { @@ -228,9 +228,9 @@ "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ - "ldr d2, [x4]", - "fcvt s2, d2", - "mov v16.s[0], v2.s[0]" + "ldr q2, [x4]", + "fcvt s0, d2", + "mov v16.s[0], v0.s[0]" ] }, "subsd xmm0, xmm1": { @@ -240,20 +240,20 @@ "0xf2 0x0f 0x5c" ], "ExpectedArm64ASM": [ - "fsub d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fsub d0, d16, d17", + "mov v16.d[0], v0.d[0]" ] }, "minsd xmm0, xmm1": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5d" ], "ExpectedArm64ASM": [ "fcmp d16, d17", - "fcsel d2, d16, d17, mi", - "mov v16.d[0], v2.d[0]" + "fcsel d0, d16, d17, mi", + "mov v16.d[0], v0.d[0]" ] }, "divsd xmm0, xmm1": { @@ -263,20 +263,20 @@ "0xf2 0x0f 0x5e" ], "ExpectedArm64ASM": [ - "fdiv d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fdiv d0, d16, d17", + "mov v16.d[0], v0.d[0]" ] }, "maxsd xmm0, xmm1": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x5f" ], "ExpectedArm64ASM": [ "fcmp d16, d17", - "fcsel d2, d17, d16, mi", - "mov v16.d[0], v2.d[0]" + "fcsel d0, d17, d16, mi", + "mov v16.d[0], v0.d[0]" ] }, "pshuflw xmm0, xmm1, 0": { @@ -396,66 +396,66 @@ }, "cmpsd xmm0, xmm1, 0": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mov v16.d[0], v2.d[0]" + "fcmeq d0, d16, d17", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 1": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmgt d2, d17, d16", - "mov v16.d[0], v2.d[0]" + "fcmgt d0, d17, d16", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 2": { "ExpectedInstructionCount": 2, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmge d2, d17, d16", - "mov v16.d[0], v2.d[0]" + "fcmge d0, d17, d16", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 3": { "ExpectedInstructionCount": 5, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v16.d[0], v2.d[0]" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 4": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ - "fcmeq d2, d16, d17", - "mvn v2.8b, v2.8b", - "mov v16.d[0], v2.d[0]" + "fcmeq d0, d16, d17", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "cmpsd xmm0, xmm1, 5": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], @@ -467,7 +467,7 @@ }, "cmpsd xmm0, xmm1, 6": { "ExpectedInstructionCount": 3, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], @@ -479,15 +479,15 @@ }, "cmpsd xmm0, xmm1, 7": { "ExpectedInstructionCount": 4, - "Optimal": "No", + "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ "fcmge d0, d16, d17", "fcmgt d1, d17, d16", - "orr v2.8b, v0.8b, v1.8b", - "mov v16.d[0], v2.d[0]" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.d[0], v0.d[0]" ] }, "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 8c1b952df..456f16898 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -673,33 +673,27 @@ ] }, "vsqrtss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ - "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b10 0x51 128-bit" ], "ExpectedArm64ASM": [ - "fsqrt s2, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsqrt s0, s18", + "mov v16.s[0], v0.s[0]" ] }, "vsqrtsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ - "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b11 0x51 128-bit" ], "ExpectedArm64ASM": [ - "fsqrt d2, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsqrt d0, d18", + "mov v16.d[0], v0.d[0]" ] }, "vrsqrtps xmm0, xmm1": { @@ -728,19 +722,17 @@ ] }, "vrsqrtss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x52 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fmov s0, #0x70 (1.0000)", "fsqrt s1, s18", - "fdiv s2, s0, s1", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s0, s0, s1", + "mov v16.s[0], v0.s[0]" ] }, "vrcpps xmm0, xmm1": { @@ -768,18 +760,16 @@ ] }, "vrcpss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x53 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fmov s0, #0x70 (1.0000)", - "fdiv s2, s0, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fdiv s0, s0, s18", + "mov v16.s[0], v0.s[0]" ] }, "vandps xmm0, xmm1": { @@ -2398,243 +2388,211 @@ ] }, "vcmpss xmm0, xmm1, xmm2, 0x00": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq s0, s17, s18", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x01": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmgt s2, s18, s17", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmgt s0, s18, s17", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x02": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmge s2, s18, s17", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmge s0, s18, s17", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x03": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge s0, s17, s18", "fcmgt s1, s18, s17", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x04": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq s2, s17, s18", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq s0, s17, s18", + "mvn v0.8b, v0.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x05": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmgt s2, s18, s17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.s[0], v2.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x06": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmge s2, s18, s17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.s[0], v2.s[0]" ] }, "vcmpss xmm0, xmm1, xmm2, 0x07": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge s0, s17, s18", "fcmgt s1, s18, s17", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.s[0], v0.s[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x00": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq d0, d17, d18", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x01": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmgt d2, d18, d17", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmgt d0, d18, d17", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x02": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmge d2, d18, d17", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmge d0, d18, d17", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x03": { - "ExpectedInstructionCount": 8, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge d0, d17, d18", "fcmgt d1, d18, d17", - "orr v2.8b, v0.8b, v1.8b", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x04": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ - "fcmeq d2, d17, d18", - "mvn v2.8b, v2.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcmeq d0, d17, d18", + "mvn v0.8b, v0.8b", + "mov v16.d[0], v0.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x05": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmgt d2, d18, d17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.d[0], v2.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x06": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ "fcmge d2, d18, d17", "mvn v2.16b, v2.16b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "mov v16.d[0], v2.d[0]" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x07": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 5, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0xC2 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmge d0, d17, d18", "fcmgt d1, d18, d17", - "orr v2.8b, v0.8b, v1.8b", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "orr v0.8b, v0.8b, v1.8b", + "mov v16.d[0], v0.d[0]" ] }, "vpinsrw xmm0, xmm1, eax, 000b": { @@ -3154,59 +3112,51 @@ ] }, "vcvtsi2ss xmm0, xmm1, eax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf s2, w4", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf s0, w4", + "mov v16.s[0], v0.s[0]" ] }, "vcvtsi2ss xmm0, xmm1, rax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf s2, x4", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf s0, x4", + "mov v16.s[0], v0.s[0]" ] }, "vcvtsi2sd xmm0, xmm1, eax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf d2, w4", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf d0, w4", + "mov v16.d[0], v0.d[0]" ] }, "vcvtsi2sd xmm0, xmm1, rax": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x2A 128-bit" ], "ExpectedArm64ASM": [ - "scvtf d2, x4", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "scvtf d0, x4", + "mov v16.d[0], v0.d[0]" ] }, "vmovntps [rax], xmm0": { @@ -3497,31 +3447,27 @@ ] }, "vaddss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x58 128-bit" ], "ExpectedArm64ASM": [ - "fadd s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fadd s0, s17, s18", + "mov v16.s[0], v0.s[0]" ] }, "vaddsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x58 128-bit" ], "ExpectedArm64ASM": [ - "fadd d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fadd d0, d17, d18", + "mov v16.d[0], v0.d[0]" ] }, "vmulps xmm0, xmm1, xmm2": { @@ -3567,31 +3513,27 @@ ] }, "vmulss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x59 128-bit" ], "ExpectedArm64ASM": [ - "fmul s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmul s0, s17, s18", + "mov v16.s[0], v0.s[0]" ] }, "vmulsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x59 128-bit" ], "ExpectedArm64ASM": [ - "fmul d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fmul d0, d17, d18", + "mov v16.d[0], v0.d[0]" ] }, "vcvtps2pd xmm0, xmm1": { @@ -3617,31 +3559,27 @@ ] }, "vcvtss2sd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5a 128-bit" ], "ExpectedArm64ASM": [ - "fcvt d2, s18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcvt d0, s18", + "mov v16.d[0], v0.d[0]" ] }, "vcvtsd2ss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5a 128-bit" ], "ExpectedArm64ASM": [ - "fcvt s2, d18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fcvt s0, d18", + "mov v16.s[0], v0.s[0]" ] }, "vcvtdq2ps xmm0, xmm1": { @@ -3752,31 +3690,27 @@ ] }, "vsubss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5c 128-bit" ], "ExpectedArm64ASM": [ - "fsub s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsub s0, s17, s18", + "mov v16.s[0], v0.s[0]" ] }, "vsubsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5c 128-bit" ], "ExpectedArm64ASM": [ - "fsub d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fsub d0, d17, d18", + "mov v16.d[0], v0.d[0]" ] }, "vminps xmm0, xmm1, xmm2": { @@ -3834,33 +3768,29 @@ ] }, "vminss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5d 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmp s17, s18", - "fcsel s2, s17, s18, mi", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcsel s0, s17, s18, mi", + "mov v16.s[0], v0.s[0]" ] }, "vminsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5d 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmp d17, d18", - "fcsel d2, d17, d18, mi", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcsel d0, d17, d18, mi", + "mov v16.d[0], v0.d[0]" ] }, "vdivps xmm0, xmm1, xmm2": { @@ -3910,31 +3840,27 @@ ] }, "vdivss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5e 128-bit" ], "ExpectedArm64ASM": [ - "fdiv s2, s17, s18", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fdiv s0, s17, s18", + "mov v16.s[0], v0.s[0]" ] }, "vdivsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 5, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5e 128-bit" ], "ExpectedArm64ASM": [ - "fdiv d2, d17, d18", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v17.16b", + "fdiv d0, d17, d18", + "mov v16.d[0], v0.d[0]" ] }, "vmaxps xmm0, xmm1, xmm2": { @@ -3990,33 +3916,29 @@ ] }, "vmaxss xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b10 0x5f 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmp s17, s18", - "fcsel s2, s18, s17, mi", - "mov v0.16b, v17.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcsel s0, s18, s17, mi", + "mov v16.s[0], v0.s[0]" ] }, "vmaxsd xmm0, xmm1, xmm2": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 4, + "Optimal": "Yes", "Comment": [ "Map 1 0b11 0x5f 128-bit" ], "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b", "fcmp d17, d18", - "fcsel d2, d18, d17, mi", - "mov v0.16b, v17.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "fcsel d0, d18, d17, mi", + "mov v16.d[0], v0.d[0]" ] }, "vpunpckhbw xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index cd5081c81..bf9e9bd8e 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -4,7 +4,9 @@ "EnabledHostFeatures": [ "SVE256" ], - "DisabledHostFeatures": [] + "DisabledHostFeatures": [ + "AFP" + ] }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 20d623967..1752d0bd3 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -1747,153 +1747,133 @@ ] }, "vroundss xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintn s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintn s0, s16", + "mov v16.s[0], v0.s[0]" ] }, "vroundss xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "-inf rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintm s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintm s0, s16", + "mov v16.s[0], v0.s[0]" ] }, "vroundss xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "+inf rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintp s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintp s0, s16", + "mov v16.s[0], v0.s[0]" ] }, "vroundss xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "truncate rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frintz s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintz s0, s16", + "mov v16.s[0], v0.s[0]" ] }, "vroundss xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "host mode rounding", "Map 3 0b01 0x0a 128-bit" ], "ExpectedArm64ASM": [ - "frinti s2, s17", - "mov v0.16b, v16.16b", - "mov v0.s[0], v2.s[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frinti s0, s16", + "mov v16.s[0], v0.s[0]" ] }, "vroundsd xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintn d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintn d0, d16", + "mov v16.d[0], v0.d[0]" ] }, "vroundsd xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "-inf rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintm d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintm d0, d16", + "mov v16.d[0], v0.d[0]" ] }, "vroundsd xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "+inf rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintp d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintp d0, d16", + "mov v16.d[0], v0.d[0]" ] }, "vroundsd xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "truncate rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frintz d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frintz d0, d16", + "mov v16.d[0], v0.d[0]" ] }, "vroundsd xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "host mode rounding", "Map 3 0b01 0x0b 128-bit" ], "ExpectedArm64ASM": [ - "frinti d2, d17", - "mov v0.16b, v16.16b", - "mov v0.d[0], v2.d[0]", - "mov v2.16b, v0.16b", - "mov v16.16b, v2.16b" + "mov v16.16b, v16.16b", + "frinti d0, d16", + "mov v16.d[0], v0.d[0]" ] }, "vblendps xmm0, xmm1, xmm2, 0000b": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 61879171a..5f71ccbda 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -5,7 +5,8 @@ "DisabledHostFeatures": [ "SVE128", "SVE256", - "CSSC" + "CSSC", + "AFP" ] }, "Instructions": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index d38a10b66..f2c513d2c 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -7,7 +7,8 @@ "EnabledHostFeatures": [], "DisabledHostFeatures": [ "SVE128", - "SVE256" + "SVE256", + "AFP" ] }, "Instructions": {