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Revert "Cache predicate register generation from pattern"

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This reverts commit 72a4063651.

Caused #4264
This commit is contained in:
Paulo Matos committed 2025-01-10 12:52:11 +01:00
1 parent a18b2d0e17
commit cbda688e29
6 files changed
+5 -41
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FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
+1 -1
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@@ -824,7 +824,7 @@ void X87StackOptimization::Run(IREmitter* Emit) {
}
if (Op->StoreSize == OpSize::f80Bit) { // Part of code from StoreResult_WithOpSize()
if (Features.SupportsSVE128 || Features.SupportsSVE256) {
auto PReg = IREmit->InitPredicateCached(OpSize::i16Bit, ARMEmitter::PredicatePattern::SVE_VL5);
auto PReg = IREmit->_InitPredicate(OpSize::i16Bit, FEXCore::ToUnderlying(ARMEmitter::PredicatePattern::SVE_VL5));
IREmit->_StoreMemPredicate(OpSize::i128Bit, OpSize::i16Bit, StackNode, PReg, AddrNode);
} else {
// For X87 extended doubles, split before storing