diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index c16779fee..26fd83e62 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -3619,19 +3619,12 @@
       "ExpectedArm64ASM": []
     },
     "pushf": {
-      "ExpectedInstructionCount": 42,
+      "ExpectedInstructionCount": 41,
       "Optimal": "No",
       "Comment": "0x9c",
       "ExpectedArm64ASM": [
         "ldr w20, [x28, #728]",
         "ubfx w21, w20, #29, #1",
-        "ldrb w22, [x28, #706]",
-        "fmov s2, w22",
-        "cnt v2.16b, v2.16b",
-        "umov w22, v2.b[0]",
-        "and x22, x22, #0x1",
-        "eor w22, w22, #0x1",
-        "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
         "ldrb w23, [x28, #706]",
         "eor w22, w22, w23",
@@ -3661,6 +3654,12 @@
         "orr x21, x21, x22, lsl #20",
         "ldrb w22, [x28, #725]",
         "orr x21, x21, x22, lsl #21",
+        "ldrb w22, [x28, #706]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
+        "orr x22, x22, #0xfffffffffffffffe",
+        "orn x21, x21, x22, ror #62",
         "and x20, x20, #0xc0000000",
         "orr x20, x21, x20, lsr #24",
         "orr x20, x20, #0x2",
@@ -3668,19 +3667,12 @@
       ]
     },
     "pushfq": {
-      "ExpectedInstructionCount": 42,
+      "ExpectedInstructionCount": 41,
       "Optimal": "No",
       "Comment": "0x9c",
       "ExpectedArm64ASM": [
         "ldr w20, [x28, #728]",
         "ubfx w21, w20, #29, #1",
-        "ldrb w22, [x28, #706]",
-        "fmov s2, w22",
-        "cnt v2.16b, v2.16b",
-        "umov w22, v2.b[0]",
-        "and x22, x22, #0x1",
-        "eor w22, w22, #0x1",
-        "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
         "ldrb w23, [x28, #706]",
         "eor w22, w22, w23",
@@ -3710,6 +3702,12 @@
         "orr x21, x21, x22, lsl #20",
         "ldrb w22, [x28, #725]",
         "orr x21, x21, x22, lsl #21",
+        "ldrb w22, [x28, #706]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
+        "orr x22, x22, #0xfffffffffffffffe",
+        "orn x21, x21, x22, ror #62",
         "and x20, x20, #0xc0000000",
         "orr x20, x21, x20, lsr #24",
         "orr x20, x20, #0x2",
@@ -3790,24 +3788,23 @@
       ]
     },
     "lahf": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 17,
       "Optimal": "Yes",
       "Comment": "0x9f",
       "ExpectedArm64ASM": [
         "ldr w20, [x28, #728]",
         "ubfx w21, w20, #29, #1",
-        "ldrb w22, [x28, #706]",
-        "fmov s2, w22",
-        "cnt v2.16b, v2.16b",
-        "umov w22, v2.b[0]",
-        "and x22, x22, #0x1",
-        "eor w22, w22, #0x1",
-        "orr x21, x21, x22, lsl #2",
         "ldrb w22, [x28, #708]",
         "ldrb w23, [x28, #706]",
         "eor w22, w22, w23",
         "ubfx w22, w22, #4, #1",
         "orr x21, x21, x22, lsl #4",
+        "ldrb w22, [x28, #706]",
+        "fmov s2, w22",
+        "cnt v2.16b, v2.16b",
+        "umov w22, v2.b[0]",
+        "orr x22, x22, #0xfffffffffffffffe",
+        "orn x21, x21, x22, ror #62",
         "and x20, x20, #0xc0000000",
         "orr x20, x21, x20, lsr #24",
         "orr x20, x20, #0x2",