From 7a06cc97273333b12587dcfdc43698217e54f13d Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 26 Sep 2023 09:06:46 -0400 Subject: [PATCH 1/2] IR: Use adcs/sbcs Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/JIT/Arm64/ALUOps.cpp | 48 ++++++++++++++++ .../Source/Interface/Core/JIT/Arm64/JIT.cpp | 2 + .../Interface/Core/JIT/Arm64/JITClass.h | 2 + .../Interface/Core/OpcodeDispatcher/Flags.cpp | 56 +++++++++++-------- FEXCore/Source/Interface/IR/IR.json | 14 +++++ 5 files changed, 98 insertions(+), 24 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 3e82539f7..48801edb0 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -103,6 +103,54 @@ DEF_OP(AddNZCV) { mrs(GetReg(Node), ARMEmitter::SystemRegister::NZCV); } +DEF_OP(AdcNZCV) { + auto Op = IROp->C(); + const IR::OpSize OpSize = Op->Size; + + LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize); + const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit; + const auto Dst = GetReg(Node); + + // TODO: Optimize this out + msr(ARMEmitter::SystemRegister::NZCV, GetReg(Op->NZCV.ID())); + + adcs(EmitSize, ARMEmitter::Reg::zr, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID())); + + // TODO: Optimize this out + mrs(Dst, ARMEmitter::SystemRegister::NZCV); +} + +DEF_OP(SbbNZCV) { + auto Op = IROp->C(); + const IR::OpSize OpSize = Op->Size; + + LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize); + const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit; + + const auto Dst = GetReg(Node); + + // Carry-in needs to be inverted for subtractions due to carry versus borrow + // distinction between x86 and arm. + // See below remarks on cfinv + eor(ARMEmitter::Size::i32Bit, TMP1, GetReg(Op->NZCV.ID()), 1u << 29); + + // TODO: Optimize this out + msr(ARMEmitter::SystemRegister::NZCV, TMP1); + + sbcs(EmitSize, ARMEmitter::Reg::zr, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID())); + + // TODO: Optimize this out + mrs(Dst, ARMEmitter::SystemRegister::NZCV); + + // The carry flag produced by arm64 sbcs is inverted compared to the x86 carry + // flag. Invert it now. + // + // TODO: Once we optimize out the mrs, this will become a cfinv operation, but + // that's only available with Feat_FlagM. For now the portable way is to flip + // bit 29 (carry) manually. + eor(ARMEmitter::Size::i32Bit, Dst, Dst, 1u << 29); +} + DEF_OP(TestNZ) { auto Op = IROp->C(); const uint8_t OpSize = Op->Size; diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index 93892c61a..41b89700d 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -794,6 +794,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, REGISTER_OP(CYCLECOUNTER, CycleCounter); REGISTER_OP(ADD, Add); REGISTER_OP(ADDNZCV, AddNZCV); + REGISTER_OP(ADCNZCV, AdcNZCV); + REGISTER_OP(SBBNZCV, SbbNZCV); REGISTER_OP(TESTNZ, TestNZ); REGISTER_OP(SUB, Sub); REGISTER_OP(SUBNZCV, SubNZCV); diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h index ca759e4d0..a02710d38 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h @@ -233,6 +233,8 @@ private: DEF_OP(CycleCounter); DEF_OP(Add); DEF_OP(AddNZCV); + DEF_OP(AdcNZCV); + DEF_OP(SbbNZCV); DEF_OP(TestNZ); DEF_OP(Sub); DEF_OP(SubNZCV); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index f7efbb7fa..e2219d739 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -515,20 +515,24 @@ void OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, Or CalculateAF(OpSize, Res, Src1, Src2); CalculatePF(Res); - // SF/ZF - SetNZ_ZeroCV(SrcSize, Res); + if (SrcSize >= 4) { + SetNZCV(_AdcNZCV(OpSize, Src1, Src2, GetNZCV())); + } else { + // SF/ZF + SetNZ_ZeroCV(SrcSize, Res); - // CF - // Unsigned - { - auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero); - auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero); - auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); - SetRFLAG(SelectCF); + // CF + // Unsigned + { + auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero); + auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero); + auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); + SetRFLAG(SelectCF); + } + + // Signed + CalculateOF(SrcSize, Res, Src1, Src2, false); } - - // Signed - CalculateOF(SrcSize, Res, Src1, Src2, false); } void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) { @@ -539,20 +543,24 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or CalculateAF(OpSize, Res, Src1, Src2); CalculatePF(Res); - // SF/ZF - SetNZ_ZeroCV(SrcSize, Res); + if (SrcSize >= 4) { + SetNZCV(_SbbNZCV(OpSize, Src1, Src2, GetNZCV())); + } else { + // SF/ZF + SetNZ_ZeroCV(SrcSize, Res); - // CF - // Unsigned - { - auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero); - auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero); - auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); - SetRFLAG(SelectCF); + // CF + // Unsigned + { + auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero); + auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero); + auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); + SetRFLAG(SelectCF); + } + + // Signed + CalculateOF(SrcSize, Res, Src1, Src2, true); } - - // Signed - CalculateOF(SrcSize, Res, Src1, Src2, true); } void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) { diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 311307e79..08e1c93c4 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -907,6 +907,20 @@ "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" ] }, + "GPR = AdcNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2, GPR:$NZCV": { + "Desc": ["Return NZCV for the sum of two GPRs and carry-in given as NZCV"], + "DestSize": "4", + "EmitValidation": [ + "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" + ] + }, + "GPR = SbbNZCV OpSize:$Size, GPR:$Src1, GPR:$Src2, GPR:$NZCV": { + "Desc": ["Return NZCV for the sum of two GPRs and carry-in given as NZCV"], + "DestSize": "4", + "EmitValidation": [ + "_Size == FEXCore::IR::OpSize::i32Bit || _Size == FEXCore::IR::OpSize::i64Bit" + ] + }, "GPR = Sub OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": [ "Integer Sub", "Will truncate to 64 or 32bits" From 7b22dbfe24e979dc52a8bf3e69156701ca6a5f06 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 26 Sep 2023 10:05:59 -0400 Subject: [PATCH 2/2] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/Primary.json | 388 ++++++----------- .../InstructionCountCI/PrimaryGroup.json | 396 ++++++------------ 2 files changed, 256 insertions(+), 528 deletions(-) diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 97301d05d..22257edc1 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -640,63 +640,41 @@ ] }, "adc ebx, ecx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "0x11", "ExpectedArm64ASM": [ "mov w20, w5", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w7", "add w7, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w7, [x28, #706]", - "tst w7, w7", - "mrs x22, nzcv", - "cmp w7, w20", - "cset x24, lo", - "cmp w7, w20", - "cset x25, ls", - "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w22, w21, lsl #29", - "eor w20, w23, w20", - "eor w22, w7, w23", - "bic w20, w22, w20", - "lsr w20, w20, #31", - "orr w20, w21, w20, lsl #28", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "adc rbx, rcx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "0x11", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "add x21, x5, x20", + "ubfx w21, w20, #29, #1", + "add x21, x5, x21", "mov x22, x7", "add x7, x22, x21", "eor x21, x22, x5", "strb w21, [x28, #708]", "strb w7, [x28, #706]", - "tst x7, x7", - "mrs x21, nzcv", - "cmp x7, x5", - "cset x23, lo", - "cmp x7, x5", - "cset x24, ls", - "cmp x20, #0x1 (1)", - "csel x20, x24, x23, eq", - "orr w20, w21, w20, lsl #29", - "eor x21, x22, x5", - "eor x22, x7, x22", - "bic x21, x22, x21", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x20", + "adcs xzr, x22, x5", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -775,7 +753,7 @@ ] }, "db 0x13, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": [ "0x13", @@ -784,32 +762,21 @@ "ExpectedArm64ASM": [ "mov w20, w7", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w5", "add w5, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w5, [x28, #706]", - "tst w5, w5", - "mrs x22, nzcv", - "cmp w5, w20", - "cset x24, lo", - "cmp w5, w20", - "cset x25, ls", - "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w22, w21, lsl #29", - "eor w20, w23, w20", - "eor w22, w5, w23", - "bic w20, w22, w20", - "lsr w20, w20, #31", - "orr w20, w21, w20, lsl #28", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "db 0x48, 0x13, 0xcb": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": [ "0x13", @@ -817,27 +784,16 @@ ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "add x21, x7, x20", + "ubfx w21, w20, #29, #1", + "add x21, x7, x21", "mov x22, x5", "add x5, x22, x21", "eor x21, x22, x7", "strb w21, [x28, #708]", "strb w5, [x28, #706]", - "tst x5, x5", - "mrs x21, nzcv", - "cmp x5, x7", - "cset x23, lo", - "cmp x5, x7", - "cset x24, ls", - "cmp x20, #0x1 (1)", - "csel x20, x24, x23, eq", - "orr w20, w21, w20, lsl #29", - "eor x21, x22, x7", - "eor x22, x5, x22", - "bic x21, x22, x21", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x20", + "adcs xzr, x22, x7", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -904,58 +860,40 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "add w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "msr nzcv, x21", + "adcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, #0x1 (1)", - "cset x23, lo", - "cmp w4, #0x1 (1)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w22", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "add x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "msr nzcv, x21", + "adcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, #0x1 (1)", - "cset x23, lo", - "cmp x4, #0x1 (1)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x22", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, @@ -1024,61 +962,43 @@ ] }, "adc eax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffff", "movk w20, #0xffff, lsl #16", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w4", "add w4, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", - "mrs x22, nzcv", - "cmp w4, w20", - "cset x24, lo", - "cmp w4, w20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic w21, w23, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x22, x20, x21", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", "mov x23, x4", "add x4, x23, x22", "eor x22, x23, x20", "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", - "mrs x22, nzcv", - "cmp x4, x20", - "cset x24, lo", - "cmp x4, x20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic x21, x23, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1151,63 +1071,45 @@ ] }, "sbb ebx, ecx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 15, "Optimal": "No", "Comment": "0x19", "ExpectedArm64ASM": [ "mov w20, w5", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w7", "sub w7, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w7, [x28, #706]", - "tst w7, w7", - "mrs x22, nzcv", - "cmp w7, w23", - "cset x24, hi", - "cmp w7, w23", - "cset x25, hs", - "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w22, w21, lsl #29", - "eor w20, w23, w20", - "eor w22, w7, w23", - "and w20, w22, w20", - "lsr w20, w20, #31", - "orr w20, w21, w20, lsl #28", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rbx, rcx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0x19", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "add x21, x5, x20", + "ubfx w21, w20, #29, #1", + "add x21, x5, x21", "mov x22, x7", "sub x7, x22, x21", "eor x21, x22, x5", "strb w21, [x28, #708]", "strb w7, [x28, #706]", - "tst x7, x7", - "mrs x21, nzcv", - "cmp x7, x22", - "cset x23, hi", - "cmp x7, x22", - "cset x24, hs", - "cmp x20, #0x1 (1)", - "csel x20, x24, x23, eq", - "orr w20, w21, w20, lsl #29", - "eor x21, x22, x5", - "eor x22, x7, x22", - "and x21, x22, x21", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w0, w20, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x22, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -1286,7 +1188,7 @@ ] }, "db 0x1B, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 15, "Optimal": "No", "Comment": [ "0x1B", @@ -1295,32 +1197,23 @@ "ExpectedArm64ASM": [ "mov w20, w7", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w5", "sub w5, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w5, [x28, #706]", - "tst w5, w5", - "mrs x22, nzcv", - "cmp w5, w23", - "cset x24, hi", - "cmp w5, w23", - "cset x25, hs", - "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w22, w21, lsl #29", - "eor w20, w23, w20", - "eor w22, w5, w23", - "and w20, w22, w20", - "lsr w20, w20, #31", - "orr w20, w21, w20, lsl #28", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "db 0x48, 0x1B, 0xcb": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0x1B", @@ -1328,27 +1221,18 @@ ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "add x21, x7, x20", + "ubfx w21, w20, #29, #1", + "add x21, x7, x21", "mov x22, x5", "sub x5, x22, x21", "eor x21, x22, x7", "strb w21, [x28, #708]", "strb w5, [x28, #706]", - "tst x5, x5", - "mrs x21, nzcv", - "cmp x5, x22", - "cset x23, hi", - "cmp x5, x22", - "cset x24, hs", - "cmp x20, #0x1 (1)", - "csel x20, x24, x23, eq", - "orr w20, w21, w20, lsl #29", - "eor x21, x22, x7", - "eor x22, x5, x22", - "and x21, x22, x21", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w0, w20, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x22, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -1415,58 +1299,44 @@ ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "sub w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w22", - "cset x23, hi", - "cmp w4, w22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w22, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "sub x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x22", - "cset x23, hi", - "cmp x4, x22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x22, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -1535,61 +1405,47 @@ ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 16, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "movk w20, #0xffff, lsl #16", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w4", "sub w4, w23, w22", - "eor w20, w23, w20", - "strb w20, [x28, #708]", + "eor w22, w23, w20", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w23", - "cset x22, hi", - "cmp w4, w23", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x22, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w23", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 15, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x22, x20, x21", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", "mov x23, x4", "sub x4, x23, x22", - "eor x20, x23, x20", - "strb w20, [x28, #708]", + "eor x22, x23, x20", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x23", - "cset x22, hi", - "cmp x4, x23", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x22, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x23", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index efd4c4dae..bc887a7e3 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -430,114 +430,82 @@ ] }, "adc eax, 256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "add w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "msr nzcv, x21", + "adcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, #0x100 (256)", - "cset x23, lo", - "cmp w4, #0x100 (256)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w22", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, "adc rax, 256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "add x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "msr nzcv, x21", + "adcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, #0x100 (256)", - "cset x23, lo", - "cmp x4, #0x100 (256)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x22", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "sub w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w22", - "cset x23, hi", - "cmp w4, w22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w22, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "sub x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x22", - "cset x23, hi", - "cmp x4, x22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x22, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -728,114 +696,82 @@ ] }, "adc eax, -256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "orr w20, wzr, #0xffffff00", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w4", "add w4, w23, w22", "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", - "mrs x22, nzcv", - "cmp w4, w20", - "cset x24, lo", - "cmp w4, w20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic w21, w23, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "adc rax, -256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x22, x20, x21", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", "mov x23, x4", "add x4, x23, x22", "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", - "mrs x22, nzcv", - "cmp x4, x20", - "cset x24, lo", - "cmp x4, x20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic x21, x23, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "sbb eax, -256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "orr w20, wzr, #0xffffff00", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "sub w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w22", - "cset x23, hi", - "cmp w4, w22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w22", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, -256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "sub x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x22", - "cset x23, hi", - "cmp x4, x22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x22", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -1027,114 +963,82 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "add w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "msr nzcv, x21", + "adcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, #0x1 (1)", - "cset x23, lo", - "cmp w4, #0x1 (1)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w22", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "add x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "msr nzcv, x21", + "adcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, #0x1 (1)", - "cset x23, lo", - "cmp x4, #0x1 (1)", - "cset x24, ls", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x22", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", "str w20, [x28, #728]" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w20, w20, w21", - "mov w22, w4", - "sub w4, w22, w20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w22", - "cset x23, hi", - "cmp w4, w22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w22, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x20, x20, x21", - "mov x22, x4", - "sub x4, x22, x20", - "strb w22, [x28, #708]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x22", - "cset x23, hi", - "cmp x4, x22", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x23, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x22, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, @@ -1332,120 +1236,88 @@ ] }, "adc eax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", "movk w20, #0xffff, lsl #16", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w4", "add w4, w23, w22", "eor w22, w23, w20", "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", - "mrs x22, nzcv", - "cmp w4, w20", - "cset x24, lo", - "cmp w4, w20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic w21, w23, w4", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x22, x20, x21", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", "mov x23, x4", "add x4, x23, x22", "eor x22, x23, x20", "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", - "mrs x22, nzcv", - "cmp x4, x20", - "cset x24, lo", - "cmp x4, x20", - "cset x20, ls", - "cmp x21, #0x1 (1)", - "csel x20, x20, x24, eq", - "orr w20, w22, w20, lsl #29", - "bic x21, x23, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 16, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", "movk w20, #0xffff, lsl #16", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add w22, w20, w21", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", "mov w23, w4", "sub w4, w23, w22", - "eor w20, w23, w20", - "strb w20, [x28, #708]", + "eor w22, w23, w20", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst w4, w4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", "mrs x20, nzcv", - "cmp w4, w23", - "cset x22, hi", - "cmp w4, w23", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x22, eq", - "orr w20, w20, w21, lsl #29", - "bic w21, w4, w23", - "lsr w21, w21, #31", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 15, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldr w21, [x28, #728]", - "ubfx w21, w21, #29, #1", - "add x22, x20, x21", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", "mov x23, x4", "sub x4, x23, x22", - "eor x20, x23, x20", - "strb w20, [x28, #708]", + "eor x22, x23, x20", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", - "tst x4, x4", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", "mrs x20, nzcv", - "cmp x4, x23", - "cset x22, hi", - "cmp x4, x23", - "cset x24, hs", - "cmp x21, #0x1 (1)", - "csel x21, x24, x22, eq", - "orr w20, w20, w21, lsl #29", - "bic x21, x4, x23", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "eor w20, w20, #0x20000000", "str w20, [x28, #728]" ] },