diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json new file mode 100644 index 000000000..50fc5f020 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -0,0 +1,134 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "AFP" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "roundss xmm0, xmm1, 00000000b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Nearest rounding", + "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "frintn s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "roundss xmm0, xmm1, 00000001b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "-inf rounding", + "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "frintm s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "roundss xmm0, xmm1, 00000010b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "+inf rounding", + "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "frintp s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "roundss xmm0, xmm1, 00000011b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "truncate rounding", + "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "frintz s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "roundss xmm0, xmm1, 00000100b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "host rounding mode rounding", + "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "frinti s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "roundsd xmm0, xmm1, 00000000b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Nearest rounding", + "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "frintn d2, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "roundsd xmm0, xmm1, 00000001b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "-inf rounding", + "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "frintm d2, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "roundsd xmm0, xmm1, 00000010b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "+inf rounding", + "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "frintp d2, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "roundsd xmm0, xmm1, 00000011b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "truncate rounding", + "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "frintz d2, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "roundsd xmm0, xmm1, 00000100b": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "host rounding mode rounding", + "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "frinti d2, d17", + "mov v16.d[0], v2.d[0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json new file mode 100644 index 000000000..72e0962e5 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -0,0 +1,43 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "cvtpi2ps xmm0, [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "scvtf v2.4s, v2.4s", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtpi2ps xmm0, mm0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "scvtf v2.4s, v2.4s", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json new file mode 100644 index 000000000..93370e686 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -0,0 +1,333 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "cvtsi2ss xmm0, eax": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf s2, w4", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsi2ss xmm0, dword [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x4]", + "scvtf s2, s2", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsi2ss xmm0, qword [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x4]", + "scvtf s2, x20", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "sqrtss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0xf3 0x0f 0x51", + "ExpectedArm64ASM": [ + "fsqrt s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "rsqrtss xmm0, xmm1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "0xf3 0x0f 0x52" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s17", + "fdiv s2, s0, s1", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "rcpss xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "0xf3 0x0f 0x53" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fdiv s2, s0, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "addss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd s2, s16, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "mulss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul s2, s16, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtss2sd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "fcvt d2, s17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtss2sd xmm0, [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "ldr s2, [x4]", + "fcvt d2, s2", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "subss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub s2, s16, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "minss xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "fcsel s2, s16, s17, mi", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "divss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv s2, s16, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "maxss xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "fcsel s2, s17, s16, mi", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s16, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s17, s16", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s17, s16", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 3": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s16, s17", + "fcmgt s1, s17, s16", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 4": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s16, s17", + "mvn v2.8b, v2.8b", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 5": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s17, s16", + "mvn v2.16b, v2.16b", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 6": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s17, s16", + "mvn v2.16b, v2.16b", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpss xmm0, xmm1, 7": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s16, s17", + "fcmgt s1, s17, s16", + "orr v2.8b, v0.8b, v1.8b", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json new file mode 100644 index 000000000..ef33ba0e2 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -0,0 +1,320 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "cvtsi2sd xmm0, eax": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf d2, w4", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsi2sd xmm0, dword [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsi2sd xmm0, rax": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf d2, x4", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsi2sd xmm0, qword [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "scvtf d2, d2", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "sqrtsd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x51" + ], + "ExpectedArm64ASM": [ + "fsqrt d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "addsd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd d2, d16, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "mulsd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul d2, d16, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsd2ss xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "fcvt s2, d17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cvtsd2ss xmm0, [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "fcvt s2, d2", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "subsd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub d2, d16, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "minsd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "fcsel d2, d16, d17, mi", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "divsd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv d2, d16, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "maxsd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "fcsel d2, d17, d16, mi", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d16, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d17, d16", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d17, d16", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 3": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d16, d17", + "fcmgt d1, d17, d16", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 4": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d16, d17", + "mvn v2.8b, v2.8b", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 5": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d17, d16", + "mvn v2.16b, v2.16b", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 6": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d17, d16", + "mvn v2.16b, v2.16b", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "cmpsd xmm0, xmm1, 7": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d16, d17", + "fcmgt d1, d17, d16", + "orr v2.8b, v0.8b, v1.8b", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json new file mode 100644 index 000000000..1f3cb6f91 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -0,0 +1,38 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "AFP" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "cvtpi2ps xmm0, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "scvtf v2.4s, v2.4s", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtpi2ps xmm0, mm0": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "scvtf v2.4s, v2.4s", + "mov v16.d[0], v2.d[0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json new file mode 100644 index 000000000..194a16464 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -0,0 +1,268 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "AFP" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "cvtsi2ss xmm0, eax": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf s2, w4", + "mov v16.s[0], v2.s[0]" + ] + }, + "cvtsi2ss xmm0, dword [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr s2, [x4]", + "scvtf s2, s2", + "mov v16.s[0], v2.s[0]" + ] + }, + "cvtsi2ss xmm0, qword [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x4]", + "scvtf s2, x20", + "mov v16.s[0], v2.s[0]" + ] + }, + "sqrtss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": "0xf3 0x0f 0x51", + "ExpectedArm64ASM": [ + "fsqrt s2, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "rsqrtss xmm0, xmm1": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "0xf3 0x0f 0x52" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s17", + "fdiv s2, s0, s1", + "mov v16.s[0], v2.s[0]" + ] + }, + "rcpss xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "0xf3 0x0f 0x53" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fdiv s2, s0, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "addss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd s2, s16, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "mulss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul s2, s16, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "cvtss2sd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "fcvt d2, s17", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtss2sd xmm0, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "ldr s2, [x4]", + "fcvt d2, s2", + "mov v16.d[0], v2.d[0]" + ] + }, + "subss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub s2, s16, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "minss xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "fcsel s2, s16, s17, mi", + "mov v16.s[0], v2.s[0]" + ] + }, + "divss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv s2, s16, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "maxss xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf3 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "fcsel s2, s17, s16, mi", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s16, s17", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s17, s16", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 2": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s17, s16", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 3": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s16, s17", + "fcmgt s1, s17, s16", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 4": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s16, s17", + "mvn v2.8b, v2.8b", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 5": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s17, s16", + "mvn v2.16b, v2.16b", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 6": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s17, s16", + "mvn v2.16b, v2.16b", + "mov v16.s[0], v2.s[0]" + ] + }, + "cmpss xmm0, xmm1, 7": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s16, s17", + "fcmgt s1, s17, s16", + "orr v2.8b, v0.8b, v1.8b", + "mov v16.s[0], v2.s[0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json new file mode 100644 index 000000000..4054feb4c --- /dev/null +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -0,0 +1,258 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "AFP" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "cvtsi2sd xmm0, eax": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf d2, w4", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtsi2sd xmm0, dword [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d2, w20", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtsi2sd xmm0, rax": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf d2, x4", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtsi2sd xmm0, qword [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "scvtf d2, d2", + "mov v16.d[0], v2.d[0]" + ] + }, + "sqrtsd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x51" + ], + "ExpectedArm64ASM": [ + "fsqrt d2, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "addsd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd d2, d16, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "mulsd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul d2, d16, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "cvtsd2ss xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "fcvt s2, d17", + "mov v16.s[0], v2.s[0]" + ] + }, + "cvtsd2ss xmm0, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "fcvt s2, d2", + "mov v16.s[0], v2.s[0]" + ] + }, + "subsd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub d2, d16, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "minsd xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "fcsel d2, d16, d17, mi", + "mov v16.d[0], v2.d[0]" + ] + }, + "divsd xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv d2, d16, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "maxsd xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": [ + "0xf2 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "fcsel d2, d17, d16, mi", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d16, d17", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d17, d16", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 2": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d17, d16", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 3": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d16, d17", + "fcmgt d1, d17, d16", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 4": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d16, d17", + "mvn v2.8b, v2.8b", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 5": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d17, d16", + "mvn v2.16b, v2.16b", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 6": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d17, d16", + "mvn v2.16b, v2.16b", + "mov v16.d[0], v2.d[0]" + ] + }, + "cmpsd xmm0, xmm1, 7": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d16, d17", + "fcmgt d1, d17, d16", + "orr v2.8b, v0.8b, v1.8b", + "mov v16.d[0], v2.d[0]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json new file mode 100644 index 000000000..bd97d9c80 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -0,0 +1,542 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "vsqrtss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "fsqrt s2, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vsqrtsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "fsqrt d2, d18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vrsqrtss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b10 0x52 128-bit" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s18", + "fdiv s2, s0, s1", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vrcpss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b10 0x53 128-bit" + ], + "ExpectedArm64ASM": [ + "fmov s0, #0x70 (1.0000)", + "fdiv s2, s0, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s17, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s18, s17", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s18, s17", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s17, s18", + "fcmgt s1, s18, s17", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmeq s2, s17, s18", + "mvn v2.8b, v2.8b", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmgt s2, s18, s17", + "mvn v2.16b, v2.16b", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge s2, s18, s17", + "mvn v2.16b, v2.16b", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge s0, s17, s18", + "fcmgt s1, s18, s17", + "orr v2.8b, v0.8b, v1.8b", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d17, d18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d18, d17", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d18, d17", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d17, d18", + "fcmgt d1, d18, d17", + "orr v2.8b, v0.8b, v1.8b", + "mvn v2.8b, v2.8b", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmeq d2, d17, d18", + "mvn v2.8b, v2.8b", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmgt d2, d18, d17", + "mvn v2.16b, v2.16b", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge d2, d18, d17", + "mvn v2.16b, v2.16b", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmge d0, d17, d18", + "fcmgt d1, d18, d17", + "orr v2.8b, v0.8b, v1.8b", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtsi2ss xmm0, xmm1, eax": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "scvtf s2, w4", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtsi2ss xmm0, xmm1, rax": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "scvtf s2, x4", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtsi2sd xmm0, xmm1, eax": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "scvtf d2, w4", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtsi2sd xmm0, xmm1, rax": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "scvtf d2, x4", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vmulss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "fmul s2, s17, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vmulsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "fmul d2, d17, d18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtss2sd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "fcvt d2, s18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vcvtsd2ss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "fcvt s2, d18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vsubss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "fsub s2, s17, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vsubsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "fsub d2, d17, d18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vminss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp s17, s18", + "fcsel s2, s17, s18, mi", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vminsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp d17, d18", + "fcsel d2, d17, d18, mi", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vdivss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "fdiv s2, s17, s18", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vdivsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "fdiv d2, d17, d18", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vmaxss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b10 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp s17, s18", + "fcsel s2, s18, s17, mi", + "mov v0.16b, v17.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vmaxsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b11 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp d17, d18", + "fcsel d2, d18, d17, mi", + "mov v0.16b, v17.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + } + } +} diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json new file mode 100644 index 000000000..bc5f36627 --- /dev/null +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -0,0 +1,163 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "vroundss xmm0, xmm1, 00000000b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "nearest rounding", + "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "frintn s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundss xmm0, xmm1, 00000001b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "-inf rounding", + "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "frintm s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundss xmm0, xmm1, 00000010b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "+inf rounding", + "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "frintp s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundss xmm0, xmm1, 00000011b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "truncate rounding", + "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "frintz s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundss xmm0, xmm1, 00000100b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "host mode rounding", + "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "frinti s2, s17", + "mov v0.16b, v16.16b", + "mov v0.s[0], v2.s[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundsd xmm0, xmm1, 00000000b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "nearest rounding", + "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "frintn d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundsd xmm0, xmm1, 00000001b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "-inf rounding", + "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "frintm d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundsd xmm0, xmm1, 00000010b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "+inf rounding", + "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "frintp d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundsd xmm0, xmm1, 00000011b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "truncate rounding", + "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "frintz d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + }, + "vroundsd xmm0, xmm1, 00000100b": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "host mode rounding", + "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "frinti d2, d17", + "mov v0.16b, v16.16b", + "mov v0.d[0], v2.d[0]", + "mov v2.16b, v0.16b", + "mov v16.16b, v2.16b" + ] + } + } +} diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 9ec45c218..a35a1b717 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -4,7 +4,8 @@ "EnabledHostFeatures": [], "DisabledHostFeatures": [ "SVE128", - "SVE256" + "SVE256", + "AFP" ] }, "Comment": [ diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json new file mode 100644 index 000000000..7311b8d7d --- /dev/null +++ b/unittests/InstructionCountCI/Repeat.json @@ -0,0 +1,11 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": {} +} diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 1c2aef26a..718ce3f85 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -5,7 +5,8 @@ "DisabledHostFeatures": [ "SVE128", "SVE256", - "RPRES" + "RPRES", + "AFP" ] }, "Comment": [ @@ -130,7 +131,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -143,7 +143,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0x0f 0x2a" ], "ExpectedArm64ASM": [ diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 7fdc82fa4..93cc6c68d 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -5,7 +5,8 @@ "DisabledHostFeatures": [ "SVE128", "SVE256", - "RPRES" + "RPRES", + "AFP" ] }, "Instructions": { @@ -71,7 +72,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -83,7 +83,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -105,7 +104,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -232,7 +230,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x58" ], "ExpectedArm64ASM": [ @@ -244,7 +241,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x59" ], "ExpectedArm64ASM": [ @@ -283,7 +279,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5c" ], "ExpectedArm64ASM": [ @@ -295,7 +290,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5d" ], "ExpectedArm64ASM": [ @@ -308,7 +302,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5e" ], "ExpectedArm64ASM": [ @@ -320,7 +313,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5f" ], "ExpectedArm64ASM": [ @@ -590,7 +582,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -602,7 +593,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -614,7 +604,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -626,7 +615,6 @@ "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -641,7 +629,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -654,7 +641,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -667,7 +653,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -680,7 +665,6 @@ "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" ], "ExpectedArm64ASM": [ diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 16c435991..fbfd7542d 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -5,7 +5,8 @@ "DisabledHostFeatures": [ "SVE128", "SVE256", - "FCMA" + "FCMA", + "AFP" ] }, "Instructions": { @@ -54,7 +55,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -66,7 +66,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -79,7 +78,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -91,7 +89,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" ], "ExpectedArm64ASM": [ @@ -184,7 +181,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x51" ], "ExpectedArm64ASM": [ @@ -196,7 +192,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x58" ], "ExpectedArm64ASM": [ @@ -208,7 +203,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x59" ], "ExpectedArm64ASM": [ @@ -220,7 +214,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ @@ -232,7 +225,6 @@ "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5a" ], "ExpectedArm64ASM": [ @@ -245,7 +237,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5c" ], "ExpectedArm64ASM": [ @@ -257,7 +248,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5d" ], "ExpectedArm64ASM": [ @@ -270,7 +260,6 @@ "ExpectedInstructionCount": 2, "Optimal": "Yes", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5e" ], "ExpectedArm64ASM": [ @@ -282,7 +271,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5f" ], "ExpectedArm64ASM": [ @@ -410,7 +398,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -422,7 +409,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -434,7 +420,6 @@ "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -446,7 +431,6 @@ "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -461,7 +445,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -474,7 +457,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -487,7 +469,6 @@ "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ @@ -500,7 +481,6 @@ "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ - "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" ], "ExpectedArm64ASM": [ diff --git a/unittests/InstructionCountCI/Test.json b/unittests/InstructionCountCI/Test.json new file mode 100644 index 000000000..519aab97e --- /dev/null +++ b/unittests/InstructionCountCI/Test.json @@ -0,0 +1,27 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "push ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x50", + "x86Insts": [ + "push ax", + "push bx" + ], + "ExpectedArm64ASM": [ + "uxth w20, w4", + "strh w20, [x8, #-2]!", + "uxth w20, w7", + "strh w20, [x8, #-2]!" + ] + } + } +} diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index af9678547..8c1b952df 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -7,7 +7,8 @@ ], "DisabledHostFeatures": [ "FCMA", - "RPRES" + "RPRES", + "AFP" ] }, "Instructions": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index d8a39ee2e..20d623967 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -4,7 +4,9 @@ "EnabledHostFeatures": [ "SVE256" ], - "DisabledHostFeatures": [] + "DisabledHostFeatures": [ + "AFP" + ] }, "Instructions": { "vpermq ymm0, ymm1, 00000000b": {