From c3c68afc3c38d9bc33db28bff7f430734cd877ab Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 8 Jan 2023 13:23:40 -0800 Subject: [PATCH] Arm64: Fixes incorrect sign extension We were accidentally zero extending. --- External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index 291b5d7f6..dd0ff6cd2 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -163,7 +163,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { const auto Src1 = GetReg(IROp->Args[0].ID()); if (Info.ABI == FABI_F80_I16) { - uxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); + sxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); } else { mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); @@ -310,7 +310,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { FillStaticRegs(); const auto Dst = GetReg(Node); - uxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); + sxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; case FABI_I32_F80:{