From c2beb27a9d0cf4e0bb1173bbef40af040ddc2d83 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 19 Jun 2024 06:52:58 -0700 Subject: [PATCH] AVX128: Implement support for vpalignr --- .../Source/Interface/Core/OpcodeDispatcher.h | 1 + .../Core/OpcodeDispatcher/AVX_128.cpp | 21 ++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 9aabf7e42..f7ba25428 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1178,6 +1178,7 @@ public: void AVX128_VPSADBW(OpcodeArgs); void AVX128_VMPSADBW(OpcodeArgs); + void AVX128_VPALIGNR(OpcodeArgs); // End of AVX 128-bit implementation diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 9fbc0adf8..2cd455165 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -346,7 +346,7 @@ void OpDispatchBuilder::InstallAVX128Handlers() { {OPD(3, 0b01, 0x0C), 1, &OpDispatchBuilder::AVX128_VBLEND}, {OPD(3, 0b01, 0x0D), 1, &OpDispatchBuilder::AVX128_VBLEND}, {OPD(3, 0b01, 0x0E), 1, &OpDispatchBuilder::AVX128_VBLEND}, - // TODO: {OPD(3, 0b01, 0x0F), 1, &OpDispatchBuilder::VPALIGNROp}, + {OPD(3, 0b01, 0x0F), 1, &OpDispatchBuilder::AVX128_VPALIGNR}, {OPD(3, 0b01, 0x14), 1, &OpDispatchBuilder::AVX128_PExtr<1>}, {OPD(3, 0b01, 0x15), 1, &OpDispatchBuilder::AVX128_PExtr<2>}, @@ -1917,4 +1917,23 @@ void OpDispatchBuilder::AVX128_VMPSADBW(OpcodeArgs) { AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result); } +void OpDispatchBuilder::AVX128_VPALIGNR(OpcodeArgs) { + const auto Index = Op->Src[2].Literal(); + const auto Size = GetDstSize(Op); + const auto SanitizedDstSize = std::min(Size, uint8_t {16}); + + AVX128_VectorBinaryImpl(Op, Size, OpSize::i8Bit, [this, Index, SanitizedDstSize](size_t, Ref Src1, Ref Src2) -> Ref { + if (Index >= (SanitizedDstSize * 2)) { + // If the immediate is greater than both vectors combined then it zeroes the vector + return LoadZeroVector(OpSize::i128Bit); + } + + if (Index == 0) { + return Src2; + } + + return _VExtr(OpSize::i128Bit, OpSize::i8Bit, Src1, Src2, Index); + }); +} + } // namespace FEXCore::IR