diff --git a/FEXCore/include/FEXCore/Core/HostFeatures.h b/FEXCore/include/FEXCore/Core/HostFeatures.h
index f1ade4e99..8d70eddf5 100644
--- a/FEXCore/include/FEXCore/Core/HostFeatures.h
+++ b/FEXCore/include/FEXCore/Core/HostFeatures.h
@@ -37,6 +37,7 @@ struct HostFeatures {
   bool SupportsSVEBitPerm {};
   bool SupportsCPUIndexInTPIDRRO {};
   bool SupportsFRINTTS {};
+  bool SupportsECV {};
 
   // Float exception behaviour
   bool SupportsAFP {};
diff --git a/Source/Common/HostFeatures.cpp b/Source/Common/HostFeatures.cpp
index f94b8d714..d40cc8de5 100644
--- a/Source/Common/HostFeatures.cpp
+++ b/Source/Common/HostFeatures.cpp
@@ -483,6 +483,7 @@ FEXCore::HostFeatures FetchHostFeatures(FEX::CPUFeatures& Features, bool Support
   HostFeatures.SupportsFRINTTS = Features.Supports(CPUFeatures::Feature::FRINTTS);
   HostFeatures.SupportsRPRES = Features.Supports(CPUFeatures::Feature::RPRES);
   HostFeatures.SupportsSVEBitPerm = Features.Supports(CPUFeatures::Feature::SVE_BitPerm);
+  HostFeatures.SupportsECV = Features.Supports(CPUFeatures::Feature::ECV);
 
 #ifdef VIXL_SIMULATOR
   // Hardcode enable SVE with 256-bit wide registers.