diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
index 3f7306ad0..4c0f7dc6c 100644
--- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
@@ -83,174 +83,100 @@
       ]
     },
     "daa": {
-      "ExpectedInstructionCount": 49,
+      "ExpectedInstructionCount": 21,
       "Comment": "0x27",
       "ExpectedArm64ASM": [
-        "mov w20, #0x0",
-        "cset w21, hs",
-        "eor w22, w27, w26",
-        "ubfx w22, w22, #4, #1",
-        "uxtb w23, w4",
-        "rmif x20, #63, #nzCv",
-        "and x20, x23, #0xf",
-        "mrs x24, nzcv",
-        "cmp x20, #0x9 (9)",
-        "cset x20, hi",
-        "orr x20, x22, x20",
-        "msr nzcv, x24",
-        "cbnz x20, #+0xc",
-        "mov w27, #0x0",
-        "b #+0x1c",
-        "add x20, x23, #0x6 (6)",
-        "bfxil w4, w20, #0, #8",
-        "cset w20, hs",
-        "orr x20, x21, x20",
-        "rmif x20, #63, #nzCv",
-        "mov w27, #0x10",
-        "mrs x20, nzcv",
-        "cmp x23, #0x99 (153)",
-        "cset x22, hi",
-        "orr x21, x21, x22",
-        "msr nzcv, x20",
-        "cbnz x21, #+0x10",
-        "mov w20, #0x0",
-        "rmif x20, #63, #nzCv",
-        "b #+0x18",
         "uxtb w20, w4",
-        "add x20, x20, #0x60 (96)",
-        "bfxil w4, w20, #0, #8",
-        "mov w20, #0x1",
-        "rmif x20, #63, #nzCv",
-        "uxtb w26, w4",
-        "and x20, x26, #0x80",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, hs",
-        "msr nzcv, x21",
-        "rmif x20, #61, #Nzcv",
-        "and x20, x26, #0xff",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
-        "msr nzcv, x21",
-        "rmif x20, #62, #nZcv",
-        "eor w27, w27, w26"
+        "cset w21, hs",
+        "and x22, x20, #0xf",
+        "cmp x22, #0x9 (9)",
+        "cset x22, hi",
+        "eor w23, w27, w26",
+        "ubfx w23, w23, #4, #1",
+        "orr x22, x23, x22",
+        "cmp x20, #0x99 (153)",
+        "cset x23, hi",
+        "orr x21, x21, x23",
+        "add x23, x20, #0x6 (6)",
+        "cmp x22, #0x0 (0)",
+        "csel x20, x23, x20, ne",
+        "add x23, x20, #0x60 (96)",
+        "cmp x21, #0x0 (0)",
+        "csel x26, x23, x20, ne",
+        "bfxil w4, w26, #0, #8",
+        "cmn wzr, w26, lsl #24",
+        "rmif x21, #63, #nzCv",
+        "eor w27, w26, w22, lsl #4"
       ]
     },
     "das": {
-      "ExpectedInstructionCount": 49,
+      "ExpectedInstructionCount": 24,
       "Comment": "0x2f",
       "ExpectedArm64ASM": [
-        "mov w20, #0x0",
-        "cset w21, hs",
-        "eor w22, w27, w26",
-        "ubfx w22, w22, #4, #1",
-        "uxtb w23, w4",
-        "rmif x20, #63, #nzCv",
-        "and x20, x23, #0xf",
-        "mrs x24, nzcv",
-        "cmp x20, #0x9 (9)",
-        "cset x20, hi",
-        "orr x20, x22, x20",
-        "msr nzcv, x24",
-        "cbnz x20, #+0xc",
-        "mov w27, #0x0",
-        "b #+0x1c",
-        "sub x20, x23, #0x6 (6)",
-        "bfxil w4, w20, #0, #8",
-        "cset w20, hs",
-        "orr x20, x21, x20",
-        "rmif x20, #63, #nzCv",
-        "mov w27, #0x10",
-        "mrs x20, nzcv",
-        "cmp x23, #0x99 (153)",
-        "cset x22, hi",
-        "orr x21, x21, x22",
-        "msr nzcv, x20",
-        "cbnz x21, #+0x10",
-        "mov w20, #0x0",
-        "rmif x20, #63, #nzCv",
-        "b #+0x18",
         "uxtb w20, w4",
-        "sub x20, x20, #0x60 (96)",
-        "bfxil w4, w20, #0, #8",
-        "mov w20, #0x1",
-        "rmif x20, #63, #nzCv",
-        "uxtb w26, w4",
-        "and x20, x26, #0x80",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, hs",
-        "msr nzcv, x21",
-        "rmif x20, #61, #Nzcv",
-        "and x20, x26, #0xff",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
-        "msr nzcv, x21",
-        "rmif x20, #62, #nZcv",
-        "eor w27, w27, w26"
+        "cset w21, hs",
+        "and x22, x20, #0xf",
+        "cmp x22, #0x9 (9)",
+        "cset x22, hi",
+        "eor w23, w27, w26",
+        "ubfx w23, w23, #4, #1",
+        "orr x22, x23, x22",
+        "cmp x20, #0x99 (153)",
+        "cset x23, hi",
+        "orr x21, x21, x23",
+        "cmp x20, #0x6 (6)",
+        "csel x23, x22, x21, lo",
+        "orr w23, w21, w23",
+        "sub x24, x20, #0x6 (6)",
+        "cmp x22, #0x0 (0)",
+        "csel x20, x24, x20, ne",
+        "sub x24, x20, #0x60 (96)",
+        "cmp x21, #0x0 (0)",
+        "csel x26, x24, x20, ne",
+        "bfxil w4, w26, #0, #8",
+        "cmn wzr, w26, lsl #24",
+        "rmif x23, #63, #nzCv",
+        "eor w27, w26, w22, lsl #4"
       ]
     },
     "aaa": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 14,
       "Comment": "0x37",
       "ExpectedArm64ASM": [
-        "eor w20, w27, w26",
-        "ubfx w20, w20, #4, #1",
-        "uxtb w21, w4",
-        "uxth w22, w4",
-        "and x21, x21, #0xf",
-        "mrs x23, nzcv",
-        "cmp x21, #0x9 (9)",
-        "cset x21, hi",
-        "orr x20, x20, x21",
-        "msr nzcv, x23",
-        "cbnz x20, #+0x1c",
-        "mov w20, #0xff0f",
-        "and x20, x22, x20",
-        "bfxil w4, w20, #0, #16",
-        "mov w27, #0x0",
-        "msr nzcv, x27",
-        "b #+0x20",
-        "add x20, x22, #0x106 (262)",
+        "and x20, x4, #0xf",
+        "cmp x20, #0x9 (9)",
+        "cset x20, hi",
+        "eor w21, w27, w26",
+        "ubfx w21, w21, #4, #1",
+        "orr x20, x21, x20",
+        "lsl x21, x20, #29",
+        "eor w27, w26, w20, lsl #4",
+        "msr nzcv, x21",
+        "add w20, w4, #0x106 (262)",
+        "csel w20, w20, w4, hs",
         "mov w21, #0xff0f",
-        "and x20, x20, x21",
-        "bfxil w4, w20, #0, #16",
-        "mov w20, #0x20000000",
-        "mov w27, #0x10",
-        "msr nzcv, x20"
+        "and w20, w20, w21",
+        "bfxil w4, w20, #0, #16"
       ]
     },
     "aas": {
-      "ExpectedInstructionCount": 25,
+      "ExpectedInstructionCount": 14,
       "Comment": "0x3f",
       "ExpectedArm64ASM": [
-        "eor w20, w27, w26",
-        "ubfx w20, w20, #4, #1",
-        "uxtb w21, w4",
-        "uxth w22, w4",
-        "and x21, x21, #0xf",
-        "mrs x23, nzcv",
-        "cmp x21, #0x9 (9)",
-        "cset x21, hi",
-        "orr x20, x20, x21",
-        "msr nzcv, x23",
-        "cbnz x20, #+0x1c",
-        "mov w20, #0xff0f",
-        "and x20, x22, x20",
-        "bfxil w4, w20, #0, #16",
-        "mov w27, #0x0",
-        "msr nzcv, x27",
-        "b #+0x24",
-        "sub x20, x22, #0x6 (6)",
-        "sub x20, x20, #0x100 (256)",
+        "and x20, x4, #0xf",
+        "cmp x20, #0x9 (9)",
+        "cset x20, hi",
+        "eor w21, w27, w26",
+        "ubfx w21, w21, #4, #1",
+        "orr x20, x21, x20",
+        "lsl x21, x20, #29",
+        "eor w27, w26, w20, lsl #4",
+        "msr nzcv, x21",
+        "sub w20, w4, #0x106 (262)",
+        "csel w20, w20, w4, hs",
         "mov w21, #0xff0f",
-        "and x20, x20, x21",
-        "bfxil w4, w20, #0, #16",
-        "mov w20, #0x20000000",
-        "mov w27, #0x10",
-        "msr nzcv, x20"
+        "and w20, w20, w21",
+        "bfxil w4, w20, #0, #16"
       ]
     },
     "inc ax": {
@@ -386,7 +312,7 @@
       ]
     },
     "aam": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 8,
       "Comment": "0xd4",
       "ExpectedArm64ASM": [
         "uxtb w20, w4",
@@ -394,31 +320,26 @@
         "udiv x22, x20, x21",
         "udiv x2, x20, x21",
         "msub x20, x2, x21, x20",
-        "lsl x21, x22, #8",
-        "add x20, x21, x20",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "add x26, x20, x22, lsl #8",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "aad": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 7,
       "Comment": "0xd5",
       "ExpectedArm64ASM": [
-        "uxtb w20, w4",
-        "uxth w21, w4",
-        "lsr w21, w21, #8",
-        "mov w22, #0xa",
-        "mul x21, x21, x22",
-        "add x20, x20, x21",
-        "and x20, x20, #0xff",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "lsr w20, w4, #8",
+        "mov w21, #0xa",
+        "mul x20, x20, x21",
+        "add x20, x4, x20",
+        "and x26, x20, #0xff",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "db 0xd4, 0x40": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 8,
       "Comment": [
         "aam with a different immediate byte base",
         "0xd4"
@@ -429,28 +350,23 @@
         "udiv x22, x20, x21",
         "udiv x2, x20, x21",
         "msub x20, x2, x21, x20",
-        "lsl x21, x22, #8",
-        "add x20, x21, x20",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "add x26, x20, x22, lsl #8",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "db 0xd5, 0x40": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "aad with a different immediate byte base",
         "0xd5"
       ],
       "ExpectedArm64ASM": [
-        "uxtb w20, w4",
-        "uxth w21, w4",
-        "lsr w21, w21, #8",
-        "lsl x21, x21, #6",
-        "add x20, x20, x21",
-        "and x20, x20, #0xff",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "lsr w20, w4, #8",
+        "lsl x20, x20, #6",
+        "add x20, x4, x20",
+        "and x26, x20, #0xff",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json
index eaeb0f592..cf8b6df87 100644
--- a/unittests/InstructionCountCI/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/Primary_32Bit.json
@@ -82,188 +82,104 @@
       ]
     },
     "daa": {
-      "ExpectedInstructionCount": 56,
+      "ExpectedInstructionCount": 23,
       "Comment": "0x27",
       "ExpectedArm64ASM": [
-        "cset w20, hs",
-        "eor w21, w27, w26",
-        "ubfx w21, w21, #4, #1",
-        "uxtb w22, w4",
-        "mrs x23, nzcv",
-        "and w23, w23, #0xdfffffff",
-        "msr nzcv, x23",
-        "and x23, x22, #0xf",
-        "mrs x24, nzcv",
-        "cmp x23, #0x9 (9)",
+        "uxtb w20, w4",
+        "cset w21, hs",
+        "and x22, x20, #0xf",
+        "cmp x22, #0x9 (9)",
+        "cset x22, hi",
+        "eor w23, w27, w26",
+        "ubfx w23, w23, #4, #1",
+        "orr x22, x23, x22",
+        "cmp x20, #0x99 (153)",
         "cset x23, hi",
         "orr x21, x21, x23",
-        "msr nzcv, x24",
-        "cbnz x21, #+0xc",
-        "mov w27, #0x0",
-        "b #+0x2c",
-        "add x21, x22, #0x6 (6)",
-        "bfxil w4, w21, #0, #8",
-        "cset w21, hs",
-        "orr x21, x20, x21",
-        "mrs x23, nzcv",
-        "mov w0, w23",
-        "bfi w0, w21, #29, #1",
-        "mov w21, w0",
-        "mov w27, #0x10",
-        "msr nzcv, x21",
-        "mrs x21, nzcv",
-        "cmp x22, #0x99 (153)",
-        "cset x22, hi",
-        "orr x20, x20, x22",
-        "msr nzcv, x21",
-        "cbnz x20, #+0x14",
-        "mrs x20, nzcv",
-        "and w20, w20, #0xdfffffff",
-        "msr nzcv, x20",
-        "b #+0x1c",
-        "uxtb w20, w4",
-        "add x20, x20, #0x60 (96)",
-        "bfxil w4, w20, #0, #8",
-        "mrs x20, nzcv",
-        "orr w20, w20, #0x20000000",
-        "msr nzcv, x20",
-        "uxtb w26, w4",
-        "and x20, x26, #0x80",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, hs",
-        "mov w0, w21",
-        "bfi w0, w20, #31, #1",
-        "mov w20, w0",
-        "and x21, x26, #0xff",
+        "add x23, x20, #0x6 (6)",
+        "cmp x22, #0x0 (0)",
+        "csel x20, x23, x20, ne",
+        "add x23, x20, #0x60 (96)",
         "cmp x21, #0x0 (0)",
-        "cset x21, eq",
-        "bfi w20, w21, #30, #1",
-        "eor w27, w27, w26",
+        "csel x26, x23, x20, ne",
+        "bfxil w4, w26, #0, #8",
+        "cmn wzr, w26, lsl #24",
+        "mrs x20, nzcv",
+        "orr w20, w20, w21, lsl #29",
+        "eor w27, w26, w22, lsl #4",
         "msr nzcv, x20"
       ]
     },
     "das": {
-      "ExpectedInstructionCount": 56,
+      "ExpectedInstructionCount": 26,
       "Comment": "0x2f",
       "ExpectedArm64ASM": [
-        "cset w20, hs",
-        "eor w21, w27, w26",
-        "ubfx w21, w21, #4, #1",
-        "uxtb w22, w4",
-        "mrs x23, nzcv",
-        "and w23, w23, #0xdfffffff",
-        "msr nzcv, x23",
-        "and x23, x22, #0xf",
-        "mrs x24, nzcv",
-        "cmp x23, #0x9 (9)",
+        "uxtb w20, w4",
+        "cset w21, hs",
+        "and x22, x20, #0xf",
+        "cmp x22, #0x9 (9)",
+        "cset x22, hi",
+        "eor w23, w27, w26",
+        "ubfx w23, w23, #4, #1",
+        "orr x22, x23, x22",
+        "cmp x20, #0x99 (153)",
         "cset x23, hi",
         "orr x21, x21, x23",
-        "msr nzcv, x24",
-        "cbnz x21, #+0xc",
-        "mov w27, #0x0",
-        "b #+0x2c",
-        "sub x21, x22, #0x6 (6)",
-        "bfxil w4, w21, #0, #8",
-        "cset w21, hs",
-        "orr x21, x20, x21",
-        "mrs x23, nzcv",
-        "mov w0, w23",
-        "bfi w0, w21, #29, #1",
-        "mov w21, w0",
-        "mov w27, #0x10",
-        "msr nzcv, x21",
-        "mrs x21, nzcv",
-        "cmp x22, #0x99 (153)",
-        "cset x22, hi",
-        "orr x20, x20, x22",
-        "msr nzcv, x21",
-        "cbnz x20, #+0x14",
-        "mrs x20, nzcv",
-        "and w20, w20, #0xdfffffff",
-        "msr nzcv, x20",
-        "b #+0x1c",
-        "uxtb w20, w4",
-        "sub x20, x20, #0x60 (96)",
-        "bfxil w4, w20, #0, #8",
-        "mrs x20, nzcv",
-        "orr w20, w20, #0x20000000",
-        "msr nzcv, x20",
-        "uxtb w26, w4",
-        "and x20, x26, #0x80",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, hs",
-        "mov w0, w21",
-        "bfi w0, w20, #31, #1",
-        "mov w20, w0",
-        "and x21, x26, #0xff",
+        "cmp x20, #0x6 (6)",
+        "csel x23, x22, x21, lo",
+        "orr w23, w21, w23",
+        "sub x24, x20, #0x6 (6)",
+        "cmp x22, #0x0 (0)",
+        "csel x20, x24, x20, ne",
+        "sub x24, x20, #0x60 (96)",
         "cmp x21, #0x0 (0)",
-        "cset x21, eq",
-        "bfi w20, w21, #30, #1",
-        "eor w27, w27, w26",
+        "csel x26, x24, x20, ne",
+        "bfxil w4, w26, #0, #8",
+        "cmn wzr, w26, lsl #24",
+        "mrs x20, nzcv",
+        "orr w20, w20, w23, lsl #29",
+        "eor w27, w26, w22, lsl #4",
         "msr nzcv, x20"
       ]
     },
     "aaa": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 14,
       "Comment": "0x37",
       "ExpectedArm64ASM": [
-        "eor w20, w27, w26",
-        "ubfx w20, w20, #4, #1",
-        "uxtb w21, w4",
-        "uxth w22, w4",
-        "and x21, x21, #0xf",
-        "mrs x23, nzcv",
-        "cmp x21, #0x9 (9)",
-        "cset x21, hi",
-        "orr x20, x20, x21",
-        "msr nzcv, x23",
-        "cbnz x20, #+0x1c",
-        "mov w20, #0xff0f",
-        "and x20, x22, x20",
-        "bfxil w4, w20, #0, #16",
-        "mov w27, #0x0",
-        "msr nzcv, x27",
-        "b #+0x20",
-        "add x20, x22, #0x106 (262)",
+        "and x20, x4, #0xf",
+        "cmp x20, #0x9 (9)",
+        "cset x20, hi",
+        "eor w21, w27, w26",
+        "ubfx w21, w21, #4, #1",
+        "orr x20, x21, x20",
+        "lsl x21, x20, #29",
+        "eor w27, w26, w20, lsl #4",
+        "msr nzcv, x21",
+        "add w20, w4, #0x106 (262)",
+        "csel w20, w20, w4, hs",
         "mov w21, #0xff0f",
-        "and x20, x20, x21",
-        "bfxil w4, w20, #0, #16",
-        "mov w20, #0x20000000",
-        "mov w27, #0x10",
-        "msr nzcv, x20"
+        "and w20, w20, w21",
+        "bfxil w4, w20, #0, #16"
       ]
     },
     "aas": {
-      "ExpectedInstructionCount": 25,
+      "ExpectedInstructionCount": 14,
       "Comment": "0x3f",
       "ExpectedArm64ASM": [
-        "eor w20, w27, w26",
-        "ubfx w20, w20, #4, #1",
-        "uxtb w21, w4",
-        "uxth w22, w4",
-        "and x21, x21, #0xf",
-        "mrs x23, nzcv",
-        "cmp x21, #0x9 (9)",
-        "cset x21, hi",
-        "orr x20, x20, x21",
-        "msr nzcv, x23",
-        "cbnz x20, #+0x1c",
-        "mov w20, #0xff0f",
-        "and x20, x22, x20",
-        "bfxil w4, w20, #0, #16",
-        "mov w27, #0x0",
-        "msr nzcv, x27",
-        "b #+0x24",
-        "sub x20, x22, #0x6 (6)",
-        "sub x20, x20, #0x100 (256)",
+        "and x20, x4, #0xf",
+        "cmp x20, #0x9 (9)",
+        "cset x20, hi",
+        "eor w21, w27, w26",
+        "ubfx w21, w21, #4, #1",
+        "orr x20, x21, x20",
+        "lsl x21, x20, #29",
+        "eor w27, w26, w20, lsl #4",
+        "msr nzcv, x21",
+        "sub w20, w4, #0x106 (262)",
+        "csel w20, w20, w4, hs",
         "mov w21, #0xff0f",
-        "and x20, x20, x21",
-        "bfxil w4, w20, #0, #16",
-        "mov w20, #0x20000000",
-        "mov w27, #0x10",
-        "msr nzcv, x20"
+        "and w20, w20, w21",
+        "bfxil w4, w20, #0, #16"
       ]
     },
     "inc ax": {
@@ -415,7 +331,7 @@
       ]
     },
     "aam": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 8,
       "Comment": "0xd4",
       "ExpectedArm64ASM": [
         "uxtb w20, w4",
@@ -423,31 +339,26 @@
         "udiv x22, x20, x21",
         "udiv x2, x20, x21",
         "msub x20, x2, x21, x20",
-        "lsl x21, x22, #8",
-        "add x20, x21, x20",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "add x26, x20, x22, lsl #8",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "aad": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 7,
       "Comment": "0xd5",
       "ExpectedArm64ASM": [
-        "uxtb w20, w4",
-        "uxth w21, w4",
-        "lsr w21, w21, #8",
-        "mov w22, #0xa",
-        "mul x21, x21, x22",
-        "add x20, x20, x21",
-        "and x20, x20, #0xff",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "lsr w20, w4, #8",
+        "mov w21, #0xa",
+        "mul x20, x20, x21",
+        "add x20, x4, x20",
+        "and x26, x20, #0xff",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "db 0xd4, 0x40": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 8,
       "Comment": [
         "aam with a different immediate byte base",
         "0xd4"
@@ -458,28 +369,23 @@
         "udiv x22, x20, x21",
         "udiv x2, x20, x21",
         "msub x20, x2, x21, x20",
-        "lsl x21, x22, #8",
-        "add x20, x21, x20",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "add x26, x20, x22, lsl #8",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },
     "db 0xd5, 0x40": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "aad with a different immediate byte base",
         "0xd5"
       ],
       "ExpectedArm64ASM": [
-        "uxtb w20, w4",
-        "uxth w21, w4",
-        "lsr w21, w21, #8",
-        "lsl x21, x21, #6",
-        "add x20, x20, x21",
-        "and x20, x20, #0xff",
-        "bfxil w4, w20, #0, #16",
-        "uxtb w26, w4",
+        "lsr w20, w4, #8",
+        "lsl x20, x20, #6",
+        "add x20, x4, x20",
+        "and x26, x20, #0xff",
+        "bfxil w4, w26, #0, #16",
         "cmn wzr, w26, lsl #24"
       ]
     },