diff --git a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
index b6c176ec7..acc1840ee 100644
--- a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
@@ -2791,17 +2791,17 @@ DEF_OP(VUShrSWide) {
   const auto Vector = GetVReg(Op->Vector);
 
   if (HostSupportsSVE256 && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
     dup(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), ShiftScalar.Z(), 0);
-    if (Dst != Vector) {
-      // NOTE: SVE LSR is a destructive operation.
-      movprfx(Dst.Z(), Vector.Z());
-    }
     if (ElementSize == IR::OpSize::i64Bit) {
+      const auto Mask = PRED_TMP_32B.Merging();
+
+      if (Dst != Vector) {
+        // NOTE: SVE LSR is a destructive operation.
+        movprfx(Dst.Z(), Vector.Z());
+      }
       lsr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
     } else {
-      lsr_wide(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
+      lsr_wide(SubRegSize, Dst.Z(), Vector.Z(), VTMP1.Z());
     }
   } else if (HostSupportsSVE128) {
     const auto Mask = PRED_TMP_16B.Merging();
@@ -2857,17 +2857,17 @@ DEF_OP(VSShrSWide) {
   const auto Vector = GetVReg(Op->Vector);
 
   if (HostSupportsSVE256 && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
     dup(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), ShiftScalar.Z(), 0);
-    if (Dst != Vector) {
-      // NOTE: SVE LSR is a destructive operation.
-      movprfx(Dst.Z(), Vector.Z());
-    }
     if (ElementSize == IR::OpSize::i64Bit) {
+      const auto Mask = PRED_TMP_32B.Merging();
+
+      if (Dst != Vector) {
+        // NOTE: SVE LSR is a destructive operation.
+        movprfx(Dst.Z(), Vector.Z());
+      }
       asr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
     } else {
-      asr_wide(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
+      asr_wide(SubRegSize, Dst.Z(), Vector.Z(), VTMP1.Z());
     }
   } else if (HostSupportsSVE128) {
     const auto Mask = PRED_TMP_16B.Merging();
@@ -2923,17 +2923,17 @@ DEF_OP(VUShlSWide) {
   const auto Vector = GetVReg(Op->Vector);
 
   if (HostSupportsSVE256 && Is256Bit) {
-    const auto Mask = PRED_TMP_32B.Merging();
-
     dup(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), ShiftScalar.Z(), 0);
-    if (Dst != Vector) {
-      // NOTE: SVE LSR is a destructive operation.
-      movprfx(Dst.Z(), Vector.Z());
-    }
     if (ElementSize == IR::OpSize::i64Bit) {
+      const auto Mask = PRED_TMP_32B.Merging();
+
+      if (Dst != Vector) {
+        // NOTE: SVE LSR is a destructive operation.
+        movprfx(Dst.Z(), Vector.Z());
+      }
       lsl(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
     } else {
-      lsl_wide(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
+      lsl_wide(SubRegSize, Dst.Z(), Vector.Z(), VTMP1.Z());
     }
   } else if (HostSupportsSVE128) {
     const auto Mask = PRED_TMP_16B.Merging();
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 22be82446..d1de940ad 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -4408,14 +4408,13 @@
       ]
     },
     "vpsrlw ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xd1 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "lsr z16.h, p7/m, z16.h, z0.d"
+        "lsr z16.h, z17.h, z0.d"
       ]
     },
     "vpsrld xmm0, xmm1, xmm2": {
@@ -4431,14 +4430,13 @@
       ]
     },
     "vpsrld ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xd2 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "lsr z16.s, p7/m, z16.s, z0.d"
+        "lsr z16.s, z17.s, z0.d"
       ]
     },
     "vpsrlq xmm0, xmm1, xmm2": {
@@ -4788,14 +4786,13 @@
       ]
     },
     "vpsraw ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xe1 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "asr z16.h, p7/m, z16.h, z0.d"
+        "asr z16.h, z17.h, z0.d"
       ]
     },
     "vpsrad xmm0, xmm1, xmm2": {
@@ -4811,14 +4808,13 @@
       ]
     },
     "vpsrad ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xe2 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "asr z16.s, p7/m, z16.s, z0.d"
+        "asr z16.s, z17.s, z0.d"
       ]
     },
     "vpavgw xmm0, xmm1, xmm2": {
@@ -5257,14 +5253,13 @@
       ]
     },
     "vpsllw ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xf1 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "lsl z16.h, p7/m, z16.h, z0.d"
+        "lsl z16.h, z17.h, z0.d"
       ]
     },
     "vpslld xmm0, xmm1, xmm2": {
@@ -5280,14 +5275,13 @@
       ]
     },
     "vpslld ymm0, ymm1, xmm2": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": [
         "Map 1 0b01 0xf2 256-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z0.d, d18",
-        "movprfx z16, z17",
-        "lsl z16.s, p7/m, z16.s, z0.d"
+        "lsl z16.s, z17.s, z0.d"
       ]
     },
     "vpsllq xmm0, xmm1, xmm2": {