From ba28e6f82e10100a552fccfab136880d2f167dc5 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 26 Jun 2024 13:28:26 -0700 Subject: [PATCH] unittests: Adds vcvtps2ph tests that use mxcsr --- unittests/ASM/Disabled_Tests_Simulator | 4 ++ unittests/ASM/VEX/vcvtps2ph_rd_mxcsr.asm | 61 +++++++++++++++++++++ unittests/ASM/VEX/vcvtps2ph_rtne_mxcsr.asm | 61 +++++++++++++++++++++ unittests/ASM/VEX/vcvtps2ph_ru_mxcsr.asm | 61 +++++++++++++++++++++ unittests/ASM/VEX/vcvtps2ph_trunc_mxcsr.asm | 61 +++++++++++++++++++++ 5 files changed, 248 insertions(+) create mode 100644 unittests/ASM/VEX/vcvtps2ph_rd_mxcsr.asm create mode 100644 unittests/ASM/VEX/vcvtps2ph_rtne_mxcsr.asm create mode 100644 unittests/ASM/VEX/vcvtps2ph_ru_mxcsr.asm create mode 100644 unittests/ASM/VEX/vcvtps2ph_trunc_mxcsr.asm diff --git a/unittests/ASM/Disabled_Tests_Simulator b/unittests/ASM/Disabled_Tests_Simulator index ac6ee7f3c..1447e32e3 100644 --- a/unittests/ASM/Disabled_Tests_Simulator +++ b/unittests/ASM/Disabled_Tests_Simulator @@ -92,6 +92,10 @@ Test_VEX/vcvtps2ph_rtne.asm Test_VEX/vcvtps2ph_rd.asm Test_VEX/vcvtps2ph_ru.asm Test_VEX/vcvtps2ph_trunc.asm +Test_VEX/vcvtps2ph_rtne_mxcsr.asm +Test_VEX/vcvtps2ph_rd_mxcsr.asm +Test_VEX/vcvtps2ph_ru_mxcsr.asm +Test_VEX/vcvtps2ph_trunc_mxcsr.asm # Simulator doesn't support cycle counter reading Test_TwoByte/0F_31.asm diff --git a/unittests/ASM/VEX/vcvtps2ph_rd_mxcsr.asm b/unittests/ASM/VEX/vcvtps2ph_rd_mxcsr.asm new file mode 100644 index 000000000..d88b99e9e --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_rd_mxcsr.asm @@ -0,0 +1,61 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007BFF00003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Set up MXCSR to Round Down +vldmxcsr [rel .mxcsr] + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 100b +vcvtps2ph xmm3, xmm1, 100b + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 100b +vcvtps2ph [rel .memarea + 8], xmm1, 100b +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 100b + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 100b +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + +.mxcsr: +dq 0x0000000000003F80 diff --git a/unittests/ASM/VEX/vcvtps2ph_rtne_mxcsr.asm b/unittests/ASM/VEX/vcvtps2ph_rtne_mxcsr.asm new file mode 100644 index 000000000..13f0d4793 --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_rtne_mxcsr.asm @@ -0,0 +1,61 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007C0000003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Set up MXCSR to Round to Nearest Even +vldmxcsr [rel .mxcsr] + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 100b +vcvtps2ph xmm3, xmm1, 100b + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 100b +vcvtps2ph [rel .memarea + 8], xmm1, 100b +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 100b + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 100b +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + +.mxcsr: +dq 0x0000000000001F80 diff --git a/unittests/ASM/VEX/vcvtps2ph_ru_mxcsr.asm b/unittests/ASM/VEX/vcvtps2ph_ru_mxcsr.asm new file mode 100644 index 000000000..dd505745c --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_ru_mxcsr.asm @@ -0,0 +1,61 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007C0000013C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0001FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"], + "XMM7": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"] + } +} +%endif + +; Set up MXCSR to Round Up +vldmxcsr [rel .mxcsr] + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 100b +vcvtps2ph xmm3, xmm1, 100b + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 100b +vcvtps2ph [rel .memarea + 8], xmm1, 100b +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 100b + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 100b +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + +.mxcsr: +dq 0x0000000000005F80 diff --git a/unittests/ASM/VEX/vcvtps2ph_trunc_mxcsr.asm b/unittests/ASM/VEX/vcvtps2ph_trunc_mxcsr.asm new file mode 100644 index 000000000..ec5bcb74f --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_trunc_mxcsr.asm @@ -0,0 +1,61 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007BFF00003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Set up MXCSR to truncate +vldmxcsr [rel .mxcsr] + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 100b +vcvtps2ph xmm3, xmm1, 100b + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 100b +vcvtps2ph [rel .memarea + 8], xmm1, 100b +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 100b + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 100b +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + +.mxcsr: +dq 0x0000000000007F80