From ba0887defac90d9c471e53d101eb135778dd7db1 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Fri, 8 Jul 2022 19:35:22 -0700 Subject: [PATCH] Misc: Convert assert logs to assume+assert that can be Most of these won't make a performance difference. But we should be using the assume version everywhere we can. --- External/FEXCore/Source/Common/BitSet.h | 6 +-- .../Interface/Core/ArchHelpers/MContext.h | 6 +-- .../Source/Interface/Core/CPUBackend.cpp | 6 +-- .../Core/Dispatcher/Arm64Dispatcher.cpp | 2 +- .../Interface/Core/Dispatcher/Dispatcher.cpp | 2 +- .../Core/Dispatcher/X86Dispatcher.cpp | 2 +- .../Source/Interface/Core/Frontend.cpp | 35 ++++++-------- .../Interface/Core/Interpreter/ALUOps.cpp | 6 +-- .../Core/Interpreter/InterpreterOps.cpp | 2 +- .../Interface/Core/Interpreter/VectorOps.cpp | 6 +-- .../Interface/Core/JIT/Arm64/ALUOps.cpp | 6 +-- .../Core/JIT/Arm64/Arm64Relocations.cpp | 2 +- .../Source/Interface/Core/JIT/Arm64/JIT.cpp | 18 +++---- .../Interface/Core/JIT/Arm64/MemoryOps.cpp | 38 +++++++-------- .../Interface/Core/JIT/Arm64/VectorOps.cpp | 4 +- .../Interface/Core/JIT/x86_64/ALUOps.cpp | 2 +- .../Source/Interface/Core/JIT/x86_64/JIT.cpp | 6 +-- .../Interface/Core/JIT/x86_64/VectorOps.cpp | 2 +- .../Core/JIT/x86_64/x64Relocations.cpp | 2 +- .../Source/Interface/Core/LookupCache.cpp | 4 +- .../Source/Interface/Core/LookupCache.h | 2 +- .../Interface/Core/OpcodeDispatcher.cpp | 10 ++-- .../Source/Interface/Core/OpcodeDispatcher.h | 2 +- .../Core/OpcodeDispatcher/Vector.cpp | 4 +- .../Interface/Core/X86Tables/X86Tables.h | 8 ++-- .../Source/Interface/HLE/Thunks/Thunks.cpp | 12 ++--- .../FEXCore/Source/Interface/IR/AOTIR.cpp | 6 +-- .../FEXCore/Source/Interface/IR/IREmitter.cpp | 2 +- .../Source/Interface/IR/Passes/ConstProp.cpp | 2 +- .../IR/Passes/DeadContextStoreElimination.cpp | 6 +-- .../Interface/IR/Passes/IRCompaction.cpp | 6 +-- .../Interface/IR/Passes/IRValidation.cpp | 2 +- .../Interface/IR/Passes/RAValidation.cpp | 4 +- .../IR/Passes/RegisterAllocationPass.cpp | 47 ++++++++++--------- .../Passes/StaticRegisterAllocationPass.cpp | 4 +- .../Source/Utils/Allocator/64BitAllocator.cpp | 2 +- .../Source/Utils/MemberFunctionToPointer.h | 4 +- .../FEXCore/include/FEXCore/IR/IREmitter.h | 2 +- .../include/FEXCore/Utils/BucketList.h | 4 +- Source/Linux/Utils/ELFContainer.cpp | 26 +++++----- Source/Tests/ELFCodeLoader.h | 2 +- Source/Tests/HarnessHelpers.h | 4 +- .../Tests/LinuxSyscalls/SignalDelegator.cpp | 4 +- .../LinuxSyscalls/SyscallsSMCTracking.cpp | 20 ++++---- Source/Tests/LinuxSyscalls/x32/FD.cpp | 4 +- Source/Tests/LinuxSyscalls/x32/Memory.cpp | 8 ++-- 46 files changed, 175 insertions(+), 179 deletions(-) diff --git a/External/FEXCore/Source/Common/BitSet.h b/External/FEXCore/Source/Common/BitSet.h index 42b581f25..57eca4ef1 100644 --- a/External/FEXCore/Source/Common/BitSet.h +++ b/External/FEXCore/Source/Common/BitSet.h @@ -20,12 +20,12 @@ struct BitSet final { ElementType *Memory; void Allocate(size_t Elements) { size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize; - LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail"); + LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail"); Memory = static_cast(FEXCore::Allocator::malloc(AllocateSize)); } void Realloc(size_t Elements) { size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize; - LOGMAN_THROW_A_FMT((AllocateSize * MinimumSize) >= Elements, "Fail"); + LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail"); Memory = static_cast(FEXCore::Allocator::realloc(Memory, AllocateSize)); } void Free() { @@ -64,7 +64,7 @@ struct BitSetView final { ElementType *Memory; void GetView(BitSet &Set, uint64_t ElementOffset) { - LOGMAN_THROW_A_FMT((ElementOffset % MinimumSize) == 0, + LOGMAN_THROW_AA_FMT((ElementOffset % MinimumSize) == 0, "Bitset view offset needs to be aligned to size of backing element"); Memory = &Set.Memory[ElementOffset / MinimumSizeBits]; } diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h b/External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h index 1b1a5e252..f8a1d3686 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h @@ -124,7 +124,7 @@ static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) { static inline __uint128_t GetArmFPR(void* ucontext, uint32_t id) { auto MContext = GetMContext(ucontext); HostFPRState *HostState = reinterpret_cast(&MContext->__reserved[0]); - LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); + LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); return HostState->FPRs[id]; } @@ -143,7 +143,7 @@ static inline void BackupContext(void* ucontext, T *Backup) { // Host FPR state starts at _mcontext->reserved[0]; HostFPRState *HostState = reinterpret_cast(&_mcontext->__reserved[0]); - LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); + LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); Backup->FPSR = HostState->FPSR; Backup->FPCR = HostState->FPCR; memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t)); @@ -163,7 +163,7 @@ static inline void RestoreContext(void* ucontext, T *Backup) { auto _mcontext = GetMContext(ucontext); HostFPRState *HostState = reinterpret_cast(&_mcontext->__reserved[0]); - LOGMAN_THROW_A_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); + LOGMAN_THROW_AA_FMT(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x{:08x}", HostState->Head.Magic); memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t)); HostState->FPCR = Backup->FPCR; HostState->FPSR = Backup->FPSR; diff --git a/External/FEXCore/Source/Interface/Core/CPUBackend.cpp b/External/FEXCore/Source/Interface/Core/CPUBackend.cpp index b7f98a920..59cc7e659 100644 --- a/External/FEXCore/Source/Interface/Core/CPUBackend.cpp +++ b/External/FEXCore/Source/Interface/Core/CPUBackend.cpp @@ -58,8 +58,8 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer { Buffer.Size = Size; Buffer.Ptr = static_cast( FEXCore::Allocator::mmap(nullptr, Buffer.Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); - LOGMAN_THROW_A_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer"); - + LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer"); + if (ThreadState->CTX->Config.GlobalJITNaming()) { ThreadState->CTX->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size); } @@ -84,4 +84,4 @@ bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const { } } -} \ No newline at end of file +} diff --git a/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp b/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp index 2672f79fa..d65af2a4a 100644 --- a/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp @@ -542,7 +542,7 @@ size_t Arm64Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t Gues } size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) { - LOGMAN_THROW_A_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA"); + LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "GenerateInterpreterTrampoline dispatcher does not support SRA"); *emit.GetBuffer() = vixl::CodeBuffer(CodeBuffer, MaxInterpreterTrampolineSize); diff --git a/External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp index d1c9c8941..4d26b8966 100644 --- a/External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp @@ -692,7 +692,7 @@ bool Dispatcher::HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, i else { NewGuestSP -= 4; *(uint32_t*)NewGuestSP = SignalReturn; - LOGMAN_THROW_A_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB"); + LOGMAN_THROW_AA_FMT(SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB"); Frame->State.gregs[FEXCore::X86State::REG_RSP] = NewGuestSP; } diff --git a/External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp b/External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp index c27b5a19a..676750091 100644 --- a/External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp @@ -33,7 +33,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, const DispatcherCon FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0), nullptr) { - LOGMAN_THROW_A_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA"); + LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA"); using namespace Xbyak; using namespace Xbyak::util; diff --git a/External/FEXCore/Source/Interface/Core/Frontend.cpp b/External/FEXCore/Source/Interface/Core/Frontend.cpp index 332b04057..0f4b565ed 100644 --- a/External/FEXCore/Source/Interface/Core/Frontend.cpp +++ b/External/FEXCore/Source/Interface/Core/Frontend.cpp @@ -188,7 +188,7 @@ Decoder::~Decoder() { uint8_t Decoder::ReadByte() { uint8_t Byte = InstStream[InstructionSize]; - LOGMAN_THROW_A_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!"); + LOGMAN_THROW_AA_FMT(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!"); Instruction[InstructionSize] = Byte; InstructionSize++; return Byte; @@ -200,14 +200,7 @@ uint8_t Decoder::PeekByte(uint8_t Offset) const { } uint64_t Decoder::ReadData(uint8_t Size) { - if (Size == 0) { - return 0; - } - - if (Size > sizeof(uint64_t)) { - LOGMAN_MSG_A_FMT("Unknown data size to read"); - return 0; - } + LOGMAN_THROW_AA_FMT(Size != 0 && Size <= sizeof(uint64_t), "Unknown data size to read"); uint64_t Res = 0; std::memcpy(&Res, &InstStream[InstructionSize], Size); @@ -347,13 +340,15 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100); Operand->Data.SIB.Base = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16); - LOGMAN_THROW_A_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src"); + LOGMAN_THROW_AA_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src"); - uint64_t Literal = ReadData(Displacement); - if (Displacement == 1) { - Literal = static_cast(Literal); + if (Displacement) { + uint64_t Literal = ReadData(Displacement); + if (Displacement == 1) { + Literal = static_cast(Literal); + } + Operand->Data.SIB.Offset = Literal; } - Operand->Data.SIB.Offset = Literal; } else if (ModRM.mod == 0) { // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes" @@ -404,7 +399,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, return false; } - LOGMAN_THROW_A_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P), + LOGMAN_THROW_AA_FMT(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P), "Group Ops should have been decoded before this!"); uint8_t DestSize{}; @@ -528,7 +523,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, } if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) { - LOGMAN_THROW_A_FMT(!HasMODRM, "This instruction shouldn't have ModRM!"); + LOGMAN_THROW_AA_FMT(!HasMODRM, "This instruction shouldn't have ModRM!"); // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR // This also means that the destination is always a GPR on these ones @@ -637,7 +632,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, } if (Bytes != 0) { - LOGMAN_THROW_A_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src"); + LOGMAN_THROW_AA_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src"); DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes; @@ -662,7 +657,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op, DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal; } - LOGMAN_THROW_A_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining", + LOGMAN_THROW_AA_FMT(Bytes == 0, "Inst at 0x{:x}: 0x{:04x} '{}' Had an instruction of size {} with {} remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name ?: "UND", InstructionSize, Bytes); DecodeInst->InstSize = InstructionSize; return true; @@ -688,7 +683,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16 return false; } - LOGMAN_THROW_A_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, + LOGMAN_THROW_AA_FMT(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!"); if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && @@ -745,7 +740,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16 3, }; uint8_t Field = RegToField[ModRM.reg]; - LOGMAN_THROW_A_FMT(Field != 255, "Invalid field selected!"); + LOGMAN_THROW_AA_FMT(Field != 255, "Invalid field selected!"); LocalOp = (Field << 3) | ModRM.rm; return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp); diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp index e54fbfcb3..30d2265af 100644 --- a/External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp +++ b/External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp @@ -843,7 +843,7 @@ DEF_OP(Bfi) { DEF_OP(Bfe) { auto Op = IROp->C(); - LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); uint64_t SourceMask = (1ULL << Op->Width) - 1; if (Op->Width == 64) { SourceMask = ~0ULL; @@ -856,7 +856,7 @@ DEF_OP(Bfe) { DEF_OP(Sbfe) { auto Op = IROp->C(); - LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for SBFE: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for SBFE: {}", IROp->Size); int64_t Src = *GetSrc(Data->SSAData, Op->Src); const uint64_t ShiftLeftAmount = (64 - (Op->Width + Op->lsb)); const uint64_t ShiftRightAmount = ShiftLeftAmount + Op->lsb; @@ -898,7 +898,7 @@ DEF_OP(VExtractToGPR) { const uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Vector); - LOGMAN_THROW_A_FMT(IROp->Size <= 16, "OpSize is too large for VExtractToGPR: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(IROp->Size <= 16, "OpSize is too large for VExtractToGPR: {}", IROp->Size); if (SourceSize == 16) { __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1; diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp index c07389549..7f72088e8 100644 --- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp +++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp @@ -358,7 +358,7 @@ void InterpreterOps::InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::I using namespace FEXCore::IR; auto [BlockNode, BlockHeader] = OpData.BlockIterator(); auto BlockIROp = BlockHeader->CW(); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); // Reset the block results per block memset(&OpData.BlockResults, 0, sizeof(OpData.BlockResults)); diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp index 78cdf2739..7a4ba3454 100644 --- a/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp +++ b/External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp @@ -43,7 +43,7 @@ DEF_OP(SplatVector) { auto Op = IROp->C(); uint8_t OpSize = IROp->Size; - LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); + LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); void *Src = GetSrc(Data->SSAData, Op->Scalar); uint8_t Tmp[16]; uint8_t Elements = 0; @@ -1376,7 +1376,7 @@ DEF_OP(VExtractElement) { auto Op = IROp->C(); const uint32_t SourceSize = GetOpSize(Data->CurrentIR, Op->Vector); - LOGMAN_THROW_A_FMT(IROp->Size <= 16, "OpSize is too large for VExtractElement: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(IROp->Size <= 16, "OpSize is too large for VExtractElement: {}", IROp->Size); if (SourceSize == 16) { __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1; uint64_t Shift = Op->Header.ElementSize * Op->Index * 8; @@ -1406,7 +1406,7 @@ DEF_OP(VDupElement) { const uint8_t OpSize = IROp->Size; const uint8_t Elements = OpSize / Op->Header.ElementSize; - LOGMAN_THROW_A_FMT(OpSize <= 16, "OpSize is too large for VDupElement: {}", OpSize); + LOGMAN_THROW_AA_FMT(OpSize <= 16, "OpSize is too large for VDupElement: {}", OpSize); if (OpSize == 16) { __uint128_t SourceMask = (1ULL << (Op->Header.ElementSize * 8)) - 1; uint64_t Shift = Op->Header.ElementSize * Op->Index * 8; diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 2c0196040..91241bf96 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -1084,8 +1084,8 @@ DEF_OP(Bfi) { DEF_OP(Bfe) { auto Op = IROp->C(); - LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); - LOGMAN_THROW_A_FMT(Op->Width != 0, "Invalid BFE width of 0"); + LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(Op->Width != 0, "Invalid BFE width of 0"); auto Dst = GetReg(Node); ubfx(Dst, GetReg(Op->Src.ID()), Op->lsb, Op->Width); @@ -1249,7 +1249,7 @@ DEF_OP(FCmp) { bool set = false; if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) { - LOGMAN_THROW_A_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0"); + LOGMAN_THROW_AA_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0"); // EQ or unordered cset(Dst, Condition::eq); // Z = 1 csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1 diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp index 34b6cf8a2..98fecf178 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/Arm64Relocations.cpp @@ -81,7 +81,7 @@ bool Arm64JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uin size_t DataIndex{}; for (size_t j = 0; j < NumRelocations; ++j) { const FEXCore::CPU::Relocation *Reloc = reinterpret_cast(&EntryRelocations[DataIndex]); - LOGMAN_THROW_A_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to"); + LOGMAN_THROW_AA_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to"); switch (Reloc->Header.Type) { case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: { diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index aff41c462..7f23fd00f 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -549,12 +549,12 @@ template<> aarch64::Register Arm64JITCore::GetReg(IR::NodeID Node) const { auto Reg = GetPhys(Node); + LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class); + if (Reg.Class == IR::GPRFixedClass.Val) { return SRA64[Reg.Reg].W(); } else if (Reg.Class == IR::GPRClass.Val) { return RA64[Reg.Reg].W(); - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class); } FEX_UNREACHABLE; @@ -564,12 +564,12 @@ template<> aarch64::Register Arm64JITCore::GetReg(IR::NodeID Node) const { auto Reg = GetPhys(Node); + LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class); + if (Reg.Class == IR::GPRFixedClass.Val) { return SRA64[Reg.Reg]; } else if (Reg.Class == IR::GPRClass.Val) { return RA64[Reg.Reg]; - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class); } FEX_UNREACHABLE; @@ -590,12 +590,12 @@ std::pair Arm64JITCore::GetSrcPairCW(); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); #endif auto BlockStartHostCode = GetCursorAddress(); diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp index 9740b55f6..a652aae25 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp @@ -115,23 +115,23 @@ DEF_OP(LoadRegister) { switch(Op->Header.Size) { case 1: - LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs"); ubfx(GetReg(Node), reg, regOffs * 8, 8); break; case 2: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); ubfx(GetReg(Node), reg, 0, 16); break; case 4: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); if (GetReg(Node).GetCode() != reg.GetCode()) mov(GetReg(Node), reg.W()); break; case 8: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); if (GetReg(Node).GetCode() != reg.GetCode()) mov(GetReg(Node), reg); break; @@ -147,17 +147,17 @@ DEF_OP(LoadRegister) { switch(Op->Header.Size) { case 1: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); mov(host.B(), guest.B()); break; case 2: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); fmov(host.H(), guest.H()); break; case 4: - LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs"); if (regOffs == 0) { if (host.GetCode() != guest.GetCode()) fmov(host.S(), guest.S()); @@ -167,7 +167,7 @@ DEF_OP(LoadRegister) { break; case 8: - LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs"); if (regOffs == 0) { if (host.GetCode() != guest.GetCode()) mov(host.D(), guest.D()); @@ -177,13 +177,13 @@ DEF_OP(LoadRegister) { break; case 16: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); if (host.GetCode() != guest.GetCode()) mov(host.Q(), guest.Q()); break; } } else { - LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class); + LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class); } } @@ -200,22 +200,22 @@ DEF_OP(StoreRegister) { switch(Op->Header.Size) { case 1: - LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs"); bfi(reg, GetReg(Op->Value.ID()), regOffs * 8, 8); break; case 2: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); bfi(reg, GetReg(Op->Value.ID()), 0, 16); break; case 4: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); bfi(reg, GetReg(Op->Value.ID()), 0, 32); break; case 8: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); if (GetReg(Op->Value.ID()).GetCode() != reg.GetCode()) mov(reg, GetReg(Op->Value.ID())); break; @@ -235,28 +235,28 @@ DEF_OP(StoreRegister) { break; case 2: - LOGMAN_THROW_A_FMT((regOffs & 1) == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT((regOffs & 1) == 0, "unexpected regOffs"); ins(guest.V8H(), regOffs/2, host.V8H(), 0); break; case 4: - LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs"); ins(guest.V4S(), regOffs/4, host.V4S(), 0); break; case 8: - LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs"); ins(guest.V2D(), regOffs / 8, host.V2D(), 0); break; case 16: - LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs"); + LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); if (guest.GetCode() != host.GetCode()) mov(guest.Q(), host.Q()); break; } } else { - LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class); + LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class); } } diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp index 1cc6afe2a..27a57bf00 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp @@ -45,7 +45,7 @@ DEF_OP(VectorImm) { DEF_OP(SplatVector2) { auto Op = IROp->C(); const uint8_t OpSize = IROp->Size; - LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); + LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); const uint8_t ElementSize = OpSize / 2; @@ -63,7 +63,7 @@ DEF_OP(SplatVector2) { DEF_OP(SplatVector4) { auto Op = IROp->C(); const uint8_t OpSize = IROp->Size; - LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); + LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); const uint8_t ElementSize = OpSize / 4; diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp index 998160cb6..907bc76ad 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp @@ -1034,7 +1034,7 @@ DEF_OP(Bfi) { DEF_OP(Bfe) { auto Op = IROp->C(); - LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); + LOGMAN_THROW_AA_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size); auto Dst = GetDst(Node); diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp index 4c72e253c..8a95865b7 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp @@ -407,7 +407,7 @@ void X86JITCore::ClearCache() { IR::PhysicalRegister X86JITCore::GetPhys(IR::NodeID Node) const { auto PhyReg = RAData->GetNodeRegister(Node); - LOGMAN_THROW_A_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class); + LOGMAN_THROW_AA_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class); return PhyReg; } @@ -592,7 +592,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi setSize(getSize() + GDBSize); } - LOGMAN_THROW_A_FMT(RAData != nullptr, "Needs RA"); + LOGMAN_THROW_AA_FMT(RAData != nullptr, "Needs RA"); SpillSlots = RAData->SpillSlots(); @@ -649,7 +649,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi using namespace FEXCore::IR; #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED auto BlockIROp = BlockHeader->CW(); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); #endif auto BlockStartHostCode = getCurr(); diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp index 7169068d6..e54f472f2 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp @@ -71,7 +71,7 @@ DEF_OP(SplatVector) { auto Op = IROp->C(); const uint8_t OpSize = IROp->Size; - LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); + LOGMAN_THROW_AA_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize); uint8_t Elements = 0; switch (Op->Header.Op) { diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp index e13c3d4c5..44b4c0238 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp @@ -91,7 +91,7 @@ bool X86JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint6 size_t DataIndex{}; for (size_t j = 0; j < NumRelocations; ++j) { const FEXCore::CPU::Relocation *Reloc = reinterpret_cast(&EntryRelocations[DataIndex]); - LOGMAN_THROW_A_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to"); + LOGMAN_THROW_AA_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to"); switch (Reloc->Header.Type) { case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: { diff --git a/External/FEXCore/Source/Interface/Core/LookupCache.cpp b/External/FEXCore/Source/Interface/Core/LookupCache.cpp index fa740bfea..e35d4d73b 100644 --- a/External/FEXCore/Source/Interface/Core/LookupCache.cpp +++ b/External/FEXCore/Source/Interface/Core/LookupCache.cpp @@ -37,11 +37,11 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX) // We currently limit to 128MB of real memory for caching for the total cache size. // Can end up being inefficient if we compile a small number of blocks per page PageMemory = reinterpret_cast(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); - LOGMAN_THROW_A_FMT(PageMemory != -1ULL, "Failed to allocate page memory"); + LOGMAN_THROW_AA_FMT(PageMemory != -1ULL, "Failed to allocate page memory"); // L1 Cache L1Pointer = reinterpret_cast(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); - LOGMAN_THROW_A_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer"); + LOGMAN_THROW_AA_FMT(L1Pointer != -1ULL, "Failed to allocate L1Pointer"); VirtualMemSize = ctx->Config.VirtualMemSize; } diff --git a/External/FEXCore/Source/Interface/Core/LookupCache.h b/External/FEXCore/Source/Interface/Core/LookupCache.h index d8cb6b969..6416e979d 100644 --- a/External/FEXCore/Source/Interface/Core/LookupCache.h +++ b/External/FEXCore/Source/Interface/Core/LookupCache.h @@ -90,7 +90,7 @@ public: std::lock_guard lk(WriteLock); [[maybe_unused]] auto Inserted = BlockList.emplace(Address, (uintptr_t)HostCode).second; - LOGMAN_THROW_A_FMT(Inserted, "Duplicate block mapping added"); + LOGMAN_THROW_AA_FMT(Inserted, "Duplicate block mapping added"); // There is no need to update L1 or L2, they will get updated on first lookup // However, adding to L1 here increases performance diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 7c7a7f34f..29992a532 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4503,7 +4503,7 @@ void OpDispatchBuilder::Finalize() { [[maybe_unused]] const FEXCore::IR::IROp_Header *IROp = RealNode->Op(DualListData.DataBegin()); - LOGMAN_THROW_A_FMT(IROp->Op == OP_IRHEADER, "First op in function must be our header"); + LOGMAN_THROW_AA_FMT(IROp->Op == OP_IRHEADER, "First op in function must be our header"); // Let's walk the jump blocks and see if we have handled every block target for (auto &Handler : JumpTargets) { @@ -4529,7 +4529,7 @@ uint8_t OpDispatchBuilder::GetDstSize(X86Tables::DecodedOp Op) const { const uint32_t DstSizeFlag = X86Tables::DecodeFlags::GetSizeDstFlags(Op->Flags); const uint8_t Size = Sizes[DstSizeFlag]; - LOGMAN_THROW_A_FMT(Size != 0, "Invalid destination size for op"); + LOGMAN_THROW_AA_FMT(Size != 0, "Invalid destination size for op"); return Size; } @@ -4547,7 +4547,7 @@ uint8_t OpDispatchBuilder::GetSrcSize(X86Tables::DecodedOp Op) const { const uint32_t SrcSizeFlag = X86Tables::DecodeFlags::GetSizeSrcFlags(Op->Flags); const uint8_t Size = Sizes[SrcSizeFlag]; - LOGMAN_THROW_A_FMT(Size != 0, "Invalid destination size for op"); + LOGMAN_THROW_AA_FMT(Size != 0, "Invalid destination size for op"); return Size; } @@ -4791,11 +4791,11 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl // For all other sizes, the upper bits are guaranteed to already be zero OrderedNode *Value = GetOpSize(Src) == 8 ? _Bfe(4, 32, 0, Src) : Src; - LOGMAN_THROW_A_FMT(!Operand.Data.GPR.HighBits, "Can't handle 32bit store to high 8bit register"); + LOGMAN_THROW_AA_FMT(!Operand.Data.GPR.HighBits, "Can't handle 32bit store to high 8bit register"); _StoreContext(GPRSize, Class, Value, offsetof(FEXCore::Core::CPUState, gregs[gpr])); } else { - LOGMAN_THROW_A_FMT(!(GPRSize == 4 && OpSize > 4), "Oops had a {} GPR load", OpSize); + LOGMAN_THROW_AA_FMT(!(GPRSize == 4 && OpSize > 4), "Oops had a {} GPR load", OpSize); _StoreContext(std::min(GPRSize, OpSize), Class, Src, offsetof(FEXCore::Core::CPUState, gregs[gpr]) + (Operand.Data.GPR.HighBits ? 1 : 0)); } } diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 6e60be07c..667047d93 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -665,7 +665,7 @@ private: void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src, int8_t Align, MemoryAccessType AccessType = MemoryAccessType::ACCESS_DEFAULT); [[nodiscard]] static uint32_t GPROffset(X86State::X86Reg reg) { - LOGMAN_THROW_A_FMT(reg <= X86State::X86Reg::REG_R15, "Invalid reg used"); + LOGMAN_THROW_AA_FMT(reg <= X86State::X86Reg::REG_R15, "Invalid reg used"); return static_cast(offsetof(Core::CPUState, gregs[static_cast(reg)])); } diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 5030d930c..4ebf53c3d 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -562,7 +562,7 @@ void OpDispatchBuilder::PSHUFBOp(OpcodeArgs) { template void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) { - LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?"); + LOGMAN_THROW_AA_FMT(ElementSize != 0, "What. No element size?"); const auto Size = GetSrcSize(Op); OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); uint8_t Shuffle = Op->Src[1].Data.Literal.Value; @@ -599,7 +599,7 @@ void OpDispatchBuilder::PSHUFDOp<4, false, true>(OpcodeArgs); template void OpDispatchBuilder::SHUFOp(OpcodeArgs) { - LOGMAN_THROW_A_FMT(ElementSize != 0, "What. No element size?"); + LOGMAN_THROW_AA_FMT(ElementSize != 0, "What. No element size?"); const auto Size = GetSrcSize(Op); OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1); OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h b/External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h index ce4af1635..f0362bc3c 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h +++ b/External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h @@ -33,7 +33,7 @@ static inline void GenerateTable(X86InstInfo *FinalTable, X86TablesInfoStruct{}", FinalTable[OpNum + i].Name, Info.Name); + LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name); FinalTable[OpNum + i] = Info; #ifndef NDEBUG ++Total; @@ -51,7 +51,7 @@ static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoS auto OpNum = Op.first; X86InstInfo const &Info = Op.Info; for (uint32_t i = 0; i < Op.second; ++i) { - LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name); + LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name); if (Info.Type == TYPE_COPY_OTHER) { FinalTable[OpNum + i] = OtherLocal[OpNum + i]; } @@ -74,7 +74,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct auto OpNum = Op.first; X86InstInfo const &Info = Op.Info; for (uint32_t i = 0; i < Op.second; ++i) { - LOGMAN_THROW_A_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name); + LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name); if ((OpNum & 0b11'000'000) == 0b11'000'000) { // If the mod field is 0b11 then it is a regular op FinalTable[OpNum + i] = Info; @@ -82,7 +82,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct else { // If the mod field is !0b11 then this instruction is duplicated through the whole mod [0b00, 0b10] range // and the modrm.rm space because that is used part of the instruction encoding - LOGMAN_THROW_A_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path"); + LOGMAN_THROW_AA_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path"); for (uint16_t mod = 0b00'000'000; mod < 0b11'000'000; mod += 0b01'000'000) { for (uint16_t rm = 0b000; rm < 0b1'000; ++rm) { FinalTable[(OpNum | mod | rm) + i] = Info; diff --git a/External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp b/External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp index 18100b2ea..cbcddc200 100644 --- a/External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp +++ b/External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp @@ -157,11 +157,11 @@ namespace FEXCore { auto args = reinterpret_cast(argsv); auto CTX = Thread->CTX; - LOGMAN_THROW_A_FMT(args->original_callee, "Tried to link null pointer address to guest function"); - LOGMAN_THROW_A_FMT(args->target_addr, "Tried to link address to null pointer guest function"); + LOGMAN_THROW_AA_FMT(args->original_callee, "Tried to link null pointer address to guest function"); + LOGMAN_THROW_AA_FMT(args->target_addr, "Tried to link address to null pointer guest function"); if (!CTX->Config.Is64BitMode) { - LOGMAN_THROW_A_FMT((args->original_callee >> 32) == 0, "Tried to link 64-bit address in 32-bit mode"); - LOGMAN_THROW_A_FMT((args->target_addr >> 32) == 0, "Tried to link 64-bit address in 32-bit mode"); + LOGMAN_THROW_AA_FMT((args->original_callee >> 32) == 0, "Tried to link 64-bit address in 32-bit mode"); + LOGMAN_THROW_AA_FMT((args->target_addr >> 32) == 0, "Tried to link 64-bit address in 32-bit mode"); } LogMan::Msg::DFmt("Thunks: Adding guest trampoline from address {:#x} to guest function {:#x}", @@ -217,7 +217,7 @@ namespace FEXCore { uintptr_t rv; // Pointer to host trampoline + TrampolineInstanceInfo } *args = reinterpret_cast(ArgsRV); - LOGMAN_THROW_A_FMT(args->GuestTarget, "Tried to create host-trampoline to null pointer guest function"); + LOGMAN_THROW_AA_FMT(args->GuestTarget, "Tried to create host-trampoline to null pointer guest function"); const auto CTX = Thread->CTX; const auto ThunkHandler = reinterpret_cast(CTX->ThunkHandler.get()); @@ -266,7 +266,7 @@ namespace FEXCore { PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - LOGMAN_THROW_A_FMT(ThunkHandler->HostTrampolineInstanceDataPtr != MAP_FAILED, "Failed to mmap HostTrampolineInstanceDataPtr"); + LOGMAN_THROW_AA_FMT(ThunkHandler->HostTrampolineInstanceDataPtr != MAP_FAILED, "Failed to mmap HostTrampolineInstanceDataPtr"); } const TrampolineInstanceInfo NewTrampolineInfo { diff --git a/External/FEXCore/Source/Interface/IR/AOTIR.cpp b/External/FEXCore/Source/Interface/IR/AOTIR.cpp index 48b6ed16d..042e6e8f2 100644 --- a/External/FEXCore/Source/Interface/IR/AOTIR.cpp +++ b/External/FEXCore/Source/Interface/IR/AOTIR.cpp @@ -127,7 +127,7 @@ namespace FEXCore::IR { auto Array = (AOTIRInlineIndex *)((char*)FilePtr + IndexOffset); - LOGMAN_THROW_A_FMT(Entry->Array == nullptr && Entry->FilePtr == nullptr, "Entry must not be initialized here"); + LOGMAN_THROW_AA_FMT(Entry->Array == nullptr && Entry->FilePtr == nullptr, "Entry must not be initialized here"); Entry->Array = Array; Entry->FilePtr = FilePtr; Entry->Size = Size; @@ -387,7 +387,7 @@ namespace FEXCore::IR { auto Inserted = AOTIRCache.insert({fileid, AOTIRCacheEntry { .FileId = fileid, .Filename = filename }}); auto Entry = &(Inserted.first->second); - LOGMAN_THROW_A_FMT(Entry->Array == nullptr, "Duplicate LoadAOTIRCacheEntry"); + LOGMAN_THROW_AA_FMT(Entry->Array == nullptr, "Duplicate LoadAOTIRCacheEntry"); if (CTX->Config.AOTIRLoad && AOTIRLoader) { auto streamfd = AOTIRLoader(fileid); @@ -403,7 +403,7 @@ namespace FEXCore::IR { } void AOTIRCaptureCache::UnloadAOTIRCacheEntry(AOTIRCacheEntry *Entry) { - LOGMAN_THROW_A_FMT(Entry != nullptr, "Removing not existing entry"); + LOGMAN_THROW_AA_FMT(Entry != nullptr, "Removing not existing entry"); if (Entry->Array) { FEXCore::Allocator::munmap(Entry->FilePtr, Entry->Size); diff --git a/External/FEXCore/Source/Interface/IR/IREmitter.cpp b/External/FEXCore/Source/Interface/IR/IREmitter.cpp index b12b1e109..30904b2e8 100644 --- a/External/FEXCore/Source/Interface/IR/IREmitter.cpp +++ b/External/FEXCore/Source/Interface/IR/IREmitter.cpp @@ -167,7 +167,7 @@ IREmitter::IRPair IREmitter::CreateNewCodeBlockAfter(OrderedNode if (insertAfter) { LinkCodeBlocks(insertAfter, CodeNode); } else { - LOGMAN_THROW_A_FMT(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here"); + LOGMAN_THROW_AA_FMT(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here"); // Find last block auto LastBlock = CurrentCodeBlock; diff --git a/External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index 78c363976..f02635f22 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -299,7 +299,7 @@ void ConstProp::FCMPOptimization(IREmitter *IREmit, const IRListView& CurrentIR) auto ghf = IROp->CW(); auto fcmp = IREmit->GetOpHeader(ghf->Value)->CW(); - LOGMAN_THROW_A_FMT(fcmp->Header.Op == OP_FCMP || fcmp->Header.Op == OP_F80CMP, "Unexpected OP_GETHOSTFLAG source"); + LOGMAN_THROW_AA_FMT(fcmp->Header.Op == OP_FCMP || fcmp->Header.Op == OP_F80CMP, "Unexpected OP_GETHOSTFLAG source"); if(fcmp->Header.Op == OP_FCMP) { fcmp->Flags |= 1 << ghf->Flag; } diff --git a/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp b/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp index 0e17c6914..815d944ca 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp @@ -246,7 +246,7 @@ namespace { ClassifiedStructSize += it.Class.Size; } - LOGMAN_THROW_A_FMT(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState), + LOGMAN_THROW_AA_FMT(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState), "Classified CPUStruct size doesn't match real CPUState struct size! {} (classified) != {} (real)", ClassifiedStructSize, sizeof(FEXCore::Core::CPUState)); @@ -331,8 +331,8 @@ ContextMemberInfo *RCLSE::FindMemberInfo(ContextInfo *ContextClassificationInfo, } ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) { - LOGMAN_THROW_A_FMT((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size"); - LOGMAN_THROW_A_FMT(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member"); + LOGMAN_THROW_AA_FMT((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size"); + LOGMAN_THROW_AA_FMT(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member"); // If we aren't fully overwriting the member then it is a partial write that we need to track if (Size < Info->Class.Size) { diff --git a/External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp b/External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp index 78ab339de..eb21df403 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp @@ -77,7 +77,7 @@ bool IRCompaction::Run(IREmitter *IREmit) { auto HeaderNode = CurrentIR.GetHeaderNode(); auto HeaderOp = CurrentIR.GetHeader(); - LOGMAN_THROW_A_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader"); + LOGMAN_THROW_AA_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader"); // This compaction pass is something that we need to ensure correct ordering and distances between IROps // Later on we assume that an IROp's SSA value live range is its Node locations @@ -101,7 +101,7 @@ bool IRCompaction::Run(IREmitter *IREmit) { { // Generate our codeblocks and link them together for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) { - LOGMAN_THROW_A_FMT(BlockHeader->Op == OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockHeader->Op == OP_CODEBLOCK, "IR type failed to be a code block"); auto LocalBlockIRNode = LocalBuilder._CodeBlock(LocalHeaderOp, LocalHeaderOp); // Use LocalHeaderOp as a dummy arg for now OldToNewRemap[CurrentIR.GetID(BlockNode).Value].NodeID = LocalIR.GetID(LocalBlockIRNode.Node); @@ -165,7 +165,7 @@ bool IRCompaction::Run(IREmitter *IREmit) { for (auto &Block : GeneratedCodeBlocks) { #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED auto BlockIROp = LocalIR.GetOp(Block.NewNode); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block"); #endif for (auto [LocalNode, LocalIROp] : LocalIR.GetCode(Block.NewNode)) { diff --git a/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp index af5e514d6..4b0fd9ff5 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp @@ -63,7 +63,7 @@ bool IRValidation::Run(IREmitter *IREmit) { for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) { auto BlockIROp = BlockHeader->CW(); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block"); if (!EntryBlock) { EntryBlock = BlockNode; diff --git a/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp b/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp index 8966875fd..0c01753b9 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp @@ -197,11 +197,11 @@ bool RAValidation::Run(IREmitter *IREmit) { // Get the control flow graph from the validation pass auto ValidationPass = Manager->GetPass("IRValidation"); - LOGMAN_THROW_A_FMT(ValidationPass != nullptr, "Couldn't find IRValidation pass"); + LOGMAN_THROW_AA_FMT(ValidationPass != nullptr, "Couldn't find IRValidation pass"); auto& OffsetToBlockMap = ValidationPass->OffsetToBlockMap; - LOGMAN_THROW_A_FMT(ValidationPass->EntryBlock != nullptr, "No entry point"); + LOGMAN_THROW_AA_FMT(ValidationPass->EntryBlock != nullptr, "No entry point"); BlocksToVisit.push_front(ValidationPass->EntryBlock); // Currently only a single entry point bool HadError = false; diff --git a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp index d222e8d1b..411b283aa 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp @@ -349,8 +349,8 @@ namespace { } void ConstrainedRAPass::AllocateRegisterSet(uint32_t RegisterCount, uint32_t ClassCount) { - LOGMAN_THROW_A_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG); - LOGMAN_THROW_A_FMT(ClassCount <= INVALID_CLASS, "Up to {} classes supported", INVALID_CLASS); + LOGMAN_THROW_AA_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG); + LOGMAN_THROW_AA_FMT(ClassCount <= INVALID_CLASS, "Up to {} classes supported", INVALID_CLASS); Graph = AllocateRegisterGraph(ClassCount); @@ -363,7 +363,7 @@ namespace { } void ConstrainedRAPass::AddRegisters(FEXCore::IR::RegisterClassType Class, uint32_t RegisterCount) { - LOGMAN_THROW_A_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG); + LOGMAN_THROW_AA_FMT(RegisterCount <= INVALID_REG, "Up to {} regs supported", INVALID_REG); AllocatePhysicalRegisters(Graph, Class, RegisterCount); } @@ -396,7 +396,7 @@ namespace { const auto BeginID = Op->Begin.ID(); const auto LastID = Op->Last.ID(); - LOGMAN_THROW_A_FMT(Op->Header.Op == OP_CODEBLOCK, "Block not defined by codeblock?"); + LOGMAN_THROW_AA_FMT(Op->Header.Op == OP_CODEBLOCK, "Block not defined by codeblock?"); LiveRange->Begin = std::min(LiveRange->Begin, BeginID); LiveRange->End = std::max(LiveRange->End, BeginID); @@ -453,7 +453,7 @@ namespace { // If the destination hasn't yet been set then set it now if (IROp->HasDest) { - LOGMAN_THROW_A_FMT(NodeLiveRange.Begin.Value == UINT32_MAX, + LOGMAN_THROW_AA_FMT(NodeLiveRange.Begin.Value == UINT32_MAX, "Node begin already defined?"); NodeLiveRange.Begin = Node; // Default to ending right where after it starts @@ -491,7 +491,7 @@ namespace { const auto ArgNode = Arg.ID(); auto& ArgNodeLiveRange = LiveRanges[ArgNode.Value]; - LOGMAN_THROW_A_FMT(ArgNodeLiveRange.Begin.Value != UINT32_MAX, + LOGMAN_THROW_AA_FMT(ArgNodeLiveRange.Begin.Value != UINT32_MAX, "%ssa{} used by %ssa{} before defined?", ArgNode, Node); const auto ArgNodeBlockID = Graph->Nodes[ArgNode.Value].Head.BlockID; @@ -544,26 +544,24 @@ namespace { // Is an OP_STOREREGISTER eligible to write directly to the SRA reg? auto IsPreWritable = [](uint8_t Size, RegisterClassType StaticClass) { + LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass); if (StaticClass == GPRFixedClass) { return Size == 8; } else if (StaticClass == FPRFixedClass) { return Size == 16; - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected static class {}", StaticClass); } return false; // Unknown }; // Is an OP_LOADREGISTER eligible to read directly from the SRA reg? auto IsAliasable = [](uint8_t Size, RegisterClassType StaticClass, uint32_t Offset) { + LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass); if (StaticClass == GPRFixedClass) { // We need more meta info to support not-size-of-reg return (Size == 8 /*|| Size == 4*/) && ((Offset & 7) == 0); } else if (StaticClass == FPRFixedClass) { // We need more meta info to support not-size-of-reg return (Size == 16 /*|| Size == 8 || Size == 4*/) && ((Offset & 15) == 0); - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected static class {}", StaticClass); } return false; // Unknown }; @@ -576,16 +574,17 @@ namespace { auto beginFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0]); auto endFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[16][0]); + LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset); + if (Offset >= beginGpr && Offset < endGpr) { auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE; return PhysicalRegister(GPRFixedClass, reg); } else if (Offset >= beginFpr && Offset < endFpr) { auto reg = (Offset - beginFpr) / Core::CPUState::XMM_REG_SIZE; return PhysicalRegister(FPRFixedClass, reg); - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected Offset {}", Offset); - return PhysicalRegister::Invalid(); } + + return PhysicalRegister::Invalid(); }; auto GprSize = Graph->Set.Classes[GPRFixedClass.Val].PhysicalCount; @@ -600,28 +599,30 @@ namespace { auto beginFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0]); auto endFpr = offsetof(FEXCore::Core::CpuStateFrame, State.xmm[16][0]); + LOGMAN_THROW_AA_FMT((Offset >= beginGpr && Offset < endGpr) || (Offset >= beginFpr && Offset < endFpr), "Unexpected Offset {}", Offset); + if (Offset >= beginGpr && Offset < endGpr) { auto reg = (Offset - beginGpr) / Core::CPUState::GPR_REG_SIZE; return &StaticMaps[reg]; } else if (Offset >= beginFpr && Offset < endFpr) { auto reg = (Offset - beginFpr) / Core::CPUState::XMM_REG_SIZE; return &StaticMaps[GprSize + reg]; - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected offset {}", Offset); - return nullptr; } + + return nullptr; }; // Get a StaticMap entry from reg and class const auto GetStaticMapFromReg = [&](IR::PhysicalRegister PhyReg) -> LiveRange** { + LOGMAN_THROW_A_FMT(PhyReg.Class == GPRFixedClass.Val || PhyReg.Class == FPRFixedClass.Val, "Unexpected Class {}", PhyReg.Class); + if (PhyReg.Class == GPRFixedClass.Val) { return &StaticMaps[PhyReg.Reg]; } else if (PhyReg.Class == FPRFixedClass.Val) { return &StaticMaps[GprSize + PhyReg.Reg]; - } else { - LOGMAN_THROW_A_FMT(false, "Unexpected Class {}", PhyReg.Class); - return nullptr; } + + return nullptr; }; // First pass: Mark pre-writes @@ -778,7 +779,7 @@ namespace { for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) { auto BlockIROp = BlockHeader->CW(); - LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); + LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block"); const auto BlockNodeID = IR->GetID(BlockNode); const auto BlockBeginID = BlockIROp->Begin.ID(); @@ -888,7 +889,7 @@ namespace { }; // SpanStart/SpanEnd assume SSA id will fit in 24bits - LOGMAN_THROW_A_FMT(NodeCount <= 0xff'ffff, "Block too large for Spans"); + LOGMAN_THROW_AA_FMT(NodeCount <= 0xff'ffff, "Block too large for Spans"); SpanStart.resize(NodeCount); SpanEnd.resize(NodeCount); @@ -924,7 +925,7 @@ namespace { }); } - LOGMAN_THROW_A_FMT(Active.Items[0] == 0, "Interference bug"); + LOGMAN_THROW_AA_FMT(Active.Items[0] == 0, "Interference bug"); SpanStart.clear(); SpanEnd.clear(); } @@ -1350,7 +1351,7 @@ namespace { auto LastCursor = IREmit->GetWriteCursor(); auto [CodeNode, IROp] = IR.at(SpillPointId)(); - LOGMAN_THROW_A_FMT(IROp->HasDest, "Can't spill with no dest"); + LOGMAN_THROW_AA_FMT(IROp->HasDest, "Can't spill with no dest"); const auto Node = IR.GetID(CodeNode); RegisterNode *CurrentNode = &Graph->Nodes[Node.Value]; diff --git a/External/FEXCore/Source/Interface/IR/Passes/StaticRegisterAllocationPass.cpp b/External/FEXCore/Source/Interface/IR/Passes/StaticRegisterAllocationPass.cpp index bd4c72a0e..9ac63a556 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/StaticRegisterAllocationPass.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/StaticRegisterAllocationPass.cpp @@ -29,7 +29,7 @@ bool IsStaticAllocGpr(uint32_t Offset, RegisterClassType Class) { if (Offset >= begin && Offset < end) { const auto reg = (Offset - begin) / Core::CPUState::GPR_REG_SIZE; - LOGMAN_THROW_A_FMT(Class == IR::GPRClass, "unexpected Class {}", Class); + LOGMAN_THROW_AA_FMT(Class.Val == IR::GPRClass.Val, "unexpected Class {}", Class); // 0..15 -> 16 in total return reg < Core::CPUState::NUM_GPRS; @@ -44,7 +44,7 @@ bool IsStaticAllocFpr(uint32_t Offset, RegisterClassType Class, bool AllowGpr) { if (Offset >= begin && Offset < end) { const auto reg = (Offset - begin) / Core::CPUState::XMM_REG_SIZE; - LOGMAN_THROW_A_FMT(Class == IR::FPRClass || (AllowGpr && Class == IR::GPRClass), "unexpected Class {}, AllowGpr {}", Class, AllowGpr); + LOGMAN_THROW_AA_FMT(Class.Val == IR::FPRClass.Val || (AllowGpr && Class.Val == IR::GPRClass.Val), "unexpected Class {}, AllowGpr {}", Class, AllowGpr); // 0..15 -> 16 in total return reg < Core::CPUState::NUM_XMMS; diff --git a/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp b/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp index cc29fd000..da7784c2b 100644 --- a/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp +++ b/External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp @@ -125,7 +125,7 @@ namespace Alloc::OSAllocator { [[maybe_unused]] auto Res = mprotect(reinterpret_cast(ReservedRegion->Base), SizePlusManagedData, PROT_READ | PROT_WRITE); - LOGMAN_THROW_A_FMT(Res == 0, "Couldn't mprotect region: {} '{}' Likely occurs when running out of memory or Maximum VMAs", errno, strerror(errno)); + LOGMAN_THROW_AA_FMT(Res == 0, "Couldn't mprotect region: {} '{}' Likely occurs when running out of memory or Maximum VMAs", errno, strerror(errno)); LiveVMARegion *LiveRange = new (reinterpret_cast(ReservedRegion->Base)) LiveVMARegion(); diff --git a/External/FEXCore/Source/Utils/MemberFunctionToPointer.h b/External/FEXCore/Source/Utils/MemberFunctionToPointer.h index 8feb2810a..f1b8c5323 100644 --- a/External/FEXCore/Source/Utils/MemberFunctionToPointer.h +++ b/External/FEXCore/Source/Utils/MemberFunctionToPointer.h @@ -21,12 +21,12 @@ class MemberFunctionToPointerCast final { // Itanium C++ ABI (https://itanium-cxx-abi.github.io/cxx-abi/abi.html#member-function-pointers) // Low bit of ptr specifies if this Member function pointer is virtual or not // Throw an assert if we were trying to cast a virtual member - LOGMAN_THROW_A_FMT((PMF.ptr & 1) == 0, "C++ Pointer-To-Member representation didn't have low bit set to 0. Are you trying to cast a virtual member?"); + LOGMAN_THROW_AA_FMT((PMF.ptr & 1) == 0, "C++ Pointer-To-Member representation didn't have low bit set to 0. Are you trying to cast a virtual member?"); #elif defined(_M_ARM_64 ) // C++ ABI for the Arm 64-bit Architecture (IHI 0059E) // 4.2.1 Representation of pointer to member function // Differs from Itanium specification - LOGMAN_THROW_A_FMT(PMF.adj == 0, "C++ Pointer-To-Member representation didn't have adj == 0. Are you trying to cast a virtual member?"); + LOGMAN_THROW_AA_FMT(PMF.adj == 0, "C++ Pointer-To-Member representation didn't have adj == 0. Are you trying to cast a virtual member?"); #else #error Don't know how to cast Member to function here. Likely just Itanium #endif diff --git a/External/FEXCore/include/FEXCore/IR/IREmitter.h b/External/FEXCore/include/FEXCore/IR/IREmitter.h index 6cc7fd5fa..b2dbe70de 100644 --- a/External/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/External/FEXCore/include/FEXCore/IR/IREmitter.h @@ -225,7 +225,7 @@ friend class FEXCore::IR::PassManager; ReplaceAllUsesWithRange(Node, NewNode, Start, AllNodesIterator(DualListData.ListBegin(), DualListData.DataBegin())); - LOGMAN_THROW_A_FMT(Node->NumUses == 0, "Node still used"); + LOGMAN_THROW_AA_FMT(Node->NumUses == 0, "Node still used"); auto IROp = Node->Op(DualListData.DataBegin())->CW(); // We can not remove the op if there are side-effects diff --git a/External/FEXCore/include/FEXCore/Utils/BucketList.h b/External/FEXCore/include/FEXCore/Utils/BucketList.h index cecc5ed4f..656d8ad82 100644 --- a/External/FEXCore/include/FEXCore/Utils/BucketList.h +++ b/External/FEXCore/include/FEXCore/Utils/BucketList.h @@ -21,7 +21,7 @@ namespace FEXCore { void Clear() { Items[0] = T{}; - #ifndef NDEBUG + #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED for (size_t i = 1; i < Size; i++) { Items[i] = T{0xDEADBEEF}; } @@ -138,4 +138,4 @@ namespace FEXCore { } }; -} // namespace \ No newline at end of file +} // namespace diff --git a/Source/Linux/Utils/ELFContainer.cpp b/Source/Linux/Utils/ELFContainer.cpp index 11720886a..5fae43792 100644 --- a/Source/Linux/Utils/ELFContainer.cpp +++ b/Source/Linux/Utils/ELFContainer.cpp @@ -133,7 +133,7 @@ ELFContainer::ELFContainer(std::string const &Filename, std::string const &RootF //PrintInitArray(); //PrintDynamicTable(); - //LOGMAN_THROW_A_FMT(InterpreterHeader == nullptr, "Can only handle static programs"); + //LOGMAN_THROW_AA_FMT(InterpreterHeader == nullptr, "Can only handle static programs"); } ELFContainer::~ELFContainer() { @@ -191,8 +191,8 @@ bool ELFContainer::LoadELF_32() { memcpy(&Header, reinterpret_cast(&RawFile.at(0)), sizeof(Elf32_Ehdr)); - LOGMAN_THROW_A_FMT(Header._32.e_phentsize == sizeof(Elf32_Phdr), "PH Entry size wasn't correct size"); - LOGMAN_THROW_A_FMT(Header._32.e_shentsize == sizeof(Elf32_Shdr), "PH Entry size wasn't correct size"); + LOGMAN_THROW_AA_FMT(Header._32.e_phentsize == sizeof(Elf32_Phdr), "PH Entry size wasn't correct size"); + LOGMAN_THROW_AA_FMT(Header._32.e_shentsize == sizeof(Elf32_Shdr), "PH Entry size wasn't correct size"); if (Header._32.e_machine != EM_386) { LogMan::Msg::DFmt("32bit ELF wasn't x86 based"); @@ -232,8 +232,8 @@ bool ELFContainer::LoadELF_64() { memcpy(&Header, reinterpret_cast(&RawFile.at(0)), sizeof(Elf64_Ehdr)); - LOGMAN_THROW_A_FMT(Header._64.e_phentsize == 56, "PH Entry size wasn't 56"); - LOGMAN_THROW_A_FMT(Header._64.e_shentsize == 64, "PH Entry size wasn't 64"); + LOGMAN_THROW_AA_FMT(Header._64.e_phentsize == 56, "PH Entry size wasn't 56"); + LOGMAN_THROW_AA_FMT(Header._64.e_shentsize == 64, "PH Entry size wasn't 64"); if (Header._64.e_machine != EM_X86_64) { LogMan::Msg::DFmt("64bit ELF wasn't x86-64 based"); @@ -405,7 +405,7 @@ void ELFContainer::CalculateSymbols() { if (SymTabHeader) { LOGMAN_THROW_A_FMT(SymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(SymTabHeader->sh_entsize == sizeof(Elf32_Sym), + LOGMAN_THROW_AA_FMT(SymTabHeader->sh_entsize == sizeof(Elf32_Sym), "Entry size doesn't match symbol entry"); StringTableHeader = SectionHeaders.at(SymTabHeader->sh_link)._32; @@ -416,7 +416,7 @@ void ELFContainer::CalculateSymbols() { if (DynSymTabHeader) { LOGMAN_THROW_A_FMT(DynSymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(DynSymTabHeader->sh_entsize == sizeof(Elf32_Sym), + LOGMAN_THROW_AA_FMT(DynSymTabHeader->sh_entsize == sizeof(Elf32_Sym), "Entry size doesn't match symbol entry"); DynStringTableHeader = SectionHeaders.at(DynSymTabHeader->sh_link)._32; @@ -538,7 +538,7 @@ void ELFContainer::CalculateSymbols() { if (SymTabHeader) { LOGMAN_THROW_A_FMT(SymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(SymTabHeader->sh_entsize == sizeof(Elf64_Sym), + LOGMAN_THROW_AA_FMT(SymTabHeader->sh_entsize == sizeof(Elf64_Sym), "Entry size doesn't match symbol entry"); StringTableHeader = SectionHeaders.at(SymTabHeader->sh_link)._64; @@ -549,7 +549,7 @@ void ELFContainer::CalculateSymbols() { if (DynSymTabHeader) { LOGMAN_THROW_A_FMT(DynSymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(DynSymTabHeader->sh_entsize == sizeof(Elf64_Sym), + LOGMAN_THROW_AA_FMT(DynSymTabHeader->sh_entsize == sizeof(Elf64_Sym), "Entry size doesn't match symbol entry"); DynStringTableHeader = SectionHeaders.at(DynSymTabHeader->sh_link)._64; @@ -819,7 +819,7 @@ void ELFContainer::PrintSymbolTable() const { LOGMAN_THROW_A_FMT(SymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(SymTabHeader->sh_entsize == sizeof(Elf32_Sym), + LOGMAN_THROW_AA_FMT(SymTabHeader->sh_entsize == sizeof(Elf32_Sym), "Entry size doesn't match symbol entry"); StringTableHeader = SectionHeaders.at(SymTabHeader->sh_link)._32; @@ -854,7 +854,7 @@ void ELFContainer::PrintSymbolTable() const { LOGMAN_THROW_A_FMT(SymTabHeader->sh_link < SectionHeaders.size(), "Symbol table string table section is wrong"); - LOGMAN_THROW_A_FMT(SymTabHeader->sh_entsize == sizeof(Elf64_Sym), + LOGMAN_THROW_AA_FMT(SymTabHeader->sh_entsize == sizeof(Elf64_Sym), "Entry size doesn't match symbol entry"); StringTableHeader = SectionHeaders.at(SymTabHeader->sh_link)._64; @@ -917,7 +917,7 @@ void ELFContainer::PrintRelocationTable() const { LogMan::Msg::DFmt("\toffset: 0x{:x}", Entry->r_offset); LogMan::Msg::DFmt("\tSym: 0x{:x}", Sym); if (DynSymHeader && Sym != 0) { - LOGMAN_THROW_A_FMT(DynSymHeader->sh_entsize == sizeof(Elf64_Sym), "Oops, entry size doesn't match"); + LOGMAN_THROW_AA_FMT(DynSymHeader->sh_entsize == sizeof(Elf64_Sym), "Oops, entry size doesn't match"); const uint64_t offset = DynSymHeader->sh_offset + Sym * DynSymHeader->sh_entsize; const auto *Symbol = reinterpret_cast(&RawFile.at(offset)); @@ -999,7 +999,7 @@ void ELFContainer::FixupRelocations(void *ELFBase, uint64_t GuestELFBase, Symbol const Elf64_Sym *EntrySymbol{nullptr}; const char *EntrySymbolName{nullptr}; if (DynSymHeader && Sym != 0) { - LOGMAN_THROW_A_FMT(DynSymHeader->sh_entsize == sizeof(Elf64_Sym), "Oops, entry size doesn't match"); + LOGMAN_THROW_AA_FMT(DynSymHeader->sh_entsize == sizeof(Elf64_Sym), "Oops, entry size doesn't match"); const uint64_t offset = DynSymHeader->sh_offset + Sym * DynSymHeader->sh_entsize; EntrySymbol = reinterpret_cast(&RawFile.at(offset)); diff --git a/Source/Tests/ELFCodeLoader.h b/Source/Tests/ELFCodeLoader.h index fd5bbfe06..edb539f7e 100644 --- a/Source/Tests/ELFCodeLoader.h +++ b/Source/Tests/ELFCodeLoader.h @@ -282,7 +282,7 @@ public: bool MapMemory(const MapperFn& Mapper, const UnmapperFn& Unmapper) override { auto DoMMap = [&Mapper](uint64_t Address, size_t Size, bool FixedNoReplace) -> void* { void *Result = Mapper(reinterpret_cast(Address), Size, PROT_READ | PROT_WRITE, (FixedNoReplace ? MAP_FIXED_NOREPLACE : MAP_FIXED) | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - LOGMAN_THROW_A_FMT(Result != (void*)~0ULL, "Couldn't mmap"); + LOGMAN_THROW_AA_FMT(Result != (void*)~0ULL, "Couldn't mmap"); return Result; }; diff --git a/Source/Tests/HarnessHelpers.h b/Source/Tests/HarnessHelpers.h index 1c2d19433..5eb09fd11 100644 --- a/Source/Tests/HarnessHelpers.h +++ b/Source/Tests/HarnessHelpers.h @@ -383,7 +383,7 @@ namespace FEX::HarnessHelper { } else { uint64_t Result = reinterpret_cast(FEXCore::Allocator::mmap(reinterpret_cast(STACK_OFFSET), STACK_SIZE, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); - LOGMAN_THROW_A_FMT(Result != ~0ULL, "Stack Pointer mmap failed"); + LOGMAN_THROW_AA_FMT(Result != ~0ULL, "Stack Pointer mmap failed"); return Result + STACK_SIZE; } } @@ -396,7 +396,7 @@ namespace FEX::HarnessHelper { bool LimitedSize = true; auto DoMMap = [&Mapper](uint64_t Address, size_t Size) -> void* { void *Result = Mapper(reinterpret_cast(Address), Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); - LOGMAN_THROW_A_FMT(Result == reinterpret_cast(Address), "Map Memory mmap failed"); + LOGMAN_THROW_AA_FMT(Result == reinterpret_cast(Address), "Map Memory mmap failed"); return Result; }; diff --git a/Source/Tests/LinuxSyscalls/SignalDelegator.cpp b/Source/Tests/LinuxSyscalls/SignalDelegator.cpp index e0ecac16a..184a3ebb8 100644 --- a/Source/Tests/LinuxSyscalls/SignalDelegator.cpp +++ b/Source/Tests/LinuxSyscalls/SignalDelegator.cpp @@ -253,7 +253,7 @@ namespace FEX::HLE { SignalDelegator::SignalDelegator() { // Register this delegate - LOGMAN_THROW_A_FMT(!GlobalDelegator, "Can't register global delegator multiple times!"); + LOGMAN_THROW_AA_FMT(!GlobalDelegator, "Can't register global delegator multiple times!"); GlobalDelegator = this; // Signal zero isn't real HostHandlers[0].Installed = true; @@ -309,7 +309,7 @@ namespace FEX::HLE { altstack.ss_sp = ThreadData.AltStackPtr; altstack.ss_size = SIGSTKSZ * 16; altstack.ss_flags = 0; - LOGMAN_THROW_A_FMT(!!altstack.ss_sp, "Couldn't allocate stack pointer"); + LOGMAN_THROW_AA_FMT(!!altstack.ss_sp, "Couldn't allocate stack pointer"); // Register the alt stack const int Result = sigaltstack(&altstack, nullptr); diff --git a/Source/Tests/LinuxSyscalls/SyscallsSMCTracking.cpp b/Source/Tests/LinuxSyscalls/SyscallsSMCTracking.cpp index 57d31b68d..3fa50df9a 100644 --- a/Source/Tests/LinuxSyscalls/SyscallsSMCTracking.cpp +++ b/Source/Tests/LinuxSyscalls/SyscallsSMCTracking.cpp @@ -71,7 +71,7 @@ bool SyscallHandler::HandleSegfault(FEXCore::Core::InternalThreadState *Thread, auto Offset = FaultBase - Entry->first + Entry->second.Offset; auto VMA = Entry->second.Resource->FirstVMA; - LOGMAN_THROW_A_FMT(VMA, "VMA tracking error"); + LOGMAN_THROW_AA_FMT(VMA, "VMA tracking error"); // Flush all mirrors, remap the page writable as needed do { @@ -81,7 +81,7 @@ bool SyscallHandler::HandleSegfault(FEXCore::Core::InternalThreadState *Thread, if (VMA->Prot.Writable) { FEXCore::Context::InvalidateGuestCodeRange(CTX, FaultBaseMirrored, FHU::FEX_PAGE_SIZE, [](uintptr_t Start, uintptr_t Length) { auto rv = mprotect((void *)Start, Length, PROT_READ | PROT_WRITE); - LogMan::Throw::AFmt(rv == 0, "mprotect({}, {}) failed", Start, Length); + LogMan::Throw::AAFmt(rv == 0, "mprotect({}, {}) failed", Start, Length); }); } else { FEXCore::Context::InvalidateGuestCodeRange(CTX, FaultBaseMirrored, FHU::FEX_PAGE_SIZE); @@ -91,7 +91,7 @@ bool SyscallHandler::HandleSegfault(FEXCore::Core::InternalThreadState *Thread, } else { FEXCore::Context::InvalidateGuestCodeRange(CTX, FaultBase, FHU::FEX_PAGE_SIZE, [](uintptr_t Start, uintptr_t Length) { auto rv = mprotect((void *)Start, Length, PROT_READ | PROT_WRITE); - LogMan::Throw::AFmt(rv == 0, "mprotect({}, {}) failed", Start, Length); + LogMan::Throw::AAFmt(rv == 0, "mprotect({}, {}) failed", Start, Length); }); } @@ -134,7 +134,7 @@ void SyscallHandler::MarkGuestExecutableRange(uint64_t Start, uint64_t Length) { const auto OffsetTop = OffsetBase + ProtectSize; auto VMA = Mapping->second.Resource->FirstVMA; - LOGMAN_THROW_A_FMT(VMA, "VMA tracking error"); + LOGMAN_THROW_AA_FMT(VMA, "VMA tracking error"); do { auto VMAOffsetBase = VMA->Offset; @@ -147,14 +147,14 @@ void SyscallHandler::MarkGuestExecutableRange(uint64_t Start, uint64_t Length) { const auto MirroredSize = std::min(OffsetTop, VMAOffsetTop) - MirroredBase; auto rv = mprotect((void *)(MirroredBase - VMAOffsetBase + VMABase), MirroredSize, PROT_READ); - LogMan::Throw::AFmt(rv == 0, "mprotect({}, {}) failed", MirroredBase, MirroredSize); + LogMan::Throw::AAFmt(rv == 0, "mprotect({}, {}) failed", MirroredBase, MirroredSize); } } while ((VMA = VMA->ResourceNextVMA)); } else if (Mapping->second.Prot.Writable) { int rv = mprotect((void *)ProtectBase, ProtectSize, PROT_READ); - LogMan::Throw::AFmt(rv == 0, "mprotect({}, {}) failed", ProtectBase, ProtectSize); + LogMan::Throw::AAFmt(rv == 0, "mprotect({}, {}) failed", ProtectBase, ProtectSize); } } } @@ -213,7 +213,7 @@ void SyscallHandler::TrackMmap(uintptr_t Base, uintptr_t Size, int Prot, int Fla MRID mrid{SpecialDev::Anon, AnonSharedId++}; auto [Iter, Inserted] = VMATracking.MappedResources.emplace(mrid, MappedResource{nullptr, nullptr, 0}); - LOGMAN_THROW_A_FMT(Inserted == true, "VMA tracking error"); + LOGMAN_THROW_AA_FMT(Inserted == true, "VMA tracking error"); Resource = &Iter->second; Resource->Iterator = Iter; } else { @@ -276,8 +276,8 @@ void SyscallHandler::TrackMremap(uintptr_t OldAddress, size_t OldSize, size_t Ne if (OldSize == 0) { // Mirror existing mapping // must be a shared mapping - LOGMAN_THROW_A_FMT(OldResource != nullptr, "VMA Tracking error"); - LOGMAN_THROW_A_FMT(OldFlags.Shared, "VMA Tracking error"); + LOGMAN_THROW_AA_FMT(OldResource != nullptr, "VMA Tracking error"); + LOGMAN_THROW_AA_FMT(OldFlags.Shared, "VMA Tracking error"); VMATracking.SetUnsafe(CTX, OldResource, NewAddress, OldOffset, NewSize, OldFlags, OldProt); } else { @@ -315,7 +315,7 @@ void SyscallHandler::TrackShmat(int shmid, uintptr_t Base, int shmflg) { shmid_ds stat; auto res = shmctl(shmid, IPC_STAT, &stat); - LOGMAN_THROW_A_FMT(res != -1, "shmctl IPC_STAT failed"); + LOGMAN_THROW_AA_FMT(res != -1, "shmctl IPC_STAT failed"); uint64_t Length = stat.shm_segsz; diff --git a/Source/Tests/LinuxSyscalls/x32/FD.cpp b/Source/Tests/LinuxSyscalls/x32/FD.cpp index 46af711aa..07818d44f 100644 --- a/Source/Tests/LinuxSyscalls/x32/FD.cpp +++ b/Source/Tests/LinuxSyscalls/x32/FD.cpp @@ -451,7 +451,7 @@ namespace FEX::HLE::x32 { }); REGISTER_SYSCALL_IMPL_X32(fstatfs64, [](FEXCore::Core::CpuStateFrame *Frame, int fd, size_t sz, struct statfs64_32 *buf) -> uint64_t { - LOGMAN_THROW_A_FMT(sz == sizeof(struct statfs64_32), "This needs to match"); + LOGMAN_THROW_AA_FMT(sz == sizeof(struct statfs64_32), "This needs to match"); struct statfs64 host_stat; uint64_t Result = ::fstatfs64(fd, &host_stat); @@ -462,7 +462,7 @@ namespace FEX::HLE::x32 { }); REGISTER_SYSCALL_IMPL_X32(statfs64, [](FEXCore::Core::CpuStateFrame *Frame, const char *path, size_t sz, struct statfs64_32 *buf) -> uint64_t { - LOGMAN_THROW_A_FMT(sz == sizeof(struct statfs64_32), "This needs to match"); + LOGMAN_THROW_AA_FMT(sz == sizeof(struct statfs64_32), "This needs to match"); struct statfs host_stat; uint64_t Result = FEX::HLE::_SyscallHandler->FM.Statfs(path, &host_stat); diff --git a/Source/Tests/LinuxSyscalls/x32/Memory.cpp b/Source/Tests/LinuxSyscalls/x32/Memory.cpp index 1c6c38c55..623cdbfc9 100644 --- a/Source/Tests/LinuxSyscalls/x32/Memory.cpp +++ b/Source/Tests/LinuxSyscalls/x32/Memory.cpp @@ -21,11 +21,11 @@ $end_info$ namespace FEX::HLE::x32 { void *x32SyscallHandler::GuestMmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { - LOGMAN_THROW_A_FMT((length >> 32) == 0, "values must fit to 32 bits"); + LOGMAN_THROW_AA_FMT((length >> 32) == 0, "values must fit to 32 bits"); auto Result = (uint64_t)GetAllocator()->mmap((void*)addr, length, prot, flags, fd, offset); - LOGMAN_THROW_A_FMT((Result >> 32) == 0|| (Result >> 32) == 0xFFFFFFFF, "values must fit to 32 bits"); + LOGMAN_THROW_AA_FMT((Result >> 32) == 0|| (Result >> 32) == 0xFFFFFFFF, "values must fit to 32 bits"); if (!FEX::HLE::HasSyscallError(Result)) { FEX::HLE::_SyscallHandler->TrackMmap(Result, length, prot, flags, fd, offset); @@ -37,8 +37,8 @@ namespace FEX::HLE::x32 { } int x32SyscallHandler::GuestMunmap(void *addr, uint64_t length) { - LOGMAN_THROW_A_FMT((uintptr_t(addr) >> 32) == 0, "values must fit to 32 bits"); - LOGMAN_THROW_A_FMT((length >> 32) == 0, "values must fit to 32 bits"); + LOGMAN_THROW_AA_FMT((uintptr_t(addr) >> 32) == 0, "values must fit to 32 bits"); + LOGMAN_THROW_AA_FMT((length >> 32) == 0, "values must fit to 32 bits"); auto Result = GetAllocator()->munmap(addr, length);