diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
index 694299c19..ae917b6a4 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
@@ -545,7 +545,7 @@ Arm64JITCore::~Arm64JITCore() {
   FreeCodeBuffer(InitialCodeBuffer);
 }
 
-static IR::PhysicalRegister GetPhys(IR::RegisterAllocationData *RAData, uint32_t Node) {
+IR::PhysicalRegister Arm64JITCore::GetPhys(uint32_t Node) {
   auto PhyReg = RAData->GetNodeRegister(Node);
 
   LogMan::Throw::A(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa%d. Class: %d", Node, PhyReg.Class);
@@ -555,7 +555,8 @@ static IR::PhysicalRegister GetPhys(IR::RegisterAllocationData *RAData, uint32_t
 
 template<>
 aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(uint32_t Node) {
-auto Reg = GetPhys(RAData, Node);
+  auto Reg = GetPhys(Node);
+
   if (Reg.Class == IR::GPRFixedClass.Val) {
     return SRA64[Reg.Reg].W();
   } else if (Reg.Class == IR::GPRClass.Val) {
@@ -568,7 +569,8 @@ auto Reg = GetPhys(RAData, Node);
 
 template<>
 aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(uint32_t Node) {
-  auto Reg = GetPhys(RAData, Node);
+  auto Reg = GetPhys(Node);
+
   if (Reg.Class == IR::GPRFixedClass.Val) {
     return SRA64[Reg.Reg];
   } else if (Reg.Class == IR::GPRClass.Val) {
@@ -581,18 +583,19 @@ aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(uint32_t Node) {
 
 template<>
 std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_32>(uint32_t Node) {
-  uint32_t Reg = GetPhys(RAData, Node).Reg;
+  uint32_t Reg = GetPhys(Node).Reg;
   return RA32Pair[Reg];
 }
 
 template<>
 std::pair<aarch64::Register, aarch64::Register> Arm64JITCore::GetSrcPair<Arm64JITCore::RA_64>(uint32_t Node) {
-  uint32_t Reg = GetPhys(RAData, Node).Reg;
+  uint32_t Reg = GetPhys(Node).Reg;
   return RA64Pair[Reg];
 }
 
 aarch64::VRegister Arm64JITCore::GetSrc(uint32_t Node) {
-  auto Reg = GetPhys(RAData, Node);
+  auto Reg = GetPhys(Node);
+
   if (Reg.Class == IR::FPRFixedClass.Val) {
     return SRAFPR[Reg.Reg];
   } else if (Reg.Class == IR::FPRClass.Val) {
@@ -604,7 +607,8 @@ aarch64::VRegister Arm64JITCore::GetSrc(uint32_t Node) {
 }
 
 aarch64::VRegister Arm64JITCore::GetDst(uint32_t Node) {
-  auto Reg = GetPhys(RAData, Node);
+  auto Reg = GetPhys(Node);
+
   if (Reg.Class == IR::FPRFixedClass.Val) {
     return SRAFPR[Reg.Reg];
   } else if (Reg.Class == IR::FPRClass.Val) {
@@ -644,7 +648,7 @@ bool Arm64JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode,
 }
 
 FEXCore::IR::RegisterClassType Arm64JITCore::GetRegClass(uint32_t Node) {
-  return FEXCore::IR::RegisterClassType {GetPhys(RAData, Node).Class};
+  return FEXCore::IR::RegisterClassType {GetPhys(Node).Class};
 }
 
 
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
index 35d8e8e2d..683681d40 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
@@ -113,6 +113,8 @@ private:
 
   FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node);
 
+  IR::PhysicalRegister GetPhys(uint32_t Node);
+
   bool IsFPR(uint32_t Node);
   bool IsGPR(uint32_t Node);