From b6f6c84790cb4f9486cf2c2ebe21a734583cf5e9 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Mon, 23 Oct 2023 14:26:51 -0400
Subject: [PATCH] IR: Optimize tests

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp | 8 ++------
 FEXCore/Source/Interface/Core/OpcodeDispatcher.h   | 5 +++--
 FEXCore/Source/Interface/IR/IR.json                | 7 +++----
 FEXCore/Source/Interface/IR/Passes/ConstProp.cpp   | 3 +++
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
index 9e9e1ebea..5ee9d1cc6 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -156,20 +156,16 @@ DEF_OP(TestNZ) {
   const uint8_t OpSize = Op->Size;
   const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
 
-  const auto Dst = GetReg(Node);
   auto Src = GetReg(Op->Src1.ID());
 
   // Shift the sign bit into place, clearing out the garbage in upper bits.
   // setf+rmif would avoid the scratch register, but higher latency on M1.
   if (OpSize < 4) {
-    lsl(EmitSize, Dst, Src, 32 - (OpSize * 8));
-    Src = Dst;
+    lsl(EmitSize, TMP1, Src, 32 - (OpSize * 8));
+    Src = TMP1;
   }
 
   tst(EmitSize, Src, Src);
-
-  // TODO: Optimize this out
-  mrs(Dst, ARMEmitter::SystemRegister::NZCV);
 }
 
 DEF_OP(Sub) {
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
index 398abd5bd..75b66d0d2 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -1301,9 +1301,10 @@ private:
   }
 
   void SetNZ_ZeroCV(unsigned SrcSize, OrderedNode *Res) {
-    CachedNZCV = _TestNZ(SrcSize, Res);
+    _TestNZ(SrcSize, Res);
+    CachedNZCV = _LoadNZCV();
     PossiblySetNZCVBits = (1u << 31) | (1u << 30);
-    NZCVDirty = true;
+    NZCVDirty = false;
   }
 
   OrderedNode *InsertNZCV(OrderedNode *NZCV, unsigned BitOffset, OrderedNode *Value) {
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index b90b212b5..21402dff3 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -1072,10 +1072,9 @@
           "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
         ]
       },
-      "GPR = TestNZ u8:$Size, GPR:$Src1": {
-        "Desc": ["Return NZCV for a GPR, setting N and Z accordingly and zeroing C and V"],
-        "ImplicitFlagClobber": true,
-        "DestSize": "4"
+      "TestNZ u8:$Size, GPR:$Src1": {
+        "Desc": ["Set NZCV for a GPR, setting N and Z accordingly and zeroing C and V"],
+        "HasSideEffects": true
       },
       "GPR = Lshl OpSize:#Size, GPR:$Src1, GPR:$Src2": {
         "Desc": ["Integer logical shift left"
diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
index 272463344..6c871770e 100644
--- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
@@ -669,6 +669,8 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       }
     break;
     }
+    /* TODO: restore this when we have rmif or something? */
+#if 0
     case OP_TESTNZ: {
       auto Op = IROp->CW<IR::IROp_TestNZ>();
       uint64_t Constant1{};
@@ -683,6 +685,7 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       }
     break;
     }
+#endif
     case OP_OR: {
       auto Op = IROp->CW<IR::IROp_Or>();
       uint64_t Constant1{};