From b5c83f0628272de71b3d20ecd37d6fbd9a238a11 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 9 Nov 2023 14:44:39 -0400 Subject: [PATCH] JIT: Optimize 8/16-bit TestNZ This is cursed. I blame the darling. Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 092e4354a..4cfcf46c8 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -128,13 +128,14 @@ DEF_OP(TestNZ) { auto Src = GetReg(Op->Src1.ID()); // Shift the sign bit into place, clearing out the garbage in upper bits. - // setf+rmif would avoid the scratch register, but higher latency on M1. + // Adding zero does an effective test, setting NZ according to the result and + // zeroing CV. if (OpSize < 4) { - lsl(EmitSize, TMP1, Src, 32 - (OpSize * 8)); - Src = TMP1; + unsigned Shift = 32 - (OpSize * 8); + cmn(EmitSize, ARMEmitter::Reg::zr, Src, ARMEmitter::ShiftType::LSL, Shift); + } else { + tst(EmitSize, Src, Src); } - - tst(EmitSize, Src, Src); } DEF_OP(Sub) {